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authorYoshihiro Shimoda <shimoda.yoshihiro@renesas.com>2008-07-07 08:11:54 -0400
committerPaul Mundt <lethal@linux-sh.org>2008-07-28 05:10:34 -0400
commitcafd63b0076b78bc8f114abbeb724c7e5f5bfe5d (patch)
treee12be13bbac6d45260f9aa0c507a2712ac272c79 /arch/sh/boards/se/7343/irq.c
parenta4e1d08491b06b17eb77c92caacd40b330ca8146 (diff)
sh: update Solution Engine 7343
updated the following codes for Solution Endine 7343: - fix compile error in arch/sh/boards/se/7343/irq.c - add nor flash physmaps - update defconfig Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/boards/se/7343/irq.c')
-rw-r--r--arch/sh/boards/se/7343/irq.c232
1 files changed, 55 insertions, 177 deletions
diff --git a/arch/sh/boards/se/7343/irq.c b/arch/sh/boards/se/7343/irq.c
index 763f6deba81..1112e86aa93 100644
--- a/arch/sh/boards/se/7343/irq.c
+++ b/arch/sh/boards/se/7343/irq.c
@@ -1,202 +1,80 @@
1/* 1/*
2 * arch/sh/boards/se/7343/irq.c 2 * linux/arch/sh/boards/se/7343/irq.c
3 * 3 *
4 * Copyright (C) 2008 Yoshihiro Shimoda
5 *
6 * Based on linux/arch/sh/boards/se/7722/irq.c
7 * Copyright (C) 2007 Nobuhiro Iwamatsu
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
4 */ 12 */
5#include <linux/init.h> 13#include <linux/init.h>
6#include <linux/interrupt.h>
7#include <linux/irq.h> 14#include <linux/irq.h>
15#include <linux/interrupt.h>
8#include <asm/irq.h> 16#include <asm/irq.h>
9#include <asm/io.h> 17#include <asm/io.h>
10#include <asm/mach/se7343.h> 18#include <asm/se7343.h>
11 19
12static void 20static void disable_se7343_irq(unsigned int irq)
13disable_intreq_irq(unsigned int irq)
14{ 21{
15 int bit = irq - OFFCHIP_IRQ_BASE; 22 unsigned int bit = irq - SE7343_FPGA_IRQ_BASE;
16 u16 val; 23 ctrl_outw(ctrl_inw(PA_CPLD_IMSK) | 1 << bit, PA_CPLD_IMSK);
17
18 val = ctrl_inw(PA_CPLD_IMSK);
19 val |= 1 << bit;
20 ctrl_outw(val, PA_CPLD_IMSK);
21} 24}
22 25
23static void 26static void enable_se7343_irq(unsigned int irq)
24enable_intreq_irq(unsigned int irq)
25{ 27{
26 int bit = irq - OFFCHIP_IRQ_BASE; 28 unsigned int bit = irq - SE7343_FPGA_IRQ_BASE;
27 u16 val; 29 ctrl_outw(ctrl_inw(PA_CPLD_IMSK) & ~(1 << bit), PA_CPLD_IMSK);
28
29 val = ctrl_inw(PA_CPLD_IMSK);
30 val &= ~(1 << bit);
31 ctrl_outw(val, PA_CPLD_IMSK);
32} 30}
33 31
34static void 32static struct irq_chip se7343_irq_chip __read_mostly = {
35mask_and_ack_intreq_irq(unsigned int irq) 33 .name = "SE7343-FPGA",
36{ 34 .mask = disable_se7343_irq,
37 disable_intreq_irq(irq); 35 .unmask = enable_se7343_irq,
38} 36 .mask_ack = disable_se7343_irq,
39
40static unsigned int
41startup_intreq_irq(unsigned int irq)
42{
43 enable_intreq_irq(irq);
44 return 0;
45}
46
47static void
48shutdown_intreq_irq(unsigned int irq)
49{
50 disable_intreq_irq(irq);
51}
52
53static void
54end_intreq_irq(unsigned int irq)
55{
56 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
57 enable_intreq_irq(irq);
58}
59
60static struct hw_interrupt_type intreq_irq_type = {
61 .typename = "FPGA-IRQ",
62 .startup = startup_intreq_irq,
63 .shutdown = shutdown_intreq_irq,
64 .enable = enable_intreq_irq,
65 .disable = disable_intreq_irq,
66 .ack = mask_and_ack_intreq_irq,
67 .end = end_intreq_irq
68}; 37};
69 38
70static void 39static void se7343_irq_demux(unsigned int irq, struct irq_desc *desc)
71make_intreq_irq(unsigned int irq)
72{
73 disable_irq_nosync(irq);
74 irq_desc[irq].chip = &intreq_irq_type;
75 disable_intreq_irq(irq);
76}
77
78int
79shmse_irq_demux(int irq)
80{ 40{
81 int bit; 41 unsigned short intv = ctrl_inw(PA_CPLD_ST);
82 volatile u16 val; 42 struct irq_desc *ext_desc;
83 43 unsigned int ext_irq = SE7343_FPGA_IRQ_BASE;
84 if (irq == IRQ5_IRQ) { 44
85 /* Read status Register */ 45 intv &= (1 << SE7343_FPGA_IRQ_NR) - 1;
86 val = ctrl_inw(PA_CPLD_ST); 46
87 bit = ffs(val); 47 while (intv) {
88 if (bit != 0) 48 if (intv & 1) {
89 return OFFCHIP_IRQ_BASE + bit - 1; 49 ext_desc = irq_desc + ext_irq;
50 handle_level_irq(ext_irq, ext_desc);
51 }
52 intv >>= 1;
53 ext_irq++;
90 } 54 }
91 return irq;
92} 55}
93 56
94/* IRQ5 is multiplexed between the following sources:
95 * 1. PC Card socket
96 * 2. Extension slot
97 * 3. USB Controller
98 * 4. Serial Controller
99 *
100 * We configure IRQ5 as a cascade IRQ.
101 */
102static struct irqaction irq5 = {
103 .handler = no_action,
104 .mask = CPU_MASK_NONE,
105 .name = "IRQ5-cascade",
106};
107
108static struct ipr_data se7343_irq5_ipr_map[] = {
109 { IRQ5_IRQ, IRQ5_IPR_ADDR+2, IRQ5_IPR_POS, IRQ5_PRIORITY },
110};
111static struct ipr_data se7343_siof0_vpu_ipr_map[] = {
112 { SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY },
113 { VPU_IRQ, VPU_IPR_ADDR, VPU_IPR_POS, 8 },
114};
115static struct ipr_data se7343_other_ipr_map[] = {
116 { DMTE0_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
117 { DMTE1_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
118 { DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
119 { DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
120 { DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY },
121 { DMTE5_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY },
122
123 /* I2C block */
124 { IIC0_ALI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
125 { IIC0_TACKI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
126 { IIC0_WAITI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
127 { IIC0_DTEI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
128
129 { IIC1_ALI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY },
130 { IIC1_TACKI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY },
131 { IIC1_WAITI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY },
132 { IIC1_DTEI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY },
133
134 /* SIOF */
135 { SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY },
136
137 /* SIU */
138 { SIU_IRQ, SIU_IPR_ADDR, SIU_IPR_POS, SIU_PRIORITY },
139
140 /* VIO interrupt */
141 { CEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
142 { BEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
143 { VEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
144
145 /*MFI interrupt*/
146
147 { MFI_IRQ, MFI_IPR_ADDR, MFI_IPR_POS, MFI_PRIORITY },
148
149 /* LCD controller */
150 { LCDC_IRQ, LCDC_IPR_ADDR, LCDC_IPR_POS, LCDC_PRIORITY },
151};
152
153/* 57/*
154 * Initialize IRQ setting 58 * Initialize IRQ setting
155 */ 59 */
156void __init 60void __init init_7343se_IRQ(void)
157init_7343se_IRQ(void)
158{ 61{
159 /* Setup Multiplexed interrupts */ 62 int i;
160 ctrl_outw(8, PA_CPLD_MODESET); /* Set all CPLD interrupts to active 63
161 * low. 64 ctrl_outw(0, PA_CPLD_IMSK); /* disable all irqs */
162 */ 65 ctrl_outw(0x2000, 0xb03fffec); /* mrshpc irq enable */
163 /* Mask all CPLD controller interrupts */ 66
164 ctrl_outw(0x0fff, PA_CPLD_IMSK); 67 for (i = 0; i < SE7343_FPGA_IRQ_NR; i++)
165 68 set_irq_chip_and_handler_name(SE7343_FPGA_IRQ_BASE + i,
166 /* PC Card interrupts */ 69 &se7343_irq_chip,
167 make_intreq_irq(PC_IRQ0); 70 handle_level_irq, "level");
168 make_intreq_irq(PC_IRQ1); 71
169 make_intreq_irq(PC_IRQ2); 72 set_irq_chained_handler(IRQ0_IRQ, se7343_irq_demux);
170 make_intreq_irq(PC_IRQ3); 73 set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
171 74 set_irq_chained_handler(IRQ1_IRQ, se7343_irq_demux);
172 /* Extension Slot Interrupts */ 75 set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
173 make_intreq_irq(EXT_IRQ0); 76 set_irq_chained_handler(IRQ4_IRQ, se7343_irq_demux);
174 make_intreq_irq(EXT_IRQ1); 77 set_irq_type(IRQ4_IRQ, IRQ_TYPE_LEVEL_LOW);
175 make_intreq_irq(EXT_IRQ2); 78 set_irq_chained_handler(IRQ5_IRQ, se7343_irq_demux);
176 make_intreq_irq(EXT_IRQ3); 79 set_irq_type(IRQ5_IRQ, IRQ_TYPE_LEVEL_LOW);
177
178 /* USB Controller interrupts */
179 make_intreq_irq(USB_IRQ0);
180 make_intreq_irq(USB_IRQ1);
181
182 /* Serial Controller interrupts */
183 make_intreq_irq(UART_IRQ0);
184 make_intreq_irq(UART_IRQ1);
185
186 /* Setup all external interrupts to be active low */
187 ctrl_outw(0xaaaa, INTC_ICR1);
188
189 make_ipr_irq(se7343_irq5_ipr_map, ARRAY_SIZE(se7343_irq5_ipr_map));
190
191 setup_irq(IRQ5_IRQ, &irq5);
192 /* Set port control to use IRQ5 */
193 *(u16 *)0xA4050108 &= ~0xc;
194
195 make_ipr_irq(se7343_siof0_vpu_ipr_map, ARRAY_SIZE(se7343_siof0_vpu_ipr_map));
196
197 ctrl_outb(0x0f, INTC_IMCR5); /* enable SCIF IRQ */
198
199 make_ipr_irq(se7343_other_ipr_map, ARRAY_SIZE(se7343_other_ipr_map));
200
201 ctrl_outw(0x2000, PA_MRSHPC + 0x0c); /* mrshpc irq enable */
202} 80}
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