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| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2010-05-06 21:29:25 -0400 |
|---|---|---|
| committer | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2010-05-06 21:29:25 -0400 |
| commit | 1ed31d6db90d51010545921e59d369d2f92b7ac2 (patch) | |
| tree | 358a0b346bc8135cd5e53700eb44308b1a7c8c5b /arch/s390/kernel/vdso64/clock_gettime.S | |
| parent | ceba1abcb00b0ef0b1efcd715285f6e05523edef (diff) | |
| parent | 722154e4cacf015161efe60009ae9be23d492296 (diff) | |
Merge commit 'origin/master' into next
Diffstat (limited to 'arch/s390/kernel/vdso64/clock_gettime.S')
| -rw-r--r-- | arch/s390/kernel/vdso64/clock_gettime.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/s390/kernel/vdso64/clock_gettime.S b/arch/s390/kernel/vdso64/clock_gettime.S index 49106c6e6f8..f40467884a0 100644 --- a/arch/s390/kernel/vdso64/clock_gettime.S +++ b/arch/s390/kernel/vdso64/clock_gettime.S | |||
| @@ -36,7 +36,7 @@ __kernel_clock_gettime: | |||
| 36 | stck 48(%r15) /* Store TOD clock */ | 36 | stck 48(%r15) /* Store TOD clock */ |
| 37 | lg %r1,48(%r15) | 37 | lg %r1,48(%r15) |
| 38 | sg %r1,__VDSO_XTIME_STAMP(%r5) /* TOD - cycle_last */ | 38 | sg %r1,__VDSO_XTIME_STAMP(%r5) /* TOD - cycle_last */ |
| 39 | mghi %r1,1000 | 39 | msgf %r1,__VDSO_NTP_MULT(%r5) /* * NTP adjustment */ |
| 40 | srlg %r1,%r1,12 /* cyc2ns(clock,cycle_delta) */ | 40 | srlg %r1,%r1,12 /* cyc2ns(clock,cycle_delta) */ |
| 41 | alg %r1,__VDSO_XTIME_NSEC(%r5) /* + xtime */ | 41 | alg %r1,__VDSO_XTIME_NSEC(%r5) /* + xtime */ |
| 42 | lg %r0,__VDSO_XTIME_SEC(%r5) | 42 | lg %r0,__VDSO_XTIME_SEC(%r5) |
| @@ -64,7 +64,7 @@ __kernel_clock_gettime: | |||
| 64 | stck 48(%r15) /* Store TOD clock */ | 64 | stck 48(%r15) /* Store TOD clock */ |
| 65 | lg %r1,48(%r15) | 65 | lg %r1,48(%r15) |
| 66 | sg %r1,__VDSO_XTIME_STAMP(%r5) /* TOD - cycle_last */ | 66 | sg %r1,__VDSO_XTIME_STAMP(%r5) /* TOD - cycle_last */ |
| 67 | mghi %r1,1000 | 67 | msgf %r1,__VDSO_NTP_MULT(%r5) /* * NTP adjustment */ |
| 68 | srlg %r1,%r1,12 /* cyc2ns(clock,cycle_delta) */ | 68 | srlg %r1,%r1,12 /* cyc2ns(clock,cycle_delta) */ |
| 69 | alg %r1,__VDSO_XTIME_NSEC(%r5) /* + xtime */ | 69 | alg %r1,__VDSO_XTIME_NSEC(%r5) /* + xtime */ |
| 70 | lg %r0,__VDSO_XTIME_SEC(%r5) | 70 | lg %r0,__VDSO_XTIME_SEC(%r5) |