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authorMichael Ellerman <michael@ellerman.id.au>2005-08-08 21:13:36 -0400
committerPaul Mackerras <paulus@samba.org>2005-08-28 20:53:38 -0400
commit180a33627d958d5d9d3602dde6ac74b315e136f0 (patch)
tree2c480741288f1f27ff3b65a95bb67fdf2f206a8f /arch/ppc64/kernel/pmc.c
parentb13cfd173f73c3f6f9a307b7b6e64d45fbd756b2 (diff)
[PATCH] ppc64: Move ppc64_enable_pmcs() logic into a ppc_md function
This patch moves power4_enable_pmcs() to arch/ppc64/kernel/pmc.c. I've tested it on P5 LPAR and P4. It does what it used to. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/ppc64/kernel/pmc.c')
-rw-r--r--arch/ppc64/kernel/pmc.c21
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/ppc64/kernel/pmc.c b/arch/ppc64/kernel/pmc.c
index 67be773f9c0..cdfec7438d0 100644
--- a/arch/ppc64/kernel/pmc.c
+++ b/arch/ppc64/kernel/pmc.c
@@ -65,3 +65,24 @@ void release_pmc_hardware(void)
65 spin_unlock(&pmc_owner_lock); 65 spin_unlock(&pmc_owner_lock);
66} 66}
67EXPORT_SYMBOL_GPL(release_pmc_hardware); 67EXPORT_SYMBOL_GPL(release_pmc_hardware);
68
69void power4_enable_pmcs(void)
70{
71 unsigned long hid0;
72
73 hid0 = mfspr(HID0);
74 hid0 |= 1UL << (63 - 20);
75
76 /* POWER4 requires the following sequence */
77 asm volatile(
78 "sync\n"
79 "mtspr %1, %0\n"
80 "mfspr %0, %1\n"
81 "mfspr %0, %1\n"
82 "mfspr %0, %1\n"
83 "mfspr %0, %1\n"
84 "mfspr %0, %1\n"
85 "mfspr %0, %1\n"
86 "isync" : "=&r" (hid0) : "i" (HID0), "0" (hid0):
87 "memory");
88}