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authorPaul Mackerras <paulus@samba.org>2006-01-15 01:30:44 -0500
committerPaul Mackerras <paulus@samba.org>2006-01-15 01:30:44 -0500
commita7fdd90bc43e3e9cb08bc1b13650024d419b89e5 (patch)
tree5c99a41b9d157186668ed63c001f72a09965143b /arch/ppc/platforms
parente8625d463560198cff7cb3eb22886c47d728d501 (diff)
[PATCH] ppc: Remove powermac support from ARCH=ppc
This makes it possible to build kernels for PReP and/or CHRP with ARCH=ppc by removing the (non-building) powermac support. It's now also possible to select PReP and CHRP independently. Powermac users should now build with ARCH=powerpc instead of ARCH=ppc. (This does mean that it is no longer possible to build a 32-bit kernel for a G5.) Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/ppc/platforms')
-rw-r--r--arch/ppc/platforms/Makefile11
-rw-r--r--arch/ppc/platforms/chrp_pci.c2
-rw-r--r--arch/ppc/platforms/chrp_setup.c73
-rw-r--r--arch/ppc/platforms/chrp_time.c64
-rw-r--r--arch/ppc/platforms/pmac_backlight.c202
-rw-r--r--arch/ppc/platforms/pmac_cache.S359
-rw-r--r--arch/ppc/platforms/pmac_cpufreq.c735
-rw-r--r--arch/ppc/platforms/pmac_feature.c3023
-rw-r--r--arch/ppc/platforms/pmac_low_i2c.c511
-rw-r--r--arch/ppc/platforms/pmac_nvram.c584
-rw-r--r--arch/ppc/platforms/pmac_pci.c1124
-rw-r--r--arch/ppc/platforms/pmac_pic.c693
-rw-r--r--arch/ppc/platforms/pmac_pic.h11
-rw-r--r--arch/ppc/platforms/pmac_setup.c745
-rw-r--r--arch/ppc/platforms/pmac_sleep.S396
-rw-r--r--arch/ppc/platforms/pmac_smp.c692
-rw-r--r--arch/ppc/platforms/pmac_time.c291
17 files changed, 136 insertions, 9380 deletions
diff --git a/arch/ppc/platforms/Makefile b/arch/ppc/platforms/Makefile
index 7c5cdabf6f3..51430e294b3 100644
--- a/arch/ppc/platforms/Makefile
+++ b/arch/ppc/platforms/Makefile
@@ -3,26 +3,18 @@
3# 3#
4 4
5# Extra CFLAGS so we don't have to do relative includes 5# Extra CFLAGS so we don't have to do relative includes
6CFLAGS_pmac_setup.o += -Iarch/$(ARCH)/mm 6CFLAGS_chrp_setup.o += -Iarch/$(ARCH)/mm
7 7
8obj-$(CONFIG_APUS) += apus_setup.o 8obj-$(CONFIG_APUS) += apus_setup.o
9ifeq ($(CONFIG_APUS),y) 9ifeq ($(CONFIG_APUS),y)
10obj-$(CONFIG_PCI) += apus_pci.o 10obj-$(CONFIG_PCI) += apus_pci.o
11endif 11endif
12obj-$(CONFIG_PPC_PMAC) += pmac_pic.o pmac_setup.o pmac_time.o \
13 pmac_feature.o pmac_pci.o pmac_sleep.o \
14 pmac_low_i2c.o pmac_cache.o
15obj-$(CONFIG_PPC_CHRP) += chrp_setup.o chrp_time.o chrp_pci.o \ 12obj-$(CONFIG_PPC_CHRP) += chrp_setup.o chrp_time.o chrp_pci.o \
16 chrp_pegasos_eth.o 13 chrp_pegasos_eth.o
17ifeq ($(CONFIG_PPC_CHRP),y) 14ifeq ($(CONFIG_PPC_CHRP),y)
18obj-$(CONFIG_NVRAM) += chrp_nvram.o 15obj-$(CONFIG_NVRAM) += chrp_nvram.o
19endif 16endif
20obj-$(CONFIG_PPC_PREP) += prep_pci.o prep_setup.o 17obj-$(CONFIG_PPC_PREP) += prep_pci.o prep_setup.o
21ifeq ($(CONFIG_PPC_PMAC),y)
22obj-$(CONFIG_NVRAM) += pmac_nvram.o
23obj-$(CONFIG_CPU_FREQ_PMAC) += pmac_cpufreq.o
24endif
25obj-$(CONFIG_PMAC_BACKLIGHT) += pmac_backlight.o
26obj-$(CONFIG_PREP_RESIDUAL) += residual.o 18obj-$(CONFIG_PREP_RESIDUAL) += residual.o
27obj-$(CONFIG_PQ2ADS) += pq2ads.o 19obj-$(CONFIG_PQ2ADS) += pq2ads.o
28obj-$(CONFIG_TQM8260) += tqm8260_setup.o 20obj-$(CONFIG_TQM8260) += tqm8260_setup.o
@@ -47,6 +39,5 @@ obj-$(CONFIG_LITE5200) += lite5200.o
47obj-$(CONFIG_EV64360) += ev64360.o 39obj-$(CONFIG_EV64360) += ev64360.o
48 40
49ifeq ($(CONFIG_SMP),y) 41ifeq ($(CONFIG_SMP),y)
50obj-$(CONFIG_PPC_PMAC) += pmac_smp.o
51obj-$(CONFIG_PPC_CHRP) += chrp_smp.o 42obj-$(CONFIG_PPC_CHRP) += chrp_smp.o
52endif 43endif
diff --git a/arch/ppc/platforms/chrp_pci.c b/arch/ppc/platforms/chrp_pci.c
index bd047aac01b..c7fe6182bb7 100644
--- a/arch/ppc/platforms/chrp_pci.c
+++ b/arch/ppc/platforms/chrp_pci.c
@@ -275,7 +275,7 @@ chrp_find_bridges(void)
275 setup_python(hose, dev); 275 setup_python(hose, dev);
276 } else if (is_mot 276 } else if (is_mot
277 || strncmp(model, "Motorola, Grackle", 17) == 0) { 277 || strncmp(model, "Motorola, Grackle", 17) == 0) {
278 setup_grackle(hose); 278 setup_indirect_pci(hose, 0xfec00000, 0xfee00000);
279 } else if (is_longtrail) { 279 } else if (is_longtrail) {
280 void __iomem *p = ioremap(GG2_PCI_CONFIG_BASE, 0x80000); 280 void __iomem *p = ioremap(GG2_PCI_CONFIG_BASE, 0x80000);
281 hose->ops = &gg2_pci_ops; 281 hose->ops = &gg2_pci_ops;
diff --git a/arch/ppc/platforms/chrp_setup.c b/arch/ppc/platforms/chrp_setup.c
index 056ac2a7b5c..48996b78737 100644
--- a/arch/ppc/platforms/chrp_setup.c
+++ b/arch/ppc/platforms/chrp_setup.c
@@ -53,6 +53,7 @@
53#include <asm/i8259.h> 53#include <asm/i8259.h>
54#include <asm/open_pic.h> 54#include <asm/open_pic.h>
55#include <asm/xmon.h> 55#include <asm/xmon.h>
56#include "mem_pieces.h"
56 57
57unsigned long chrp_get_rtc_time(void); 58unsigned long chrp_get_rtc_time(void);
58int chrp_set_rtc_time(unsigned long nowtime); 59int chrp_set_rtc_time(unsigned long nowtime);
@@ -65,7 +66,6 @@ void rtas_display_progress(char *, unsigned short);
65void rtas_indicator_progress(char *, unsigned short); 66void rtas_indicator_progress(char *, unsigned short);
66void btext_progress(char *, unsigned short); 67void btext_progress(char *, unsigned short);
67 68
68extern unsigned long pmac_find_end_of_memory(void);
69extern int of_show_percpuinfo(struct seq_file *, int); 69extern int of_show_percpuinfo(struct seq_file *, int);
70 70
71int _chrp_type; 71int _chrp_type;
@@ -467,6 +467,75 @@ chrp_init2(void)
467 ppc_md.progress(" Have fun! ", 0x7777); 467 ppc_md.progress(" Have fun! ", 0x7777);
468} 468}
469 469
470static struct device_node *memory_node;
471
472static int __init get_mem_prop(char *name, struct mem_pieces *mp)
473{
474 struct reg_property *rp;
475 int i, s;
476 unsigned int *ip;
477 int nac = prom_n_addr_cells(memory_node);
478 int nsc = prom_n_size_cells(memory_node);
479
480 ip = (unsigned int *) get_property(memory_node, name, &s);
481 if (ip == NULL) {
482 printk(KERN_ERR "error: couldn't get %s property on /memory\n",
483 name);
484 return 0;
485 }
486 s /= (nsc + nac) * 4;
487 rp = mp->regions;
488 for (i = 0; i < s; ++i, ip += nac+nsc) {
489 if (nac >= 2 && ip[nac-2] != 0)
490 continue;
491 rp->address = ip[nac-1];
492 if (nsc >= 2 && ip[nac+nsc-2] != 0)
493 rp->size = ~0U;
494 else
495 rp->size = ip[nac+nsc-1];
496 ++rp;
497 }
498 mp->n_regions = rp - mp->regions;
499
500 /* Make sure the pieces are sorted. */
501 mem_pieces_sort(mp);
502 mem_pieces_coalesce(mp);
503 return 1;
504}
505
506static unsigned long __init chrp_find_end_of_memory(void)
507{
508 unsigned long a, total;
509 struct mem_pieces phys_mem;
510
511 /*
512 * Find out where physical memory is, and check that it
513 * starts at 0 and is contiguous. It seems that RAM is
514 * always physically contiguous on Power Macintoshes.
515 *
516 * Supporting discontiguous physical memory isn't hard,
517 * it just makes the virtual <-> physical mapping functions
518 * more complicated (or else you end up wasting space
519 * in mem_map).
520 */
521 memory_node = find_devices("memory");
522 if (memory_node == NULL || !get_mem_prop("reg", &phys_mem)
523 || phys_mem.n_regions == 0)
524 panic("No RAM??");
525 a = phys_mem.regions[0].address;
526 if (a != 0)
527 panic("RAM doesn't start at physical address 0");
528 total = phys_mem.regions[0].size;
529
530 if (phys_mem.n_regions > 1) {
531 printk("RAM starting at 0x%x is not contiguous\n",
532 phys_mem.regions[1].address);
533 printk("Using RAM from 0 to 0x%lx\n", total-1);
534 }
535
536 return total;
537}
538
470void __init 539void __init
471chrp_init(unsigned long r3, unsigned long r4, unsigned long r5, 540chrp_init(unsigned long r3, unsigned long r4, unsigned long r5,
472 unsigned long r6, unsigned long r7) 541 unsigned long r6, unsigned long r7)
@@ -525,7 +594,7 @@ chrp_init(unsigned long r3, unsigned long r4, unsigned long r5,
525 ppc_md.get_rtc_time = chrp_get_rtc_time; 594 ppc_md.get_rtc_time = chrp_get_rtc_time;
526 ppc_md.calibrate_decr = chrp_calibrate_decr; 595 ppc_md.calibrate_decr = chrp_calibrate_decr;
527 596
528 ppc_md.find_end_of_memory = pmac_find_end_of_memory; 597 ppc_md.find_end_of_memory = chrp_find_end_of_memory;
529 598
530 if (rtas_data) { 599 if (rtas_data) {
531 struct device_node *rtas; 600 struct device_node *rtas;
diff --git a/arch/ppc/platforms/chrp_time.c b/arch/ppc/platforms/chrp_time.c
index 29d074c305f..57753a55b58 100644
--- a/arch/ppc/platforms/chrp_time.c
+++ b/arch/ppc/platforms/chrp_time.c
@@ -163,13 +163,75 @@ unsigned long chrp_get_rtc_time(void)
163 return mktime(year, mon, day, hour, min, sec); 163 return mktime(year, mon, day, hour, min, sec);
164} 164}
165 165
166/*
167 * Calibrate the decrementer frequency with the VIA timer 1.
168 */
169#define VIA_TIMER_FREQ_6 4700000 /* time 1 frequency * 6 */
170
171/* VIA registers */
172#define RS 0x200 /* skip between registers */
173#define T1CL (4*RS) /* Timer 1 ctr/latch (low 8 bits) */
174#define T1CH (5*RS) /* Timer 1 counter (high 8 bits) */
175#define T1LL (6*RS) /* Timer 1 latch (low 8 bits) */
176#define T1LH (7*RS) /* Timer 1 latch (high 8 bits) */
177#define ACR (11*RS) /* Auxiliary control register */
178#define IFR (13*RS) /* Interrupt flag register */
179
180/* Bits in ACR */
181#define T1MODE 0xc0 /* Timer 1 mode */
182#define T1MODE_CONT 0x40 /* continuous interrupts */
183
184/* Bits in IFR and IER */
185#define T1_INT 0x40 /* Timer 1 interrupt */
186
187static int __init chrp_via_calibrate_decr(void)
188{
189 struct device_node *vias;
190 volatile unsigned char __iomem *via;
191 int count = VIA_TIMER_FREQ_6 / 100;
192 unsigned int dstart, dend;
193
194 vias = find_devices("via-cuda");
195 if (vias == 0)
196 vias = find_devices("via");
197 if (vias == 0 || vias->n_addrs == 0)
198 return 0;
199 via = ioremap(vias->addrs[0].address, vias->addrs[0].size);
200
201 /* set timer 1 for continuous interrupts */
202 out_8(&via[ACR], (via[ACR] & ~T1MODE) | T1MODE_CONT);
203 /* set the counter to a small value */
204 out_8(&via[T1CH], 2);
205 /* set the latch to `count' */
206 out_8(&via[T1LL], count);
207 out_8(&via[T1LH], count >> 8);
208 /* wait until it hits 0 */
209 while ((in_8(&via[IFR]) & T1_INT) == 0)
210 ;
211 dstart = get_dec();
212 /* clear the interrupt & wait until it hits 0 again */
213 in_8(&via[T1CL]);
214 while ((in_8(&via[IFR]) & T1_INT) == 0)
215 ;
216 dend = get_dec();
217
218 tb_ticks_per_jiffy = (dstart - dend) / ((6 * HZ)/100);
219 tb_to_us = mulhwu_scale_factor(dstart - dend, 60000);
220
221 printk(KERN_INFO "via_calibrate_decr: ticks per jiffy = %u (%u ticks)\n",
222 tb_ticks_per_jiffy, dstart - dend);
223
224 iounmap(via);
225
226 return 1;
227}
166 228
167void __init chrp_calibrate_decr(void) 229void __init chrp_calibrate_decr(void)
168{ 230{
169 struct device_node *cpu; 231 struct device_node *cpu;
170 unsigned int freq, *fp; 232 unsigned int freq, *fp;
171 233
172 if (via_calibrate_decr()) 234 if (chrp_via_calibrate_decr())
173 return; 235 return;
174 236
175 /* 237 /*
diff --git a/arch/ppc/platforms/pmac_backlight.c b/arch/ppc/platforms/pmac_backlight.c
deleted file mode 100644
index 8be2f7d071f..00000000000
--- a/arch/ppc/platforms/pmac_backlight.c
+++ /dev/null
@@ -1,202 +0,0 @@
1/*
2 * Miscellaneous procedures for dealing with the PowerMac hardware.
3 * Contains support for the backlight.
4 *
5 * Copyright (C) 2000 Benjamin Herrenschmidt
6 *
7 */
8
9#include <linux/config.h>
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/stddef.h>
13#include <linux/reboot.h>
14#include <linux/nvram.h>
15#include <linux/console.h>
16#include <asm/sections.h>
17#include <asm/ptrace.h>
18#include <asm/io.h>
19#include <asm/pgtable.h>
20#include <asm/system.h>
21#include <asm/prom.h>
22#include <asm/machdep.h>
23#include <asm/nvram.h>
24#include <asm/backlight.h>
25
26#include <linux/adb.h>
27#include <linux/pmu.h>
28
29static struct backlight_controller *backlighter;
30static void* backlighter_data;
31static int backlight_autosave;
32static int backlight_level = BACKLIGHT_MAX;
33static int backlight_enabled = 1;
34static int backlight_req_level = -1;
35static int backlight_req_enable = -1;
36
37static void backlight_callback(void *);
38static DECLARE_WORK(backlight_work, backlight_callback, NULL);
39
40void register_backlight_controller(struct backlight_controller *ctrler,
41 void *data, char *type)
42{
43 struct device_node* bk_node;
44 char *prop;
45 int valid = 0;
46
47 /* There's already a matching controller, bail out */
48 if (backlighter != NULL)
49 return;
50
51 bk_node = find_devices("backlight");
52
53#ifdef CONFIG_ADB_PMU
54 /* Special case for the old PowerBook since I can't test on it */
55 backlight_autosave = machine_is_compatible("AAPL,3400/2400")
56 || machine_is_compatible("AAPL,3500");
57 if ((backlight_autosave
58 || machine_is_compatible("AAPL,PowerBook1998")
59 || machine_is_compatible("PowerBook1,1"))
60 && !strcmp(type, "pmu"))
61 valid = 1;
62#endif
63 if (bk_node) {
64 prop = get_property(bk_node, "backlight-control", NULL);
65 if (prop && !strncmp(prop, type, strlen(type)))
66 valid = 1;
67 }
68 if (!valid)
69 return;
70 backlighter = ctrler;
71 backlighter_data = data;
72
73 if (bk_node && !backlight_autosave)
74 prop = get_property(bk_node, "bklt", NULL);
75 else
76 prop = NULL;
77 if (prop) {
78 backlight_level = ((*prop)+1) >> 1;
79 if (backlight_level > BACKLIGHT_MAX)
80 backlight_level = BACKLIGHT_MAX;
81 }
82
83#ifdef CONFIG_ADB_PMU
84 if (backlight_autosave) {
85 struct adb_request req;
86 pmu_request(&req, NULL, 2, 0xd9, 0);
87 while (!req.complete)
88 pmu_poll();
89 backlight_level = req.reply[0] >> 4;
90 }
91#endif
92 acquire_console_sem();
93 if (!backlighter->set_enable(1, backlight_level, data))
94 backlight_enabled = 1;
95 release_console_sem();
96
97 printk(KERN_INFO "Registered \"%s\" backlight controller,"
98 "level: %d/15\n", type, backlight_level);
99}
100EXPORT_SYMBOL(register_backlight_controller);
101
102void unregister_backlight_controller(struct backlight_controller
103 *ctrler, void *data)
104{
105 /* We keep the current backlight level (for now) */
106 if (ctrler == backlighter && data == backlighter_data)
107 backlighter = NULL;
108}
109EXPORT_SYMBOL(unregister_backlight_controller);
110
111static int __set_backlight_enable(int enable)
112{
113 int rc;
114
115 if (!backlighter)
116 return -ENODEV;
117 acquire_console_sem();
118 rc = backlighter->set_enable(enable, backlight_level,
119 backlighter_data);
120 if (!rc)
121 backlight_enabled = enable;
122 release_console_sem();
123 return rc;
124}
125int set_backlight_enable(int enable)
126{
127 if (!backlighter)
128 return -ENODEV;
129 backlight_req_enable = enable;
130 schedule_work(&backlight_work);
131 return 0;
132}
133
134EXPORT_SYMBOL(set_backlight_enable);
135
136int get_backlight_enable(void)
137{
138 if (!backlighter)
139 return -ENODEV;
140 return backlight_enabled;
141}
142EXPORT_SYMBOL(get_backlight_enable);
143
144static int __set_backlight_level(int level)
145{
146 int rc = 0;
147
148 if (!backlighter)
149 return -ENODEV;
150 if (level < BACKLIGHT_MIN)
151 level = BACKLIGHT_OFF;
152 if (level > BACKLIGHT_MAX)
153 level = BACKLIGHT_MAX;
154 acquire_console_sem();
155 if (backlight_enabled)
156 rc = backlighter->set_level(level, backlighter_data);
157 if (!rc)
158 backlight_level = level;
159 release_console_sem();
160 if (!rc && !backlight_autosave) {
161 level <<=1;
162 if (level & 0x10)
163 level |= 0x01;
164 // -- todo: save to property "bklt"
165 }
166 return rc;
167}
168int set_backlight_level(int level)
169{
170 if (!backlighter)
171 return -ENODEV;
172 backlight_req_level = level;
173 schedule_work(&backlight_work);
174 return 0;
175}
176
177EXPORT_SYMBOL(set_backlight_level);
178
179int get_backlight_level(void)
180{
181 if (!backlighter)
182 return -ENODEV;
183 return backlight_level;
184}
185EXPORT_SYMBOL(get_backlight_level);
186
187static void backlight_callback(void *dummy)
188{
189 int level, enable;
190
191 do {
192 level = backlight_req_level;
193 enable = backlight_req_enable;
194 mb();
195
196 if (level >= 0)
197 __set_backlight_level(level);
198 if (enable >= 0)
199 __set_backlight_enable(enable);
200 } while(cmpxchg(&backlight_req_level, level, -1) != level ||
201 cmpxchg(&backlight_req_enable, enable, -1) != enable);
202}
diff --git a/arch/ppc/platforms/pmac_cache.S b/arch/ppc/platforms/pmac_cache.S
deleted file mode 100644
index fb977de6b70..00000000000
--- a/arch/ppc/platforms/pmac_cache.S
+++ /dev/null
@@ -1,359 +0,0 @@
1/*
2 * This file contains low-level cache management functions
3 * used for sleep and CPU speed changes on Apple machines.
4 * (In fact the only thing that is Apple-specific is that we assume
5 * that we can read from ROM at physical address 0xfff00000.)
6 *
7 * Copyright (C) 2004 Paul Mackerras (paulus@samba.org) and
8 * Benjamin Herrenschmidt (benh@kernel.crashing.org)
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 *
15 */
16
17#include <linux/config.h>
18#include <asm/processor.h>
19#include <asm/ppc_asm.h>
20#include <asm/cputable.h>
21
22/*
23 * Flush and disable all data caches (dL1, L2, L3). This is used
24 * when going to sleep, when doing a PMU based cpufreq transition,
25 * or when "offlining" a CPU on SMP machines. This code is over
26 * paranoid, but I've had enough issues with various CPU revs and
27 * bugs that I decided it was worth beeing over cautious
28 */
29
30_GLOBAL(flush_disable_caches)
31#ifndef CONFIG_6xx
32 blr
33#else
34BEGIN_FTR_SECTION
35 b flush_disable_745x
36END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)
37BEGIN_FTR_SECTION
38 b flush_disable_75x
39END_FTR_SECTION_IFSET(CPU_FTR_L2CR)
40 b __flush_disable_L1
41
42/* This is the code for G3 and 74[01]0 */
43flush_disable_75x:
44 mflr r10
45
46 /* Turn off EE and DR in MSR */
47 mfmsr r11
48 rlwinm r0,r11,0,~MSR_EE
49 rlwinm r0,r0,0,~MSR_DR
50 sync
51 mtmsr r0
52 isync
53
54 /* Stop DST streams */
55BEGIN_FTR_SECTION
56 DSSALL
57 sync
58END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
59
60 /* Stop DPM */
61 mfspr r8,SPRN_HID0 /* Save SPRN_HID0 in r8 */
62 rlwinm r4,r8,0,12,10 /* Turn off HID0[DPM] */
63 sync
64 mtspr SPRN_HID0,r4 /* Disable DPM */
65 sync
66
67 /* Disp-flush L1. We have a weird problem here that I never
68 * totally figured out. On 750FX, using the ROM for the flush
69 * results in a non-working flush. We use that workaround for
70 * now until I finally understand what's going on. --BenH
71 */
72
73 /* ROM base by default */
74 lis r4,0xfff0
75 mfpvr r3
76 srwi r3,r3,16
77 cmplwi cr0,r3,0x7000
78 bne+ 1f
79 /* RAM base on 750FX */
80 li r4,0
811: li r4,0x4000
82 mtctr r4
831: lwz r0,0(r4)
84 addi r4,r4,32
85 bdnz 1b
86 sync
87 isync
88
89 /* Disable / invalidate / enable L1 data */
90 mfspr r3,SPRN_HID0
91 rlwinm r3,r3,0,~(HID0_DCE | HID0_ICE)
92 mtspr SPRN_HID0,r3
93 sync
94 isync
95 ori r3,r3,(HID0_DCE|HID0_DCI|HID0_ICE|HID0_ICFI)
96 sync
97 isync
98 mtspr SPRN_HID0,r3
99 xori r3,r3,(HID0_DCI|HID0_ICFI)
100 mtspr SPRN_HID0,r3
101 sync
102
103 /* Get the current enable bit of the L2CR into r4 */
104 mfspr r5,SPRN_L2CR
105 /* Set to data-only (pre-745x bit) */
106 oris r3,r5,L2CR_L2DO@h
107 b 2f
108 /* When disabling L2, code must be in L1 */
109 .balign 32
1101: mtspr SPRN_L2CR,r3
1113: sync
112 isync
113 b 1f
1142: b 3f
1153: sync
116 isync
117 b 1b
1181: /* disp-flush L2. The interesting thing here is that the L2 can be
119 * up to 2Mb ... so using the ROM, we'll end up wrapping back to memory
120 * but that is probbaly fine. We disp-flush over 4Mb to be safe
121 */
122 lis r4,2
123 mtctr r4
124 lis r4,0xfff0
1251: lwz r0,0(r4)
126 addi r4,r4,32
127 bdnz 1b
128 sync
129 isync
130 lis r4,2
131 mtctr r4
132 lis r4,0xfff0
1331: dcbf 0,r4
134 addi r4,r4,32
135 bdnz 1b
136 sync
137 isync
138
139 /* now disable L2 */
140 rlwinm r5,r5,0,~L2CR_L2E
141 b 2f
142 /* When disabling L2, code must be in L1 */
143 .balign 32
1441: mtspr SPRN_L2CR,r5
1453: sync
146 isync
147 b 1f
1482: b 3f
1493: sync
150 isync
151 b 1b
1521: sync
153 isync
154 /* Invalidate L2. This is pre-745x, we clear the L2I bit ourselves */
155 oris r4,r5,L2CR_L2I@h
156 mtspr SPRN_L2CR,r4
157 sync
158 isync
159
160 /* Wait for the invalidation to complete */
1611: mfspr r3,SPRN_L2CR
162 rlwinm. r0,r3,0,31,31
163 bne 1b
164
165 /* Clear L2I */
166 xoris r4,r4,L2CR_L2I@h
167 sync
168 mtspr SPRN_L2CR,r4
169 sync
170
171 /* now disable the L1 data cache */
172 mfspr r0,SPRN_HID0
173 rlwinm r0,r0,0,~(HID0_DCE|HID0_ICE)
174 mtspr SPRN_HID0,r0
175 sync
176 isync
177
178 /* Restore HID0[DPM] to whatever it was before */
179 sync
180 mfspr r0,SPRN_HID0
181 rlwimi r0,r8,0,11,11 /* Turn back HID0[DPM] */
182 mtspr SPRN_HID0,r0
183 sync
184
185 /* restore DR and EE */
186 sync
187 mtmsr r11
188 isync
189
190 mtlr r10
191 blr
192
193/* This code is for 745x processors */
194flush_disable_745x:
195 /* Turn off EE and DR in MSR */
196 mfmsr r11
197 rlwinm r0,r11,0,~MSR_EE
198 rlwinm r0,r0,0,~MSR_DR
199 sync
200 mtmsr r0
201 isync
202
203 /* Stop prefetch streams */
204 DSSALL
205 sync
206
207 /* Disable L2 prefetching */
208 mfspr r0,SPRN_MSSCR0
209 rlwinm r0,r0,0,0,29
210 mtspr SPRN_MSSCR0,r0
211 sync
212 isync
213 lis r4,0
214 dcbf 0,r4
215 dcbf 0,r4
216 dcbf 0,r4
217 dcbf 0,r4
218 dcbf 0,r4
219 dcbf 0,r4
220 dcbf 0,r4
221 dcbf 0,r4
222
223 /* Due to a bug with the HW flush on some CPU revs, we occasionally
224 * experience data corruption. I'm adding a displacement flush along
225 * with a dcbf loop over a few Mb to "help". The problem isn't totally
226 * fixed by this in theory, but at least, in practice, I couldn't reproduce
227 * it even with a big hammer...
228 */
229
230 lis r4,0x0002
231 mtctr r4
232 li r4,0
2331:
234 lwz r0,0(r4)
235 addi r4,r4,32 /* Go to start of next cache line */
236 bdnz 1b
237 isync
238
239 /* Now, flush the first 4MB of memory */
240 lis r4,0x0002
241 mtctr r4
242 li r4,0
243 sync
2441:
245 dcbf 0,r4
246 addi r4,r4,32 /* Go to start of next cache line */
247 bdnz 1b
248
249 /* Flush and disable the L1 data cache */
250 mfspr r6,SPRN_LDSTCR
251 lis r3,0xfff0 /* read from ROM for displacement flush */
252 li r4,0xfe /* start with only way 0 unlocked */
253 li r5,128 /* 128 lines in each way */
2541: mtctr r5
255 rlwimi r6,r4,0,24,31
256 mtspr SPRN_LDSTCR,r6
257 sync
258 isync
2592: lwz r0,0(r3) /* touch each cache line */
260 addi r3,r3,32
261 bdnz 2b
262 rlwinm r4,r4,1,24,30 /* move on to the next way */
263 ori r4,r4,1
264 cmpwi r4,0xff /* all done? */
265 bne 1b
266 /* now unlock the L1 data cache */
267 li r4,0
268 rlwimi r6,r4,0,24,31
269 sync
270 mtspr SPRN_LDSTCR,r6
271 sync
272 isync
273
274 /* Flush the L2 cache using the hardware assist */
275 mfspr r3,SPRN_L2CR
276 cmpwi r3,0 /* check if it is enabled first */
277 bge 4f
278 oris r0,r3,(L2CR_L2IO_745x|L2CR_L2DO_745x)@h
279 b 2f
280 /* When disabling/locking L2, code must be in L1 */
281 .balign 32
2821: mtspr SPRN_L2CR,r0 /* lock the L2 cache */
2833: sync
284 isync
285 b 1f
2862: b 3f
2873: sync
288 isync
289 b 1b
2901: sync
291 isync
292 ori r0,r3,L2CR_L2HWF_745x
293 sync
294 mtspr SPRN_L2CR,r0 /* set the hardware flush bit */
2953: mfspr r0,SPRN_L2CR /* wait for it to go to 0 */
296 andi. r0,r0,L2CR_L2HWF_745x
297 bne 3b
298 sync
299 rlwinm r3,r3,0,~L2CR_L2E
300 b 2f
301 /* When disabling L2, code must be in L1 */
302 .balign 32
3031: mtspr SPRN_L2CR,r3 /* disable the L2 cache */
3043: sync
305 isync
306 b 1f
3072: b 3f
3083: sync
309 isync
310 b 1b
3111: sync
312 isync
313 oris r4,r3,L2CR_L2I@h
314 mtspr SPRN_L2CR,r4
315 sync
316 isync
3171: mfspr r4,SPRN_L2CR
318 andis. r0,r4,L2CR_L2I@h
319 bne 1b
320 sync
321
322BEGIN_FTR_SECTION
323 /* Flush the L3 cache using the hardware assist */
3244: mfspr r3,SPRN_L3CR
325 cmpwi r3,0 /* check if it is enabled */
326 bge 6f
327 oris r0,r3,L3CR_L3IO@h
328 ori r0,r0,L3CR_L3DO
329 sync
330 mtspr SPRN_L3CR,r0 /* lock the L3 cache */
331 sync
332 isync
333 ori r0,r0,L3CR_L3HWF
334 sync
335 mtspr SPRN_L3CR,r0 /* set the hardware flush bit */
3365: mfspr r0,SPRN_L3CR /* wait for it to go to zero */
337 andi. r0,r0,L3CR_L3HWF
338 bne 5b
339 rlwinm r3,r3,0,~L3CR_L3E
340 sync
341 mtspr SPRN_L3CR,r3 /* disable the L3 cache */
342 sync
343 ori r4,r3,L3CR_L3I
344 mtspr SPRN_L3CR,r4
3451: mfspr r4,SPRN_L3CR
346 andi. r0,r4,L3CR_L3I
347 bne 1b
348 sync
349END_FTR_SECTION_IFSET(CPU_FTR_L3CR)
350
3516: mfspr r0,SPRN_HID0 /* now disable the L1 data cache */
352 rlwinm r0,r0,0,~HID0_DCE
353 mtspr SPRN_HID0,r0
354 sync
355 isync
356 mtmsr r11 /* restore DR and EE */
357 isync
358 blr
359#endif /* CONFIG_6xx */
diff --git a/arch/ppc/platforms/pmac_cpufreq.c b/arch/ppc/platforms/pmac_cpufreq.c
deleted file mode 100644
index fba7e4d7c0b..00000000000
--- a/arch/ppc/platforms/pmac_cpufreq.c
+++ /dev/null
@@ -1,735 +0,0 @@
1/*
2 * arch/ppc/platforms/pmac_cpufreq.c
3 *
4 * Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 * Copyright (C) 2004 John Steele Scott <toojays@toojays.net>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * TODO: Need a big cleanup here. Basically, we need to have different
12 * cpufreq_driver structures for the different type of HW instead of the
13 * current mess. We also need to better deal with the detection of the
14 * type of machine.
15 *
16 */
17
18#include <linux/config.h>
19#include <linux/module.h>
20#include <linux/types.h>
21#include <linux/errno.h>
22#include <linux/kernel.h>
23#include <linux/delay.h>
24#include <linux/sched.h>
25#include <linux/adb.h>
26#include <linux/pmu.h>
27#include <linux/slab.h>
28#include <linux/cpufreq.h>
29#include <linux/init.h>
30#include <linux/sysdev.h>
31#include <linux/i2c.h>
32#include <linux/hardirq.h>
33#include <asm/prom.h>
34#include <asm/machdep.h>
35#include <asm/irq.h>
36#include <asm/pmac_feature.h>
37#include <asm/mmu_context.h>
38#include <asm/sections.h>
39#include <asm/cputable.h>
40#include <asm/time.h>
41#include <asm/system.h>
42#include <asm/open_pic.h>
43#include <asm/keylargo.h>
44
45/* WARNING !!! This will cause calibrate_delay() to be called,
46 * but this is an __init function ! So you MUST go edit
47 * init/main.c to make it non-init before enabling DEBUG_FREQ
48 */
49#undef DEBUG_FREQ
50
51/*
52 * There is a problem with the core cpufreq code on SMP kernels,
53 * it won't recalculate the Bogomips properly
54 */
55#ifdef CONFIG_SMP
56#warning "WARNING, CPUFREQ not recommended on SMP kernels"
57#endif
58
59extern void low_choose_7447a_dfs(int dfs);
60extern void low_choose_750fx_pll(int pll);
61extern void low_sleep_handler(void);
62
63/*
64 * Currently, PowerMac cpufreq supports only high & low frequencies
65 * that are set by the firmware
66 */
67static unsigned int low_freq;
68static unsigned int hi_freq;
69static unsigned int cur_freq;
70static unsigned int sleep_freq;
71
72/*
73 * Different models uses different mecanisms to switch the frequency
74 */
75static int (*set_speed_proc)(int low_speed);
76static unsigned int (*get_speed_proc)(void);
77
78/*
79 * Some definitions used by the various speedprocs
80 */
81static u32 voltage_gpio;
82static u32 frequency_gpio;
83static u32 slew_done_gpio;
84static int no_schedule;
85static int has_cpu_l2lve;
86static int is_pmu_based;
87
88/* There are only two frequency states for each processor. Values
89 * are in kHz for the time being.
90 */
91#define CPUFREQ_HIGH 0
92#define CPUFREQ_LOW 1
93
94static struct cpufreq_frequency_table pmac_cpu_freqs[] = {
95 {CPUFREQ_HIGH, 0},
96 {CPUFREQ_LOW, 0},
97 {0, CPUFREQ_TABLE_END},
98};
99
100static struct freq_attr* pmac_cpu_freqs_attr[] = {
101 &cpufreq_freq_attr_scaling_available_freqs,
102 NULL,
103};
104
105static inline void local_delay(unsigned long ms)
106{
107 if (no_schedule)
108 mdelay(ms);
109 else
110 msleep(ms);
111}
112
113static inline void wakeup_decrementer(void)
114{
115 set_dec(tb_ticks_per_jiffy);
116 /* No currently-supported powerbook has a 601,
117 * so use get_tbl, not native
118 */
119 last_jiffy_stamp(0) = tb_last_stamp = get_tbl();
120}
121
122#ifdef DEBUG_FREQ
123static inline void debug_calc_bogomips(void)
124{
125 /* This will cause a recalc of bogomips and display the
126 * result. We backup/restore the value to avoid affecting the
127 * core cpufreq framework's own calculation.
128 */
129 extern void calibrate_delay(void);
130
131 unsigned long save_lpj = loops_per_jiffy;
132 calibrate_delay();
133 loops_per_jiffy = save_lpj;
134}
135#endif /* DEBUG_FREQ */
136
137/* Switch CPU speed under 750FX CPU control
138 */
139static int cpu_750fx_cpu_speed(int low_speed)
140{
141 u32 hid2;
142
143 if (low_speed == 0) {
144 /* ramping up, set voltage first */
145 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x05);
146 /* Make sure we sleep for at least 1ms */
147 local_delay(10);
148
149 /* tweak L2 for high voltage */
150 if (has_cpu_l2lve) {
151 hid2 = mfspr(SPRN_HID2);
152 hid2 &= ~0x2000;
153 mtspr(SPRN_HID2, hid2);
154 }
155 }
156#ifdef CONFIG_6xx
157 low_choose_750fx_pll(low_speed);
158#endif
159 if (low_speed == 1) {
160 /* tweak L2 for low voltage */
161 if (has_cpu_l2lve) {
162 hid2 = mfspr(SPRN_HID2);
163 hid2 |= 0x2000;
164 mtspr(SPRN_HID2, hid2);
165 }
166
167 /* ramping down, set voltage last */
168 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x04);
169 local_delay(10);
170 }
171
172 return 0;
173}
174
175static unsigned int cpu_750fx_get_cpu_speed(void)
176{
177 if (mfspr(SPRN_HID1) & HID1_PS)
178 return low_freq;
179 else
180 return hi_freq;
181}
182
183/* Switch CPU speed using DFS */
184static int dfs_set_cpu_speed(int low_speed)
185{
186 if (low_speed == 0) {
187 /* ramping up, set voltage first */
188 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x05);
189 /* Make sure we sleep for at least 1ms */
190 local_delay(1);
191 }
192
193 /* set frequency */
194#ifdef CONFIG_6xx
195 low_choose_7447a_dfs(low_speed);
196#endif
197 udelay(100);
198
199 if (low_speed == 1) {
200 /* ramping down, set voltage last */
201 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x04);
202 local_delay(1);
203 }
204
205 return 0;
206}
207
208static unsigned int dfs_get_cpu_speed(void)
209{
210 if (mfspr(SPRN_HID1) & HID1_DFS)
211 return low_freq;
212 else
213 return hi_freq;
214}
215
216
217/* Switch CPU speed using slewing GPIOs
218 */
219static int gpios_set_cpu_speed(int low_speed)
220{
221 int gpio, timeout = 0;
222
223 /* If ramping up, set voltage first */
224 if (low_speed == 0) {
225 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x05);
226 /* Delay is way too big but it's ok, we schedule */
227 local_delay(10);
228 }
229
230 /* Set frequency */
231 gpio = pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, frequency_gpio, 0);
232 if (low_speed == ((gpio & 0x01) == 0))
233 goto skip;
234
235 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, frequency_gpio,
236 low_speed ? 0x04 : 0x05);
237 udelay(200);
238 do {
239 if (++timeout > 100)
240 break;
241 local_delay(1);
242 gpio = pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, slew_done_gpio, 0);
243 } while((gpio & 0x02) == 0);
244 skip:
245 /* If ramping down, set voltage last */
246 if (low_speed == 1) {
247 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x04);
248 /* Delay is way too big but it's ok, we schedule */
249 local_delay(10);
250 }
251
252#ifdef DEBUG_FREQ
253 debug_calc_bogomips();
254#endif
255
256 return 0;
257}
258
259/* Switch CPU speed under PMU control
260 */
261static int pmu_set_cpu_speed(int low_speed)
262{
263 struct adb_request req;
264 unsigned long save_l2cr;
265 unsigned long save_l3cr;
266 unsigned int pic_prio;
267 unsigned long flags;
268
269 preempt_disable();
270
271#ifdef DEBUG_FREQ
272 printk(KERN_DEBUG "HID1, before: %x\n", mfspr(SPRN_HID1));
273#endif
274 pmu_suspend();
275
276 /* Disable all interrupt sources on openpic */
277 pic_prio = openpic_get_priority();
278 openpic_set_priority(0xf);
279
280 /* Make sure the decrementer won't interrupt us */
281 asm volatile("mtdec %0" : : "r" (0x7fffffff));
282 /* Make sure any pending DEC interrupt occuring while we did
283 * the above didn't re-enable the DEC */
284 mb();
285 asm volatile("mtdec %0" : : "r" (0x7fffffff));
286
287 /* We can now disable MSR_EE */
288 local_irq_save(flags);
289
290 /* Giveup the FPU & vec */
291 enable_kernel_fp();
292
293#ifdef CONFIG_ALTIVEC
294 if (cpu_has_feature(CPU_FTR_ALTIVEC))
295 enable_kernel_altivec();
296#endif /* CONFIG_ALTIVEC */
297
298 /* Save & disable L2 and L3 caches */
299 save_l3cr = _get_L3CR(); /* (returns -1 if not available) */
300 save_l2cr = _get_L2CR(); /* (returns -1 if not available) */
301
302 /* Send the new speed command. My assumption is that this command
303 * will cause PLL_CFG[0..3] to be changed next time CPU goes to sleep
304 */
305 pmu_request(&req, NULL, 6, PMU_CPU_SPEED, 'W', 'O', 'O', 'F', low_speed);
306 while (!req.complete)
307 pmu_poll();
308
309 /* Prepare the northbridge for the speed transition */
310 pmac_call_feature(PMAC_FTR_SLEEP_STATE,NULL,1,1);
311
312 /* Call low level code to backup CPU state and recover from
313 * hardware reset
314 */
315 low_sleep_handler();
316
317 /* Restore the northbridge */
318 pmac_call_feature(PMAC_FTR_SLEEP_STATE,NULL,1,0);
319
320 /* Restore L2 cache */
321 if (save_l2cr != 0xffffffff && (save_l2cr & L2CR_L2E) != 0)
322 _set_L2CR(save_l2cr);
323 /* Restore L3 cache */
324 if (save_l3cr != 0xffffffff && (save_l3cr & L3CR_L3E) != 0)
325 _set_L3CR(save_l3cr);
326
327 /* Restore userland MMU context */
328 set_context(current->active_mm->context, current->active_mm->pgd);
329
330#ifdef DEBUG_FREQ
331 printk(KERN_DEBUG "HID1, after: %x\n", mfspr(SPRN_HID1));
332#endif
333
334 /* Restore low level PMU operations */
335 pmu_unlock();
336
337 /* Restore decrementer */
338 wakeup_decrementer();
339
340 /* Restore interrupts */
341 openpic_set_priority(pic_prio);
342
343 /* Let interrupts flow again ... */
344 local_irq_restore(flags);
345
346#ifdef DEBUG_FREQ
347 debug_calc_bogomips();
348#endif
349
350 pmu_resume();
351
352 preempt_enable();
353
354 return 0;
355}
356
357static int do_set_cpu_speed(int speed_mode, int notify)
358{
359 struct cpufreq_freqs freqs;
360 unsigned long l3cr;
361 static unsigned long prev_l3cr;
362
363 freqs.old = cur_freq;
364 freqs.new = (speed_mode == CPUFREQ_HIGH) ? hi_freq : low_freq;
365 freqs.cpu = smp_processor_id();
366
367 if (freqs.old == freqs.new)
368 return 0;
369
370 if (notify)
371 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
372 if (speed_mode == CPUFREQ_LOW &&
373 cpu_has_feature(CPU_FTR_L3CR)) {
374 l3cr = _get_L3CR();
375 if (l3cr & L3CR_L3E) {
376 prev_l3cr = l3cr;
377 _set_L3CR(0);
378 }
379 }
380 set_speed_proc(speed_mode == CPUFREQ_LOW);
381 if (speed_mode == CPUFREQ_HIGH &&
382 cpu_has_feature(CPU_FTR_L3CR)) {
383 l3cr = _get_L3CR();
384 if ((prev_l3cr & L3CR_L3E) && l3cr != prev_l3cr)
385 _set_L3CR(prev_l3cr);
386 }
387 if (notify)
388 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
389 cur_freq = (speed_mode == CPUFREQ_HIGH) ? hi_freq : low_freq;
390
391 return 0;
392}
393
394static unsigned int pmac_cpufreq_get_speed(unsigned int cpu)
395{
396 return cur_freq;
397}
398
399static int pmac_cpufreq_verify(struct cpufreq_policy *policy)
400{
401 return cpufreq_frequency_table_verify(policy, pmac_cpu_freqs);
402}
403
404static int pmac_cpufreq_target( struct cpufreq_policy *policy,
405 unsigned int target_freq,
406 unsigned int relation)
407{
408 unsigned int newstate = 0;
409
410 if (cpufreq_frequency_table_target(policy, pmac_cpu_freqs,
411 target_freq, relation, &newstate))
412 return -EINVAL;
413
414 return do_set_cpu_speed(newstate, 1);
415}
416
417unsigned int pmac_get_one_cpufreq(int i)
418{
419 /* Supports only one CPU for now */
420 return (i == 0) ? cur_freq : 0;
421}
422
423static int pmac_cpufreq_cpu_init(struct cpufreq_policy *policy)
424{
425 if (policy->cpu != 0)
426 return -ENODEV;
427
428 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
429 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
430 policy->cur = cur_freq;
431
432 cpufreq_frequency_table_get_attr(pmac_cpu_freqs, policy->cpu);
433 return cpufreq_frequency_table_cpuinfo(policy, pmac_cpu_freqs);
434}
435
436static u32 read_gpio(struct device_node *np)
437{
438 u32 *reg = (u32 *)get_property(np, "reg", NULL);
439 u32 offset;
440
441 if (reg == NULL)
442 return 0;
443 /* That works for all keylargos but shall be fixed properly
444 * some day... The problem is that it seems we can't rely
445 * on the "reg" property of the GPIO nodes, they are either
446 * relative to the base of KeyLargo or to the base of the
447 * GPIO space, and the device-tree doesn't help.
448 */
449 offset = *reg;
450 if (offset < KEYLARGO_GPIO_LEVELS0)
451 offset += KEYLARGO_GPIO_LEVELS0;
452 return offset;
453}
454
455static int pmac_cpufreq_suspend(struct cpufreq_policy *policy, pm_message_t pmsg)
456{
457 /* Ok, this could be made a bit smarter, but let's be robust for now. We
458 * always force a speed change to high speed before sleep, to make sure
459 * we have appropriate voltage and/or bus speed for the wakeup process,
460 * and to make sure our loops_per_jiffies are "good enough", that is will
461 * not cause too short delays if we sleep in low speed and wake in high
462 * speed..
463 */
464 no_schedule = 1;
465 sleep_freq = cur_freq;
466 if (cur_freq == low_freq && !is_pmu_based)
467 do_set_cpu_speed(CPUFREQ_HIGH, 0);
468 return 0;
469}
470
471static int pmac_cpufreq_resume(struct cpufreq_policy *policy)
472{
473 /* If we resume, first check if we have a get() function */
474 if (get_speed_proc)
475 cur_freq = get_speed_proc();
476 else
477 cur_freq = 0;
478
479 /* We don't, hrm... we don't really know our speed here, best
480 * is that we force a switch to whatever it was, which is
481 * probably high speed due to our suspend() routine
482 */
483 do_set_cpu_speed(sleep_freq == low_freq ?
484 CPUFREQ_LOW : CPUFREQ_HIGH, 0);
485
486 no_schedule = 0;
487 return 0;
488}
489
490static struct cpufreq_driver pmac_cpufreq_driver = {
491 .verify = pmac_cpufreq_verify,
492 .target = pmac_cpufreq_target,
493 .get = pmac_cpufreq_get_speed,
494 .init = pmac_cpufreq_cpu_init,
495 .suspend = pmac_cpufreq_suspend,
496 .resume = pmac_cpufreq_resume,
497 .flags = CPUFREQ_PM_NO_WARN,
498 .attr = pmac_cpu_freqs_attr,
499 .name = "powermac",
500 .owner = THIS_MODULE,
501};
502
503
504static int pmac_cpufreq_init_MacRISC3(struct device_node *cpunode)
505{
506 struct device_node *volt_gpio_np = of_find_node_by_name(NULL,
507 "voltage-gpio");
508 struct device_node *freq_gpio_np = of_find_node_by_name(NULL,
509 "frequency-gpio");
510 struct device_node *slew_done_gpio_np = of_find_node_by_name(NULL,
511 "slewing-done");
512 u32 *value;
513
514 /*
515 * Check to see if it's GPIO driven or PMU only
516 *
517 * The way we extract the GPIO address is slightly hackish, but it
518 * works well enough for now. We need to abstract the whole GPIO
519 * stuff sooner or later anyway
520 */
521
522 if (volt_gpio_np)
523 voltage_gpio = read_gpio(volt_gpio_np);
524 if (freq_gpio_np)
525 frequency_gpio = read_gpio(freq_gpio_np);
526 if (slew_done_gpio_np)
527 slew_done_gpio = read_gpio(slew_done_gpio_np);
528
529 /* If we use the frequency GPIOs, calculate the min/max speeds based
530 * on the bus frequencies
531 */
532 if (frequency_gpio && slew_done_gpio) {
533 int lenp, rc;
534 u32 *freqs, *ratio;
535
536 freqs = (u32 *)get_property(cpunode, "bus-frequencies", &lenp);
537 lenp /= sizeof(u32);
538 if (freqs == NULL || lenp != 2) {
539 printk(KERN_ERR "cpufreq: bus-frequencies incorrect or missing\n");
540 return 1;
541 }
542 ratio = (u32 *)get_property(cpunode, "processor-to-bus-ratio*2", NULL);
543 if (ratio == NULL) {
544 printk(KERN_ERR "cpufreq: processor-to-bus-ratio*2 missing\n");
545 return 1;
546 }
547
548 /* Get the min/max bus frequencies */
549 low_freq = min(freqs[0], freqs[1]);
550 hi_freq = max(freqs[0], freqs[1]);
551
552 /* Grrrr.. It _seems_ that the device-tree is lying on the low bus
553 * frequency, it claims it to be around 84Mhz on some models while
554 * it appears to be approx. 101Mhz on all. Let's hack around here...
555 * fortunately, we don't need to be too precise
556 */
557 if (low_freq < 98000000)
558 low_freq = 101000000;
559
560 /* Convert those to CPU core clocks */
561 low_freq = (low_freq * (*ratio)) / 2000;
562 hi_freq = (hi_freq * (*ratio)) / 2000;
563
564 /* Now we get the frequencies, we read the GPIO to see what is out current
565 * speed
566 */
567 rc = pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, frequency_gpio, 0);
568 cur_freq = (rc & 0x01) ? hi_freq : low_freq;
569
570 set_speed_proc = gpios_set_cpu_speed;
571 return 1;
572 }
573
574 /* If we use the PMU, look for the min & max frequencies in the
575 * device-tree
576 */
577 value = (u32 *)get_property(cpunode, "min-clock-frequency", NULL);
578 if (!value)
579 return 1;
580 low_freq = (*value) / 1000;
581 /* The PowerBook G4 12" (PowerBook6,1) has an error in the device-tree
582 * here */
583 if (low_freq < 100000)
584 low_freq *= 10;
585
586 value = (u32 *)get_property(cpunode, "max-clock-frequency", NULL);
587 if (!value)
588 return 1;
589 hi_freq = (*value) / 1000;
590 set_speed_proc = pmu_set_cpu_speed;
591 is_pmu_based = 1;
592
593 return 0;
594}
595
596static int pmac_cpufreq_init_7447A(struct device_node *cpunode)
597{
598 struct device_node *volt_gpio_np;
599
600 if (get_property(cpunode, "dynamic-power-step", NULL) == NULL)
601 return 1;
602
603 volt_gpio_np = of_find_node_by_name(NULL, "cpu-vcore-select");
604 if (volt_gpio_np)
605 voltage_gpio = read_gpio(volt_gpio_np);
606 if (!voltage_gpio){
607 printk(KERN_ERR "cpufreq: missing cpu-vcore-select gpio\n");
608 return 1;
609 }
610
611 /* OF only reports the high frequency */
612 hi_freq = cur_freq;
613 low_freq = cur_freq/2;
614
615 /* Read actual frequency from CPU */
616 cur_freq = dfs_get_cpu_speed();
617 set_speed_proc = dfs_set_cpu_speed;
618 get_speed_proc = dfs_get_cpu_speed;
619
620 return 0;
621}
622
623static int pmac_cpufreq_init_750FX(struct device_node *cpunode)
624{
625 struct device_node *volt_gpio_np;
626 u32 pvr, *value;
627
628 if (get_property(cpunode, "dynamic-power-step", NULL) == NULL)
629 return 1;
630
631 hi_freq = cur_freq;
632 value = (u32 *)get_property(cpunode, "reduced-clock-frequency", NULL);
633 if (!value)
634 return 1;
635 low_freq = (*value) / 1000;
636
637 volt_gpio_np = of_find_node_by_name(NULL, "cpu-vcore-select");
638 if (volt_gpio_np)
639 voltage_gpio = read_gpio(volt_gpio_np);
640
641 pvr = mfspr(SPRN_PVR);
642 has_cpu_l2lve = !((pvr & 0xf00) == 0x100);
643
644 set_speed_proc = cpu_750fx_cpu_speed;
645 get_speed_proc = cpu_750fx_get_cpu_speed;
646 cur_freq = cpu_750fx_get_cpu_speed();
647
648 return 0;
649}
650
651/* Currently, we support the following machines:
652 *
653 * - Titanium PowerBook 1Ghz (PMU based, 667Mhz & 1Ghz)
654 * - Titanium PowerBook 800 (PMU based, 667Mhz & 800Mhz)
655 * - Titanium PowerBook 400 (PMU based, 300Mhz & 400Mhz)
656 * - Titanium PowerBook 500 (PMU based, 300Mhz & 500Mhz)
657 * - iBook2 500/600 (PMU based, 400Mhz & 500/600Mhz)
658 * - iBook2 700 (CPU based, 400Mhz & 700Mhz, support low voltage)
659 * - Recent MacRISC3 laptops
660 * - All new machines with 7447A CPUs
661 */
662static int __init pmac_cpufreq_setup(void)
663{
664 struct device_node *cpunode;
665 u32 *value;
666
667 if (strstr(cmd_line, "nocpufreq"))
668 return 0;
669
670 /* Assume only one CPU */
671 cpunode = find_type_devices("cpu");
672 if (!cpunode)
673 goto out;
674
675 /* Get current cpu clock freq */
676 value = (u32 *)get_property(cpunode, "clock-frequency", NULL);
677 if (!value)
678 goto out;
679 cur_freq = (*value) / 1000;
680
681 /* Check for 7447A based MacRISC3 */
682 if (machine_is_compatible("MacRISC3") &&
683 get_property(cpunode, "dynamic-power-step", NULL) &&
684 PVR_VER(mfspr(SPRN_PVR)) == 0x8003) {
685 pmac_cpufreq_init_7447A(cpunode);
686 /* Check for other MacRISC3 machines */
687 } else if (machine_is_compatible("PowerBook3,4") ||
688 machine_is_compatible("PowerBook3,5") ||
689 machine_is_compatible("MacRISC3")) {
690 pmac_cpufreq_init_MacRISC3(cpunode);
691 /* Else check for iBook2 500/600 */
692 } else if (machine_is_compatible("PowerBook4,1")) {
693 hi_freq = cur_freq;
694 low_freq = 400000;
695 set_speed_proc = pmu_set_cpu_speed;
696 is_pmu_based = 1;
697 }
698 /* Else check for TiPb 550 */
699 else if (machine_is_compatible("PowerBook3,3") && cur_freq == 550000) {
700 hi_freq = cur_freq;
701 low_freq = 500000;
702 set_speed_proc = pmu_set_cpu_speed;
703 is_pmu_based = 1;
704 }
705 /* Else check for TiPb 400 & 500 */
706 else if (machine_is_compatible("PowerBook3,2")) {
707 /* We only know about the 400 MHz and the 500Mhz model
708 * they both have 300 MHz as low frequency
709 */
710 if (cur_freq < 350000 || cur_freq > 550000)
711 goto out;
712 hi_freq = cur_freq;
713 low_freq = 300000;
714 set_speed_proc = pmu_set_cpu_speed;
715 is_pmu_based = 1;
716 }
717 /* Else check for 750FX */
718 else if (PVR_VER(mfspr(SPRN_PVR)) == 0x7000)
719 pmac_cpufreq_init_750FX(cpunode);
720out:
721 if (set_speed_proc == NULL)
722 return -ENODEV;
723
724 pmac_cpu_freqs[CPUFREQ_LOW].frequency = low_freq;
725 pmac_cpu_freqs[CPUFREQ_HIGH].frequency = hi_freq;
726
727 printk(KERN_INFO "Registering PowerMac CPU frequency driver\n");
728 printk(KERN_INFO "Low: %d Mhz, High: %d Mhz, Boot: %d Mhz\n",
729 low_freq/1000, hi_freq/1000, cur_freq/1000);
730
731 return cpufreq_register_driver(&pmac_cpufreq_driver);
732}
733
734module_init(pmac_cpufreq_setup);
735
diff --git a/arch/ppc/platforms/pmac_feature.c b/arch/ppc/platforms/pmac_feature.c
deleted file mode 100644
index 6b7b3a15063..00000000000
--- a/arch/ppc/platforms/pmac_feature.c
+++ /dev/null
@@ -1,3023 +0,0 @@
1/*
2 * arch/ppc/platforms/pmac_feature.c
3 *
4 * Copyright (C) 1996-2001 Paul Mackerras (paulus@cs.anu.edu.au)
5 * Ben. Herrenschmidt (benh@kernel.crashing.org)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 *
12 * TODO:
13 *
14 * - Replace mdelay with some schedule loop if possible
15 * - Shorten some obfuscated delays on some routines (like modem
16 * power)
17 * - Refcount some clocks (see darwin)
18 * - Split split split...
19 *
20 */
21#include <linux/config.h>
22#include <linux/types.h>
23#include <linux/init.h>
24#include <linux/delay.h>
25#include <linux/kernel.h>
26#include <linux/sched.h>
27#include <linux/spinlock.h>
28#include <linux/adb.h>
29#include <linux/pmu.h>
30#include <linux/ioport.h>
31#include <linux/pci.h>
32#include <asm/sections.h>
33#include <asm/errno.h>
34#include <asm/ohare.h>
35#include <asm/heathrow.h>
36#include <asm/keylargo.h>
37#include <asm/uninorth.h>
38#include <asm/io.h>
39#include <asm/prom.h>
40#include <asm/machdep.h>
41#include <asm/pmac_feature.h>
42#include <asm/dbdma.h>
43#include <asm/pci-bridge.h>
44#include <asm/pmac_low_i2c.h>
45
46#undef DEBUG_FEATURE
47
48#ifdef DEBUG_FEATURE
49#define DBG(fmt,...) printk(KERN_DEBUG fmt)
50#else
51#define DBG(fmt,...)
52#endif
53
54#ifdef CONFIG_6xx
55extern int powersave_lowspeed;
56#endif
57
58extern int powersave_nap;
59extern struct device_node *k2_skiplist[2];
60
61
62/*
63 * We use a single global lock to protect accesses. Each driver has
64 * to take care of its own locking
65 */
66static DEFINE_SPINLOCK(feature_lock);
67
68#define LOCK(flags) spin_lock_irqsave(&feature_lock, flags);
69#define UNLOCK(flags) spin_unlock_irqrestore(&feature_lock, flags);
70
71
72/*
73 * Instance of some macio stuffs
74 */
75struct macio_chip macio_chips[MAX_MACIO_CHIPS];
76
77struct macio_chip* macio_find(struct device_node* child, int type)
78{
79 while(child) {
80 int i;
81
82 for (i=0; i < MAX_MACIO_CHIPS && macio_chips[i].of_node; i++)
83 if (child == macio_chips[i].of_node &&
84 (!type || macio_chips[i].type == type))
85 return &macio_chips[i];
86 child = child->parent;
87 }
88 return NULL;
89}
90EXPORT_SYMBOL_GPL(macio_find);
91
92static const char* macio_names[] =
93{
94 "Unknown",
95 "Grand Central",
96 "OHare",
97 "OHareII",
98 "Heathrow",
99 "Gatwick",
100 "Paddington",
101 "Keylargo",
102 "Pangea",
103 "Intrepid",
104 "K2"
105};
106
107
108
109/*
110 * Uninorth reg. access. Note that Uni-N regs are big endian
111 */
112
113#define UN_REG(r) (uninorth_base + ((r) >> 2))
114#define UN_IN(r) (in_be32(UN_REG(r)))
115#define UN_OUT(r,v) (out_be32(UN_REG(r), (v)))
116#define UN_BIS(r,v) (UN_OUT((r), UN_IN(r) | (v)))
117#define UN_BIC(r,v) (UN_OUT((r), UN_IN(r) & ~(v)))
118
119static struct device_node* uninorth_node;
120static u32 __iomem * uninorth_base;
121static u32 uninorth_rev;
122static int uninorth_u3;
123static void __iomem *u3_ht;
124
125/*
126 * For each motherboard family, we have a table of functions pointers
127 * that handle the various features.
128 */
129
130typedef long (*feature_call)(struct device_node* node, long param, long value);
131
132struct feature_table_entry {
133 unsigned int selector;
134 feature_call function;
135};
136
137struct pmac_mb_def
138{
139 const char* model_string;
140 const char* model_name;
141 int model_id;
142 struct feature_table_entry* features;
143 unsigned long board_flags;
144};
145static struct pmac_mb_def pmac_mb;
146
147/*
148 * Here are the chip specific feature functions
149 */
150
151static inline int
152simple_feature_tweak(struct device_node* node, int type, int reg, u32 mask, int value)
153{
154 struct macio_chip* macio;
155 unsigned long flags;
156
157 macio = macio_find(node, type);
158 if (!macio)
159 return -ENODEV;
160 LOCK(flags);
161 if (value)
162 MACIO_BIS(reg, mask);
163 else
164 MACIO_BIC(reg, mask);
165 (void)MACIO_IN32(reg);
166 UNLOCK(flags);
167
168 return 0;
169}
170
171#ifndef CONFIG_POWER4
172
173static long
174ohare_htw_scc_enable(struct device_node* node, long param, long value)
175{
176 struct macio_chip* macio;
177 unsigned long chan_mask;
178 unsigned long fcr;
179 unsigned long flags;
180 int htw, trans;
181 unsigned long rmask;
182
183 macio = macio_find(node, 0);
184 if (!macio)
185 return -ENODEV;
186 if (!strcmp(node->name, "ch-a"))
187 chan_mask = MACIO_FLAG_SCCA_ON;
188 else if (!strcmp(node->name, "ch-b"))
189 chan_mask = MACIO_FLAG_SCCB_ON;
190 else
191 return -ENODEV;
192
193 htw = (macio->type == macio_heathrow || macio->type == macio_paddington
194 || macio->type == macio_gatwick);
195 /* On these machines, the HRW_SCC_TRANS_EN_N bit mustn't be touched */
196 trans = (pmac_mb.model_id != PMAC_TYPE_YOSEMITE &&
197 pmac_mb.model_id != PMAC_TYPE_YIKES);
198 if (value) {
199#ifdef CONFIG_ADB_PMU
200 if ((param & 0xfff) == PMAC_SCC_IRDA)
201 pmu_enable_irled(1);
202#endif /* CONFIG_ADB_PMU */
203 LOCK(flags);
204 fcr = MACIO_IN32(OHARE_FCR);
205 /* Check if scc cell need enabling */
206 if (!(fcr & OH_SCC_ENABLE)) {
207 fcr |= OH_SCC_ENABLE;
208 if (htw) {
209 /* Side effect: this will also power up the
210 * modem, but it's too messy to figure out on which
211 * ports this controls the tranceiver and on which
212 * it controls the modem
213 */
214 if (trans)
215 fcr &= ~HRW_SCC_TRANS_EN_N;
216 MACIO_OUT32(OHARE_FCR, fcr);
217 fcr |= (rmask = HRW_RESET_SCC);
218 MACIO_OUT32(OHARE_FCR, fcr);
219 } else {
220 fcr |= (rmask = OH_SCC_RESET);
221 MACIO_OUT32(OHARE_FCR, fcr);
222 }
223 UNLOCK(flags);
224 (void)MACIO_IN32(OHARE_FCR);
225 mdelay(15);
226 LOCK(flags);
227 fcr &= ~rmask;
228 MACIO_OUT32(OHARE_FCR, fcr);
229 }
230 if (chan_mask & MACIO_FLAG_SCCA_ON)
231 fcr |= OH_SCCA_IO;
232 if (chan_mask & MACIO_FLAG_SCCB_ON)
233 fcr |= OH_SCCB_IO;
234 MACIO_OUT32(OHARE_FCR, fcr);
235 macio->flags |= chan_mask;
236 UNLOCK(flags);
237 if (param & PMAC_SCC_FLAG_XMON)
238 macio->flags |= MACIO_FLAG_SCC_LOCKED;
239 } else {
240 if (macio->flags & MACIO_FLAG_SCC_LOCKED)
241 return -EPERM;
242 LOCK(flags);
243 fcr = MACIO_IN32(OHARE_FCR);
244 if (chan_mask & MACIO_FLAG_SCCA_ON)
245 fcr &= ~OH_SCCA_IO;
246 if (chan_mask & MACIO_FLAG_SCCB_ON)
247 fcr &= ~OH_SCCB_IO;
248 MACIO_OUT32(OHARE_FCR, fcr);
249 if ((fcr & (OH_SCCA_IO | OH_SCCB_IO)) == 0) {
250 fcr &= ~OH_SCC_ENABLE;
251 if (htw && trans)
252 fcr |= HRW_SCC_TRANS_EN_N;
253 MACIO_OUT32(OHARE_FCR, fcr);
254 }
255 macio->flags &= ~(chan_mask);
256 UNLOCK(flags);
257 mdelay(10);
258#ifdef CONFIG_ADB_PMU
259 if ((param & 0xfff) == PMAC_SCC_IRDA)
260 pmu_enable_irled(0);
261#endif /* CONFIG_ADB_PMU */
262 }
263 return 0;
264}
265
266static long
267ohare_floppy_enable(struct device_node* node, long param, long value)
268{
269 return simple_feature_tweak(node, macio_ohare,
270 OHARE_FCR, OH_FLOPPY_ENABLE, value);
271}
272
273static long
274ohare_mesh_enable(struct device_node* node, long param, long value)
275{
276 return simple_feature_tweak(node, macio_ohare,
277 OHARE_FCR, OH_MESH_ENABLE, value);
278}
279
280static long
281ohare_ide_enable(struct device_node* node, long param, long value)
282{
283 switch(param) {
284 case 0:
285 /* For some reason, setting the bit in set_initial_features()
286 * doesn't stick. I'm still investigating... --BenH.
287 */
288 if (value)
289 simple_feature_tweak(node, macio_ohare,
290 OHARE_FCR, OH_IOBUS_ENABLE, 1);
291 return simple_feature_tweak(node, macio_ohare,
292 OHARE_FCR, OH_IDE0_ENABLE, value);
293 case 1:
294 return simple_feature_tweak(node, macio_ohare,
295 OHARE_FCR, OH_BAY_IDE_ENABLE, value);
296 default:
297 return -ENODEV;
298 }
299}
300
301static long
302ohare_ide_reset(struct device_node* node, long param, long value)
303{
304 switch(param) {
305 case 0:
306 return simple_feature_tweak(node, macio_ohare,
307 OHARE_FCR, OH_IDE0_RESET_N, !value);
308 case 1:
309 return simple_feature_tweak(node, macio_ohare,
310 OHARE_FCR, OH_IDE1_RESET_N, !value);
311 default:
312 return -ENODEV;
313 }
314}
315
316static long
317ohare_sleep_state(struct device_node* node, long param, long value)
318{
319 struct macio_chip* macio = &macio_chips[0];
320
321 if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0)
322 return -EPERM;
323 if (value == 1) {
324 MACIO_BIC(OHARE_FCR, OH_IOBUS_ENABLE);
325 } else if (value == 0) {
326 MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE);
327 }
328
329 return 0;
330}
331
332static long
333heathrow_modem_enable(struct device_node* node, long param, long value)
334{
335 struct macio_chip* macio;
336 u8 gpio;
337 unsigned long flags;
338
339 macio = macio_find(node, macio_unknown);
340 if (!macio)
341 return -ENODEV;
342 gpio = MACIO_IN8(HRW_GPIO_MODEM_RESET) & ~1;
343 if (!value) {
344 LOCK(flags);
345 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio);
346 UNLOCK(flags);
347 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET);
348 mdelay(250);
349 }
350 if (pmac_mb.model_id != PMAC_TYPE_YOSEMITE &&
351 pmac_mb.model_id != PMAC_TYPE_YIKES) {
352 LOCK(flags);
353 if (value)
354 MACIO_BIC(HEATHROW_FCR, HRW_SCC_TRANS_EN_N);
355 else
356 MACIO_BIS(HEATHROW_FCR, HRW_SCC_TRANS_EN_N);
357 UNLOCK(flags);
358 (void)MACIO_IN32(HEATHROW_FCR);
359 mdelay(250);
360 }
361 if (value) {
362 LOCK(flags);
363 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio | 1);
364 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET);
365 UNLOCK(flags); mdelay(250); LOCK(flags);
366 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio);
367 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET);
368 UNLOCK(flags); mdelay(250); LOCK(flags);
369 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio | 1);
370 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET);
371 UNLOCK(flags); mdelay(250);
372 }
373 return 0;
374}
375
376static long
377heathrow_floppy_enable(struct device_node* node, long param, long value)
378{
379 return simple_feature_tweak(node, macio_unknown,
380 HEATHROW_FCR,
381 HRW_SWIM_ENABLE|HRW_BAY_FLOPPY_ENABLE,
382 value);
383}
384
385static long
386heathrow_mesh_enable(struct device_node* node, long param, long value)
387{
388 struct macio_chip* macio;
389 unsigned long flags;
390
391 macio = macio_find(node, macio_unknown);
392 if (!macio)
393 return -ENODEV;
394 LOCK(flags);
395 /* Set clear mesh cell enable */
396 if (value)
397 MACIO_BIS(HEATHROW_FCR, HRW_MESH_ENABLE);
398 else
399 MACIO_BIC(HEATHROW_FCR, HRW_MESH_ENABLE);
400 (void)MACIO_IN32(HEATHROW_FCR);
401 udelay(10);
402 /* Set/Clear termination power */
403 if (value)
404 MACIO_BIC(HEATHROW_MBCR, 0x04000000);
405 else
406 MACIO_BIS(HEATHROW_MBCR, 0x04000000);
407 (void)MACIO_IN32(HEATHROW_MBCR);
408 udelay(10);
409 UNLOCK(flags);
410
411 return 0;
412}
413
414static long
415heathrow_ide_enable(struct device_node* node, long param, long value)
416{
417 switch(param) {
418 case 0:
419 return simple_feature_tweak(node, macio_unknown,
420 HEATHROW_FCR, HRW_IDE0_ENABLE, value);
421 case 1:
422 return simple_feature_tweak(node, macio_unknown,
423 HEATHROW_FCR, HRW_BAY_IDE_ENABLE, value);
424 default:
425 return -ENODEV;
426 }
427}
428
429static long
430heathrow_ide_reset(struct device_node* node, long param, long value)
431{
432 switch(param) {
433 case 0:
434 return simple_feature_tweak(node, macio_unknown,
435 HEATHROW_FCR, HRW_IDE0_RESET_N, !value);
436 case 1:
437 return simple_feature_tweak(node, macio_unknown,
438 HEATHROW_FCR, HRW_IDE1_RESET_N, !value);
439 default:
440 return -ENODEV;
441 }
442}
443
444static long
445heathrow_bmac_enable(struct device_node* node, long param, long value)
446{
447 struct macio_chip* macio;
448 unsigned long flags;
449
450 macio = macio_find(node, 0);
451 if (!macio)
452 return -ENODEV;
453 if (value) {
454 LOCK(flags);
455 MACIO_BIS(HEATHROW_FCR, HRW_BMAC_IO_ENABLE);
456 MACIO_BIS(HEATHROW_FCR, HRW_BMAC_RESET);
457 UNLOCK(flags);
458 (void)MACIO_IN32(HEATHROW_FCR);
459 mdelay(10);
460 LOCK(flags);
461 MACIO_BIC(HEATHROW_FCR, HRW_BMAC_RESET);
462 UNLOCK(flags);
463 (void)MACIO_IN32(HEATHROW_FCR);
464 mdelay(10);
465 } else {
466 LOCK(flags);
467 MACIO_BIC(HEATHROW_FCR, HRW_BMAC_IO_ENABLE);
468 UNLOCK(flags);
469 }
470 return 0;
471}
472
473static long
474heathrow_sound_enable(struct device_node* node, long param, long value)
475{
476 struct macio_chip* macio;
477 unsigned long flags;
478
479 /* B&W G3 and Yikes don't support that properly (the
480 * sound appear to never come back after beeing shut down).
481 */
482 if (pmac_mb.model_id == PMAC_TYPE_YOSEMITE ||
483 pmac_mb.model_id == PMAC_TYPE_YIKES)
484 return 0;
485
486 macio = macio_find(node, 0);
487 if (!macio)
488 return -ENODEV;
489 if (value) {
490 LOCK(flags);
491 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE);
492 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_POWER_N);
493 UNLOCK(flags);
494 (void)MACIO_IN32(HEATHROW_FCR);
495 } else {
496 LOCK(flags);
497 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_POWER_N);
498 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE);
499 UNLOCK(flags);
500 }
501 return 0;
502}
503
504static u32 save_fcr[6];
505static u32 save_mbcr;
506static u32 save_gpio_levels[2];
507static u8 save_gpio_extint[KEYLARGO_GPIO_EXTINT_CNT];
508static u8 save_gpio_normal[KEYLARGO_GPIO_CNT];
509static u32 save_unin_clock_ctl;
510static struct dbdma_regs save_dbdma[13];
511static struct dbdma_regs save_alt_dbdma[13];
512
513static void
514dbdma_save(struct macio_chip* macio, struct dbdma_regs* save)
515{
516 int i;
517
518 /* Save state & config of DBDMA channels */
519 for (i=0; i<13; i++) {
520 volatile struct dbdma_regs __iomem * chan = (void __iomem *)
521 (macio->base + ((0x8000+i*0x100)>>2));
522 save[i].cmdptr_hi = in_le32(&chan->cmdptr_hi);
523 save[i].cmdptr = in_le32(&chan->cmdptr);
524 save[i].intr_sel = in_le32(&chan->intr_sel);
525 save[i].br_sel = in_le32(&chan->br_sel);
526 save[i].wait_sel = in_le32(&chan->wait_sel);
527 }
528}
529
530static void
531dbdma_restore(struct macio_chip* macio, struct dbdma_regs* save)
532{
533 int i;
534
535 /* Save state & config of DBDMA channels */
536 for (i=0; i<13; i++) {
537 volatile struct dbdma_regs __iomem * chan = (void __iomem *)
538 (macio->base + ((0x8000+i*0x100)>>2));
539 out_le32(&chan->control, (ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN)<<16);
540 while (in_le32(&chan->status) & ACTIVE)
541 mb();
542 out_le32(&chan->cmdptr_hi, save[i].cmdptr_hi);
543 out_le32(&chan->cmdptr, save[i].cmdptr);
544 out_le32(&chan->intr_sel, save[i].intr_sel);
545 out_le32(&chan->br_sel, save[i].br_sel);
546 out_le32(&chan->wait_sel, save[i].wait_sel);
547 }
548}
549
550static void
551heathrow_sleep(struct macio_chip* macio, int secondary)
552{
553 if (secondary) {
554 dbdma_save(macio, save_alt_dbdma);
555 save_fcr[2] = MACIO_IN32(0x38);
556 save_fcr[3] = MACIO_IN32(0x3c);
557 } else {
558 dbdma_save(macio, save_dbdma);
559 save_fcr[0] = MACIO_IN32(0x38);
560 save_fcr[1] = MACIO_IN32(0x3c);
561 save_mbcr = MACIO_IN32(0x34);
562 /* Make sure sound is shut down */
563 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_POWER_N);
564 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE);
565 /* This seems to be necessary as well or the fan
566 * keeps coming up and battery drains fast */
567 MACIO_BIC(HEATHROW_FCR, HRW_IOBUS_ENABLE);
568 MACIO_BIC(HEATHROW_FCR, HRW_IDE0_RESET_N);
569 /* Make sure eth is down even if module or sleep
570 * won't work properly */
571 MACIO_BIC(HEATHROW_FCR, HRW_BMAC_IO_ENABLE | HRW_BMAC_RESET);
572 }
573 /* Make sure modem is shut down */
574 MACIO_OUT8(HRW_GPIO_MODEM_RESET,
575 MACIO_IN8(HRW_GPIO_MODEM_RESET) & ~1);
576 MACIO_BIS(HEATHROW_FCR, HRW_SCC_TRANS_EN_N);
577 MACIO_BIC(HEATHROW_FCR, OH_SCCA_IO|OH_SCCB_IO|HRW_SCC_ENABLE);
578
579 /* Let things settle */
580 (void)MACIO_IN32(HEATHROW_FCR);
581}
582
583static void
584heathrow_wakeup(struct macio_chip* macio, int secondary)
585{
586 if (secondary) {
587 MACIO_OUT32(0x38, save_fcr[2]);
588 (void)MACIO_IN32(0x38);
589 mdelay(1);
590 MACIO_OUT32(0x3c, save_fcr[3]);
591 (void)MACIO_IN32(0x38);
592 mdelay(10);
593 dbdma_restore(macio, save_alt_dbdma);
594 } else {
595 MACIO_OUT32(0x38, save_fcr[0] | HRW_IOBUS_ENABLE);
596 (void)MACIO_IN32(0x38);
597 mdelay(1);
598 MACIO_OUT32(0x3c, save_fcr[1]);
599 (void)MACIO_IN32(0x38);
600 mdelay(1);
601 MACIO_OUT32(0x34, save_mbcr);
602 (void)MACIO_IN32(0x38);
603 mdelay(10);
604 dbdma_restore(macio, save_dbdma);
605 }
606}
607
608static long
609heathrow_sleep_state(struct device_node* node, long param, long value)
610{
611 if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0)
612 return -EPERM;
613 if (value == 1) {
614 if (macio_chips[1].type == macio_gatwick)
615 heathrow_sleep(&macio_chips[0], 1);
616 heathrow_sleep(&macio_chips[0], 0);
617 } else if (value == 0) {
618 heathrow_wakeup(&macio_chips[0], 0);
619 if (macio_chips[1].type == macio_gatwick)
620 heathrow_wakeup(&macio_chips[0], 1);
621 }
622 return 0;
623}
624
625static long
626core99_scc_enable(struct device_node* node, long param, long value)
627{
628 struct macio_chip* macio;
629 unsigned long flags;
630 unsigned long chan_mask;
631 u32 fcr;
632
633 macio = macio_find(node, 0);
634 if (!macio)
635 return -ENODEV;
636 if (!strcmp(node->name, "ch-a"))
637 chan_mask = MACIO_FLAG_SCCA_ON;
638 else if (!strcmp(node->name, "ch-b"))
639 chan_mask = MACIO_FLAG_SCCB_ON;
640 else
641 return -ENODEV;
642
643 if (value) {
644 int need_reset_scc = 0;
645 int need_reset_irda = 0;
646
647 LOCK(flags);
648 fcr = MACIO_IN32(KEYLARGO_FCR0);
649 /* Check if scc cell need enabling */
650 if (!(fcr & KL0_SCC_CELL_ENABLE)) {
651 fcr |= KL0_SCC_CELL_ENABLE;
652 need_reset_scc = 1;
653 }
654 if (chan_mask & MACIO_FLAG_SCCA_ON) {
655 fcr |= KL0_SCCA_ENABLE;
656 /* Don't enable line drivers for I2S modem */
657 if ((param & 0xfff) == PMAC_SCC_I2S1)
658 fcr &= ~KL0_SCC_A_INTF_ENABLE;
659 else
660 fcr |= KL0_SCC_A_INTF_ENABLE;
661 }
662 if (chan_mask & MACIO_FLAG_SCCB_ON) {
663 fcr |= KL0_SCCB_ENABLE;
664 /* Perform irda specific inits */
665 if ((param & 0xfff) == PMAC_SCC_IRDA) {
666 fcr &= ~KL0_SCC_B_INTF_ENABLE;
667 fcr |= KL0_IRDA_ENABLE;
668 fcr |= KL0_IRDA_CLK32_ENABLE | KL0_IRDA_CLK19_ENABLE;
669 fcr |= KL0_IRDA_SOURCE1_SEL;
670 fcr &= ~(KL0_IRDA_FAST_CONNECT|KL0_IRDA_DEFAULT1|KL0_IRDA_DEFAULT0);
671 fcr &= ~(KL0_IRDA_SOURCE2_SEL|KL0_IRDA_HIGH_BAND);
672 need_reset_irda = 1;
673 } else
674 fcr |= KL0_SCC_B_INTF_ENABLE;
675 }
676 MACIO_OUT32(KEYLARGO_FCR0, fcr);
677 macio->flags |= chan_mask;
678 if (need_reset_scc) {
679 MACIO_BIS(KEYLARGO_FCR0, KL0_SCC_RESET);
680 (void)MACIO_IN32(KEYLARGO_FCR0);
681 UNLOCK(flags);
682 mdelay(15);
683 LOCK(flags);
684 MACIO_BIC(KEYLARGO_FCR0, KL0_SCC_RESET);
685 }
686 if (need_reset_irda) {
687 MACIO_BIS(KEYLARGO_FCR0, KL0_IRDA_RESET);
688 (void)MACIO_IN32(KEYLARGO_FCR0);
689 UNLOCK(flags);
690 mdelay(15);
691 LOCK(flags);
692 MACIO_BIC(KEYLARGO_FCR0, KL0_IRDA_RESET);
693 }
694 UNLOCK(flags);
695 if (param & PMAC_SCC_FLAG_XMON)
696 macio->flags |= MACIO_FLAG_SCC_LOCKED;
697 } else {
698 if (macio->flags & MACIO_FLAG_SCC_LOCKED)
699 return -EPERM;
700 LOCK(flags);
701 fcr = MACIO_IN32(KEYLARGO_FCR0);
702 if (chan_mask & MACIO_FLAG_SCCA_ON)
703 fcr &= ~KL0_SCCA_ENABLE;
704 if (chan_mask & MACIO_FLAG_SCCB_ON) {
705 fcr &= ~KL0_SCCB_ENABLE;
706 /* Perform irda specific clears */
707 if ((param & 0xfff) == PMAC_SCC_IRDA) {
708 fcr &= ~KL0_IRDA_ENABLE;
709 fcr &= ~(KL0_IRDA_CLK32_ENABLE | KL0_IRDA_CLK19_ENABLE);
710 fcr &= ~(KL0_IRDA_FAST_CONNECT|KL0_IRDA_DEFAULT1|KL0_IRDA_DEFAULT0);
711 fcr &= ~(KL0_IRDA_SOURCE1_SEL|KL0_IRDA_SOURCE2_SEL|KL0_IRDA_HIGH_BAND);
712 }
713 }
714 MACIO_OUT32(KEYLARGO_FCR0, fcr);
715 if ((fcr & (KL0_SCCA_ENABLE | KL0_SCCB_ENABLE)) == 0) {
716 fcr &= ~KL0_SCC_CELL_ENABLE;
717 MACIO_OUT32(KEYLARGO_FCR0, fcr);
718 }
719 macio->flags &= ~(chan_mask);
720 UNLOCK(flags);
721 mdelay(10);
722 }
723 return 0;
724}
725
726static long
727core99_modem_enable(struct device_node* node, long param, long value)
728{
729 struct macio_chip* macio;
730 u8 gpio;
731 unsigned long flags;
732
733 /* Hack for internal USB modem */
734 if (node == NULL) {
735 if (macio_chips[0].type != macio_keylargo)
736 return -ENODEV;
737 node = macio_chips[0].of_node;
738 }
739 macio = macio_find(node, 0);
740 if (!macio)
741 return -ENODEV;
742 gpio = MACIO_IN8(KL_GPIO_MODEM_RESET);
743 gpio |= KEYLARGO_GPIO_OUTPUT_ENABLE;
744 gpio &= ~KEYLARGO_GPIO_OUTOUT_DATA;
745
746 if (!value) {
747 LOCK(flags);
748 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio);
749 UNLOCK(flags);
750 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
751 mdelay(250);
752 }
753 LOCK(flags);
754 if (value) {
755 MACIO_BIC(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);
756 UNLOCK(flags);
757 (void)MACIO_IN32(KEYLARGO_FCR2);
758 mdelay(250);
759 } else {
760 MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);
761 UNLOCK(flags);
762 }
763 if (value) {
764 LOCK(flags);
765 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA);
766 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
767 UNLOCK(flags); mdelay(250); LOCK(flags);
768 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio);
769 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
770 UNLOCK(flags); mdelay(250); LOCK(flags);
771 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA);
772 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
773 UNLOCK(flags); mdelay(250);
774 }
775 return 0;
776}
777
778static long
779pangea_modem_enable(struct device_node* node, long param, long value)
780{
781 struct macio_chip* macio;
782 u8 gpio;
783 unsigned long flags;
784
785 /* Hack for internal USB modem */
786 if (node == NULL) {
787 if (macio_chips[0].type != macio_pangea &&
788 macio_chips[0].type != macio_intrepid)
789 return -ENODEV;
790 node = macio_chips[0].of_node;
791 }
792 macio = macio_find(node, 0);
793 if (!macio)
794 return -ENODEV;
795 gpio = MACIO_IN8(KL_GPIO_MODEM_RESET);
796 gpio |= KEYLARGO_GPIO_OUTPUT_ENABLE;
797 gpio &= ~KEYLARGO_GPIO_OUTOUT_DATA;
798
799 if (!value) {
800 LOCK(flags);
801 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio);
802 UNLOCK(flags);
803 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
804 mdelay(250);
805 }
806 LOCK(flags);
807 if (value) {
808 MACIO_OUT8(KL_GPIO_MODEM_POWER,
809 KEYLARGO_GPIO_OUTPUT_ENABLE);
810 UNLOCK(flags);
811 (void)MACIO_IN32(KEYLARGO_FCR2);
812 mdelay(250);
813 } else {
814 MACIO_OUT8(KL_GPIO_MODEM_POWER,
815 KEYLARGO_GPIO_OUTPUT_ENABLE | KEYLARGO_GPIO_OUTOUT_DATA);
816 UNLOCK(flags);
817 }
818 if (value) {
819 LOCK(flags);
820 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA);
821 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
822 UNLOCK(flags); mdelay(250); LOCK(flags);
823 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio);
824 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
825 UNLOCK(flags); mdelay(250); LOCK(flags);
826 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA);
827 (void)MACIO_IN8(KL_GPIO_MODEM_RESET);
828 UNLOCK(flags); mdelay(250);
829 }
830 return 0;
831}
832
833static long
834core99_ata100_enable(struct device_node* node, long value)
835{
836 unsigned long flags;
837 struct pci_dev *pdev = NULL;
838 u8 pbus, pid;
839
840 if (uninorth_rev < 0x24)
841 return -ENODEV;
842
843 LOCK(flags);
844 if (value)
845 UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_ATA100);
846 else
847 UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_ATA100);
848 (void)UN_IN(UNI_N_CLOCK_CNTL);
849 UNLOCK(flags);
850 udelay(20);
851
852 if (value) {
853 if (pci_device_from_OF_node(node, &pbus, &pid) == 0)
854 pdev = pci_find_slot(pbus, pid);
855 if (pdev == NULL)
856 return 0;
857 pci_enable_device(pdev);
858 pci_set_master(pdev);
859 }
860 return 0;
861}
862
863static long
864core99_ide_enable(struct device_node* node, long param, long value)
865{
866 /* Bus ID 0 to 2 are KeyLargo based IDE, busID 3 is U2
867 * based ata-100
868 */
869 switch(param) {
870 case 0:
871 return simple_feature_tweak(node, macio_unknown,
872 KEYLARGO_FCR1, KL1_EIDE0_ENABLE, value);
873 case 1:
874 return simple_feature_tweak(node, macio_unknown,
875 KEYLARGO_FCR1, KL1_EIDE1_ENABLE, value);
876 case 2:
877 return simple_feature_tweak(node, macio_unknown,
878 KEYLARGO_FCR1, KL1_UIDE_ENABLE, value);
879 case 3:
880 return core99_ata100_enable(node, value);
881 default:
882 return -ENODEV;
883 }
884}
885
886static long
887core99_ide_reset(struct device_node* node, long param, long value)
888{
889 switch(param) {
890 case 0:
891 return simple_feature_tweak(node, macio_unknown,
892 KEYLARGO_FCR1, KL1_EIDE0_RESET_N, !value);
893 case 1:
894 return simple_feature_tweak(node, macio_unknown,
895 KEYLARGO_FCR1, KL1_EIDE1_RESET_N, !value);
896 case 2:
897 return simple_feature_tweak(node, macio_unknown,
898 KEYLARGO_FCR1, KL1_UIDE_RESET_N, !value);
899 default:
900 return -ENODEV;
901 }
902}
903
904static long
905core99_gmac_enable(struct device_node* node, long param, long value)
906{
907 unsigned long flags;
908
909 LOCK(flags);
910 if (value)
911 UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_GMAC);
912 else
913 UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_GMAC);
914 (void)UN_IN(UNI_N_CLOCK_CNTL);
915 UNLOCK(flags);
916 udelay(20);
917
918 return 0;
919}
920
921static long
922core99_gmac_phy_reset(struct device_node* node, long param, long value)
923{
924 unsigned long flags;
925 struct macio_chip* macio;
926
927 macio = &macio_chips[0];
928 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
929 macio->type != macio_intrepid)
930 return -ENODEV;
931
932 LOCK(flags);
933 MACIO_OUT8(KL_GPIO_ETH_PHY_RESET, KEYLARGO_GPIO_OUTPUT_ENABLE);
934 (void)MACIO_IN8(KL_GPIO_ETH_PHY_RESET);
935 UNLOCK(flags);
936 mdelay(10);
937 LOCK(flags);
938 MACIO_OUT8(KL_GPIO_ETH_PHY_RESET, /*KEYLARGO_GPIO_OUTPUT_ENABLE | */
939 KEYLARGO_GPIO_OUTOUT_DATA);
940 UNLOCK(flags);
941 mdelay(10);
942
943 return 0;
944}
945
946static long
947core99_sound_chip_enable(struct device_node* node, long param, long value)
948{
949 struct macio_chip* macio;
950 unsigned long flags;
951
952 macio = macio_find(node, 0);
953 if (!macio)
954 return -ENODEV;
955
956 /* Do a better probe code, screamer G4 desktops &
957 * iMacs can do that too, add a recalibrate in
958 * the driver as well
959 */
960 if (pmac_mb.model_id == PMAC_TYPE_PISMO ||
961 pmac_mb.model_id == PMAC_TYPE_TITANIUM) {
962 LOCK(flags);
963 if (value)
964 MACIO_OUT8(KL_GPIO_SOUND_POWER,
965 KEYLARGO_GPIO_OUTPUT_ENABLE |
966 KEYLARGO_GPIO_OUTOUT_DATA);
967 else
968 MACIO_OUT8(KL_GPIO_SOUND_POWER,
969 KEYLARGO_GPIO_OUTPUT_ENABLE);
970 (void)MACIO_IN8(KL_GPIO_SOUND_POWER);
971 UNLOCK(flags);
972 }
973 return 0;
974}
975
976static long
977core99_airport_enable(struct device_node* node, long param, long value)
978{
979 struct macio_chip* macio;
980 unsigned long flags;
981 int state;
982
983 macio = macio_find(node, 0);
984 if (!macio)
985 return -ENODEV;
986
987 /* Hint: we allow passing of macio itself for the sake of the
988 * sleep code
989 */
990 if (node != macio->of_node &&
991 (!node->parent || node->parent != macio->of_node))
992 return -ENODEV;
993 state = (macio->flags & MACIO_FLAG_AIRPORT_ON) != 0;
994 if (value == state)
995 return 0;
996 if (value) {
997 /* This code is a reproduction of OF enable-cardslot
998 * and init-wireless methods, slightly hacked until
999 * I got it working.
1000 */
1001 LOCK(flags);
1002 MACIO_OUT8(KEYLARGO_GPIO_0+0xf, 5);
1003 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xf);
1004 UNLOCK(flags);
1005 mdelay(10);
1006 LOCK(flags);
1007 MACIO_OUT8(KEYLARGO_GPIO_0+0xf, 4);
1008 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xf);
1009 UNLOCK(flags);
1010
1011 mdelay(10);
1012
1013 LOCK(flags);
1014 MACIO_BIC(KEYLARGO_FCR2, KL2_CARDSEL_16);
1015 (void)MACIO_IN32(KEYLARGO_FCR2);
1016 udelay(10);
1017 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xb, 0);
1018 (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xb);
1019 udelay(10);
1020 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xa, 0x28);
1021 (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xa);
1022 udelay(10);
1023 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xd, 0x28);
1024 (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xd);
1025 udelay(10);
1026 MACIO_OUT8(KEYLARGO_GPIO_0+0xd, 0x28);
1027 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xd);
1028 udelay(10);
1029 MACIO_OUT8(KEYLARGO_GPIO_0+0xe, 0x28);
1030 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xe);
1031 UNLOCK(flags);
1032 udelay(10);
1033 MACIO_OUT32(0x1c000, 0);
1034 mdelay(1);
1035 MACIO_OUT8(0x1a3e0, 0x41);
1036 (void)MACIO_IN8(0x1a3e0);
1037 udelay(10);
1038 LOCK(flags);
1039 MACIO_BIS(KEYLARGO_FCR2, KL2_CARDSEL_16);
1040 (void)MACIO_IN32(KEYLARGO_FCR2);
1041 UNLOCK(flags);
1042 mdelay(100);
1043
1044 macio->flags |= MACIO_FLAG_AIRPORT_ON;
1045 } else {
1046 LOCK(flags);
1047 MACIO_BIC(KEYLARGO_FCR2, KL2_CARDSEL_16);
1048 (void)MACIO_IN32(KEYLARGO_FCR2);
1049 MACIO_OUT8(KL_GPIO_AIRPORT_0, 0);
1050 MACIO_OUT8(KL_GPIO_AIRPORT_1, 0);
1051 MACIO_OUT8(KL_GPIO_AIRPORT_2, 0);
1052 MACIO_OUT8(KL_GPIO_AIRPORT_3, 0);
1053 MACIO_OUT8(KL_GPIO_AIRPORT_4, 0);
1054 (void)MACIO_IN8(KL_GPIO_AIRPORT_4);
1055 UNLOCK(flags);
1056
1057 macio->flags &= ~MACIO_FLAG_AIRPORT_ON;
1058 }
1059 return 0;
1060}
1061
1062#ifdef CONFIG_SMP
1063static long
1064core99_reset_cpu(struct device_node* node, long param, long value)
1065{
1066 unsigned int reset_io = 0;
1067 unsigned long flags;
1068 struct macio_chip* macio;
1069 struct device_node* np;
1070 const int dflt_reset_lines[] = { KL_GPIO_RESET_CPU0,
1071 KL_GPIO_RESET_CPU1,
1072 KL_GPIO_RESET_CPU2,
1073 KL_GPIO_RESET_CPU3 };
1074
1075 macio = &macio_chips[0];
1076 if (macio->type != macio_keylargo)
1077 return -ENODEV;
1078
1079 np = find_path_device("/cpus");
1080 if (np == NULL)
1081 return -ENODEV;
1082 for (np = np->child; np != NULL; np = np->sibling) {
1083 u32* num = (u32 *)get_property(np, "reg", NULL);
1084 u32* rst = (u32 *)get_property(np, "soft-reset", NULL);
1085 if (num == NULL || rst == NULL)
1086 continue;
1087 if (param == *num) {
1088 reset_io = *rst;
1089 break;
1090 }
1091 }
1092 if (np == NULL || reset_io == 0)
1093 reset_io = dflt_reset_lines[param];
1094
1095 LOCK(flags);
1096 MACIO_OUT8(reset_io, KEYLARGO_GPIO_OUTPUT_ENABLE);
1097 (void)MACIO_IN8(reset_io);
1098 udelay(1);
1099 MACIO_OUT8(reset_io, 0);
1100 (void)MACIO_IN8(reset_io);
1101 UNLOCK(flags);
1102
1103 return 0;
1104}
1105#endif /* CONFIG_SMP */
1106
1107static long
1108core99_usb_enable(struct device_node* node, long param, long value)
1109{
1110 struct macio_chip* macio;
1111 unsigned long flags;
1112 char* prop;
1113 int number;
1114 u32 reg;
1115
1116 macio = &macio_chips[0];
1117 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1118 macio->type != macio_intrepid)
1119 return -ENODEV;
1120
1121 prop = (char *)get_property(node, "AAPL,clock-id", NULL);
1122 if (!prop)
1123 return -ENODEV;
1124 if (strncmp(prop, "usb0u048", 8) == 0)
1125 number = 0;
1126 else if (strncmp(prop, "usb1u148", 8) == 0)
1127 number = 2;
1128 else if (strncmp(prop, "usb2u248", 8) == 0)
1129 number = 4;
1130 else
1131 return -ENODEV;
1132
1133 /* Sorry for the brute-force locking, but this is only used during
1134 * sleep and the timing seem to be critical
1135 */
1136 LOCK(flags);
1137 if (value) {
1138 /* Turn ON */
1139 if (number == 0) {
1140 MACIO_BIC(KEYLARGO_FCR0, (KL0_USB0_PAD_SUSPEND0 | KL0_USB0_PAD_SUSPEND1));
1141 (void)MACIO_IN32(KEYLARGO_FCR0);
1142 UNLOCK(flags);
1143 mdelay(1);
1144 LOCK(flags);
1145 MACIO_BIS(KEYLARGO_FCR0, KL0_USB0_CELL_ENABLE);
1146 } else if (number == 2) {
1147 MACIO_BIC(KEYLARGO_FCR0, (KL0_USB1_PAD_SUSPEND0 | KL0_USB1_PAD_SUSPEND1));
1148 UNLOCK(flags);
1149 (void)MACIO_IN32(KEYLARGO_FCR0);
1150 mdelay(1);
1151 LOCK(flags);
1152 MACIO_BIS(KEYLARGO_FCR0, KL0_USB1_CELL_ENABLE);
1153 } else if (number == 4) {
1154 MACIO_BIC(KEYLARGO_FCR1, (KL1_USB2_PAD_SUSPEND0 | KL1_USB2_PAD_SUSPEND1));
1155 UNLOCK(flags);
1156 (void)MACIO_IN32(KEYLARGO_FCR1);
1157 mdelay(1);
1158 LOCK(flags);
1159 MACIO_BIS(KEYLARGO_FCR1, KL1_USB2_CELL_ENABLE);
1160 }
1161 if (number < 4) {
1162 reg = MACIO_IN32(KEYLARGO_FCR4);
1163 reg &= ~(KL4_PORT_WAKEUP_ENABLE(number) | KL4_PORT_RESUME_WAKE_EN(number) |
1164 KL4_PORT_CONNECT_WAKE_EN(number) | KL4_PORT_DISCONNECT_WAKE_EN(number));
1165 reg &= ~(KL4_PORT_WAKEUP_ENABLE(number+1) | KL4_PORT_RESUME_WAKE_EN(number+1) |
1166 KL4_PORT_CONNECT_WAKE_EN(number+1) | KL4_PORT_DISCONNECT_WAKE_EN(number+1));
1167 MACIO_OUT32(KEYLARGO_FCR4, reg);
1168 (void)MACIO_IN32(KEYLARGO_FCR4);
1169 udelay(10);
1170 } else {
1171 reg = MACIO_IN32(KEYLARGO_FCR3);
1172 reg &= ~(KL3_IT_PORT_WAKEUP_ENABLE(0) | KL3_IT_PORT_RESUME_WAKE_EN(0) |
1173 KL3_IT_PORT_CONNECT_WAKE_EN(0) | KL3_IT_PORT_DISCONNECT_WAKE_EN(0));
1174 reg &= ~(KL3_IT_PORT_WAKEUP_ENABLE(1) | KL3_IT_PORT_RESUME_WAKE_EN(1) |
1175 KL3_IT_PORT_CONNECT_WAKE_EN(1) | KL3_IT_PORT_DISCONNECT_WAKE_EN(1));
1176 MACIO_OUT32(KEYLARGO_FCR3, reg);
1177 (void)MACIO_IN32(KEYLARGO_FCR3);
1178 udelay(10);
1179 }
1180 if (macio->type == macio_intrepid) {
1181 /* wait for clock stopped bits to clear */
1182 u32 test0 = 0, test1 = 0;
1183 u32 status0, status1;
1184 int timeout = 1000;
1185
1186 UNLOCK(flags);
1187 switch (number) {
1188 case 0:
1189 test0 = UNI_N_CLOCK_STOPPED_USB0;
1190 test1 = UNI_N_CLOCK_STOPPED_USB0PCI;
1191 break;
1192 case 2:
1193 test0 = UNI_N_CLOCK_STOPPED_USB1;
1194 test1 = UNI_N_CLOCK_STOPPED_USB1PCI;
1195 break;
1196 case 4:
1197 test0 = UNI_N_CLOCK_STOPPED_USB2;
1198 test1 = UNI_N_CLOCK_STOPPED_USB2PCI;
1199 break;
1200 }
1201 do {
1202 if (--timeout <= 0) {
1203 printk(KERN_ERR "core99_usb_enable: "
1204 "Timeout waiting for clocks\n");
1205 break;
1206 }
1207 mdelay(1);
1208 status0 = UN_IN(UNI_N_CLOCK_STOP_STATUS0);
1209 status1 = UN_IN(UNI_N_CLOCK_STOP_STATUS1);
1210 } while ((status0 & test0) | (status1 & test1));
1211 LOCK(flags);
1212 }
1213 } else {
1214 /* Turn OFF */
1215 if (number < 4) {
1216 reg = MACIO_IN32(KEYLARGO_FCR4);
1217 reg |= KL4_PORT_WAKEUP_ENABLE(number) | KL4_PORT_RESUME_WAKE_EN(number) |
1218 KL4_PORT_CONNECT_WAKE_EN(number) | KL4_PORT_DISCONNECT_WAKE_EN(number);
1219 reg |= KL4_PORT_WAKEUP_ENABLE(number+1) | KL4_PORT_RESUME_WAKE_EN(number+1) |
1220 KL4_PORT_CONNECT_WAKE_EN(number+1) | KL4_PORT_DISCONNECT_WAKE_EN(number+1);
1221 MACIO_OUT32(KEYLARGO_FCR4, reg);
1222 (void)MACIO_IN32(KEYLARGO_FCR4);
1223 udelay(1);
1224 } else {
1225 reg = MACIO_IN32(KEYLARGO_FCR3);
1226 reg |= KL3_IT_PORT_WAKEUP_ENABLE(0) | KL3_IT_PORT_RESUME_WAKE_EN(0) |
1227 KL3_IT_PORT_CONNECT_WAKE_EN(0) | KL3_IT_PORT_DISCONNECT_WAKE_EN(0);
1228 reg |= KL3_IT_PORT_WAKEUP_ENABLE(1) | KL3_IT_PORT_RESUME_WAKE_EN(1) |
1229 KL3_IT_PORT_CONNECT_WAKE_EN(1) | KL3_IT_PORT_DISCONNECT_WAKE_EN(1);
1230 MACIO_OUT32(KEYLARGO_FCR3, reg);
1231 (void)MACIO_IN32(KEYLARGO_FCR3);
1232 udelay(1);
1233 }
1234 if (number == 0) {
1235 if (macio->type != macio_intrepid)
1236 MACIO_BIC(KEYLARGO_FCR0, KL0_USB0_CELL_ENABLE);
1237 (void)MACIO_IN32(KEYLARGO_FCR0);
1238 udelay(1);
1239 MACIO_BIS(KEYLARGO_FCR0, (KL0_USB0_PAD_SUSPEND0 | KL0_USB0_PAD_SUSPEND1));
1240 (void)MACIO_IN32(KEYLARGO_FCR0);
1241 } else if (number == 2) {
1242 if (macio->type != macio_intrepid)
1243 MACIO_BIC(KEYLARGO_FCR0, KL0_USB1_CELL_ENABLE);
1244 (void)MACIO_IN32(KEYLARGO_FCR0);
1245 udelay(1);
1246 MACIO_BIS(KEYLARGO_FCR0, (KL0_USB1_PAD_SUSPEND0 | KL0_USB1_PAD_SUSPEND1));
1247 (void)MACIO_IN32(KEYLARGO_FCR0);
1248 } else if (number == 4) {
1249 udelay(1);
1250 MACIO_BIS(KEYLARGO_FCR1, (KL1_USB2_PAD_SUSPEND0 | KL1_USB2_PAD_SUSPEND1));
1251 (void)MACIO_IN32(KEYLARGO_FCR1);
1252 }
1253 udelay(1);
1254 }
1255 UNLOCK(flags);
1256
1257 return 0;
1258}
1259
1260static long
1261core99_firewire_enable(struct device_node* node, long param, long value)
1262{
1263 unsigned long flags;
1264 struct macio_chip* macio;
1265
1266 macio = &macio_chips[0];
1267 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1268 macio->type != macio_intrepid)
1269 return -ENODEV;
1270 if (!(macio->flags & MACIO_FLAG_FW_SUPPORTED))
1271 return -ENODEV;
1272
1273 LOCK(flags);
1274 if (value) {
1275 UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_FW);
1276 (void)UN_IN(UNI_N_CLOCK_CNTL);
1277 } else {
1278 UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_FW);
1279 (void)UN_IN(UNI_N_CLOCK_CNTL);
1280 }
1281 UNLOCK(flags);
1282 mdelay(1);
1283
1284 return 0;
1285}
1286
1287static long
1288core99_firewire_cable_power(struct device_node* node, long param, long value)
1289{
1290 unsigned long flags;
1291 struct macio_chip* macio;
1292
1293 /* Trick: we allow NULL node */
1294 if ((pmac_mb.board_flags & PMAC_MB_HAS_FW_POWER) == 0)
1295 return -ENODEV;
1296 macio = &macio_chips[0];
1297 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1298 macio->type != macio_intrepid)
1299 return -ENODEV;
1300 if (!(macio->flags & MACIO_FLAG_FW_SUPPORTED))
1301 return -ENODEV;
1302
1303 LOCK(flags);
1304 if (value) {
1305 MACIO_OUT8(KL_GPIO_FW_CABLE_POWER , 0);
1306 MACIO_IN8(KL_GPIO_FW_CABLE_POWER);
1307 udelay(10);
1308 } else {
1309 MACIO_OUT8(KL_GPIO_FW_CABLE_POWER , 4);
1310 MACIO_IN8(KL_GPIO_FW_CABLE_POWER); udelay(10);
1311 }
1312 UNLOCK(flags);
1313 mdelay(1);
1314
1315 return 0;
1316}
1317
1318static long
1319intrepid_aack_delay_enable(struct device_node* node, long param, long value)
1320{
1321 unsigned long flags;
1322
1323 if (uninorth_rev < 0xd2)
1324 return -ENODEV;
1325
1326 LOCK(flags);
1327 if (param)
1328 UN_BIS(UNI_N_AACK_DELAY, UNI_N_AACK_DELAY_ENABLE);
1329 else
1330 UN_BIC(UNI_N_AACK_DELAY, UNI_N_AACK_DELAY_ENABLE);
1331 UNLOCK(flags);
1332
1333 return 0;
1334}
1335
1336
1337#endif /* CONFIG_POWER4 */
1338
1339static long
1340core99_read_gpio(struct device_node* node, long param, long value)
1341{
1342 struct macio_chip* macio = &macio_chips[0];
1343
1344 return MACIO_IN8(param);
1345}
1346
1347
1348static long
1349core99_write_gpio(struct device_node* node, long param, long value)
1350{
1351 struct macio_chip* macio = &macio_chips[0];
1352
1353 MACIO_OUT8(param, (u8)(value & 0xff));
1354 return 0;
1355}
1356
1357#ifdef CONFIG_POWER4
1358
1359static long
1360g5_gmac_enable(struct device_node* node, long param, long value)
1361{
1362 struct macio_chip* macio = &macio_chips[0];
1363 unsigned long flags;
1364 u8 pbus, pid;
1365
1366 LOCK(flags);
1367 if (value) {
1368 MACIO_BIS(KEYLARGO_FCR1, K2_FCR1_GMAC_CLK_ENABLE);
1369 mb();
1370 k2_skiplist[0] = NULL;
1371 } else {
1372 k2_skiplist[0] = node;
1373 mb();
1374 MACIO_BIC(KEYLARGO_FCR1, K2_FCR1_GMAC_CLK_ENABLE);
1375 }
1376
1377 UNLOCK(flags);
1378 mdelay(1);
1379
1380 return 0;
1381}
1382
1383static long
1384g5_fw_enable(struct device_node* node, long param, long value)
1385{
1386 struct macio_chip* macio = &macio_chips[0];
1387 unsigned long flags;
1388
1389 LOCK(flags);
1390 if (value) {
1391 MACIO_BIS(KEYLARGO_FCR1, K2_FCR1_FW_CLK_ENABLE);
1392 mb();
1393 k2_skiplist[1] = NULL;
1394 } else {
1395 k2_skiplist[1] = node;
1396 mb();
1397 MACIO_BIC(KEYLARGO_FCR1, K2_FCR1_FW_CLK_ENABLE);
1398 }
1399
1400 UNLOCK(flags);
1401 mdelay(1);
1402
1403 return 0;
1404}
1405
1406static long
1407g5_mpic_enable(struct device_node* node, long param, long value)
1408{
1409 unsigned long flags;
1410
1411 if (node->parent == NULL || strcmp(node->parent->name, "u3"))
1412 return 0;
1413
1414 LOCK(flags);
1415 UN_BIS(U3_TOGGLE_REG, U3_MPIC_RESET | U3_MPIC_OUTPUT_ENABLE);
1416 UNLOCK(flags);
1417
1418 return 0;
1419}
1420
1421#ifdef CONFIG_SMP
1422static long
1423g5_reset_cpu(struct device_node* node, long param, long value)
1424{
1425 unsigned int reset_io = 0;
1426 unsigned long flags;
1427 struct macio_chip* macio;
1428 struct device_node* np;
1429
1430 macio = &macio_chips[0];
1431 if (macio->type != macio_keylargo2)
1432 return -ENODEV;
1433
1434 np = find_path_device("/cpus");
1435 if (np == NULL)
1436 return -ENODEV;
1437 for (np = np->child; np != NULL; np = np->sibling) {
1438 u32* num = (u32 *)get_property(np, "reg", NULL);
1439 u32* rst = (u32 *)get_property(np, "soft-reset", NULL);
1440 if (num == NULL || rst == NULL)
1441 continue;
1442 if (param == *num) {
1443 reset_io = *rst;
1444 break;
1445 }
1446 }
1447 if (np == NULL || reset_io == 0)
1448 return -ENODEV;
1449
1450 LOCK(flags);
1451 MACIO_OUT8(reset_io, KEYLARGO_GPIO_OUTPUT_ENABLE);
1452 (void)MACIO_IN8(reset_io);
1453 udelay(1);
1454 MACIO_OUT8(reset_io, 0);
1455 (void)MACIO_IN8(reset_io);
1456 UNLOCK(flags);
1457
1458 return 0;
1459}
1460#endif /* CONFIG_SMP */
1461
1462/*
1463 * This can be called from pmac_smp so isn't static
1464 *
1465 * This takes the second CPU off the bus on dual CPU machines
1466 * running UP
1467 */
1468void g5_phy_disable_cpu1(void)
1469{
1470 UN_OUT(U3_API_PHY_CONFIG_1, 0);
1471}
1472
1473#endif /* CONFIG_POWER4 */
1474
1475#ifndef CONFIG_POWER4
1476
1477static void
1478keylargo_shutdown(struct macio_chip* macio, int sleep_mode)
1479{
1480 u32 temp;
1481
1482 if (sleep_mode) {
1483 mdelay(1);
1484 MACIO_BIS(KEYLARGO_FCR0, KL0_USB_REF_SUSPEND);
1485 (void)MACIO_IN32(KEYLARGO_FCR0);
1486 mdelay(1);
1487 }
1488
1489 MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE |
1490 KL0_SCC_CELL_ENABLE |
1491 KL0_IRDA_ENABLE | KL0_IRDA_CLK32_ENABLE |
1492 KL0_IRDA_CLK19_ENABLE);
1493
1494 MACIO_BIC(KEYLARGO_MBCR, KL_MBCR_MB0_DEV_MASK);
1495 MACIO_BIS(KEYLARGO_MBCR, KL_MBCR_MB0_IDE_ENABLE);
1496
1497 MACIO_BIC(KEYLARGO_FCR1,
1498 KL1_AUDIO_SEL_22MCLK | KL1_AUDIO_CLK_ENABLE_BIT |
1499 KL1_AUDIO_CLK_OUT_ENABLE | KL1_AUDIO_CELL_ENABLE |
1500 KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT |
1501 KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE |
1502 KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE |
1503 KL1_EIDE0_ENABLE | KL1_EIDE0_RESET_N |
1504 KL1_EIDE1_ENABLE | KL1_EIDE1_RESET_N |
1505 KL1_UIDE_ENABLE);
1506
1507 MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);
1508 MACIO_BIC(KEYLARGO_FCR2, KL2_IOBUS_ENABLE);
1509
1510 temp = MACIO_IN32(KEYLARGO_FCR3);
1511 if (macio->rev >= 2) {
1512 temp |= KL3_SHUTDOWN_PLL2X;
1513 if (sleep_mode)
1514 temp |= KL3_SHUTDOWN_PLL_TOTAL;
1515 }
1516
1517 temp |= KL3_SHUTDOWN_PLLKW6 | KL3_SHUTDOWN_PLLKW4 |
1518 KL3_SHUTDOWN_PLLKW35;
1519 if (sleep_mode)
1520 temp |= KL3_SHUTDOWN_PLLKW12;
1521 temp &= ~(KL3_CLK66_ENABLE | KL3_CLK49_ENABLE | KL3_CLK45_ENABLE
1522 | KL3_CLK31_ENABLE | KL3_I2S1_CLK18_ENABLE | KL3_I2S0_CLK18_ENABLE);
1523 if (sleep_mode)
1524 temp &= ~(KL3_TIMER_CLK18_ENABLE | KL3_VIA_CLK16_ENABLE);
1525 MACIO_OUT32(KEYLARGO_FCR3, temp);
1526
1527 /* Flush posted writes & wait a bit */
1528 (void)MACIO_IN32(KEYLARGO_FCR0); mdelay(1);
1529}
1530
1531static void
1532pangea_shutdown(struct macio_chip* macio, int sleep_mode)
1533{
1534 u32 temp;
1535
1536 MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE |
1537 KL0_SCC_CELL_ENABLE |
1538 KL0_USB0_CELL_ENABLE | KL0_USB1_CELL_ENABLE);
1539
1540 MACIO_BIC(KEYLARGO_FCR1,
1541 KL1_AUDIO_SEL_22MCLK | KL1_AUDIO_CLK_ENABLE_BIT |
1542 KL1_AUDIO_CLK_OUT_ENABLE | KL1_AUDIO_CELL_ENABLE |
1543 KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT |
1544 KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE |
1545 KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE |
1546 KL1_UIDE_ENABLE);
1547 if (pmac_mb.board_flags & PMAC_MB_MOBILE)
1548 MACIO_BIC(KEYLARGO_FCR1, KL1_UIDE_RESET_N);
1549
1550 MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);
1551
1552 temp = MACIO_IN32(KEYLARGO_FCR3);
1553 temp |= KL3_SHUTDOWN_PLLKW6 | KL3_SHUTDOWN_PLLKW4 |
1554 KL3_SHUTDOWN_PLLKW35;
1555 temp &= ~(KL3_CLK49_ENABLE | KL3_CLK45_ENABLE | KL3_CLK31_ENABLE
1556 | KL3_I2S0_CLK18_ENABLE | KL3_I2S1_CLK18_ENABLE);
1557 if (sleep_mode)
1558 temp &= ~(KL3_VIA_CLK16_ENABLE | KL3_TIMER_CLK18_ENABLE);
1559 MACIO_OUT32(KEYLARGO_FCR3, temp);
1560
1561 /* Flush posted writes & wait a bit */
1562 (void)MACIO_IN32(KEYLARGO_FCR0); mdelay(1);
1563}
1564
1565static void
1566intrepid_shutdown(struct macio_chip* macio, int sleep_mode)
1567{
1568 u32 temp;
1569
1570 MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE |
1571 KL0_SCC_CELL_ENABLE);
1572
1573 MACIO_BIC(KEYLARGO_FCR1,
1574 /*KL1_USB2_CELL_ENABLE |*/
1575 KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT |
1576 KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE |
1577 KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE);
1578 if (pmac_mb.board_flags & PMAC_MB_MOBILE)
1579 MACIO_BIC(KEYLARGO_FCR1, KL1_UIDE_RESET_N);
1580
1581 temp = MACIO_IN32(KEYLARGO_FCR3);
1582 temp &= ~(KL3_CLK49_ENABLE | KL3_CLK45_ENABLE |
1583 KL3_I2S1_CLK18_ENABLE | KL3_I2S0_CLK18_ENABLE);
1584 if (sleep_mode)
1585 temp &= ~(KL3_TIMER_CLK18_ENABLE | KL3_IT_VIA_CLK32_ENABLE);
1586 MACIO_OUT32(KEYLARGO_FCR3, temp);
1587
1588 /* Flush posted writes & wait a bit */
1589 (void)MACIO_IN32(KEYLARGO_FCR0);
1590 mdelay(10);
1591}
1592
1593
1594void pmac_tweak_clock_spreading(int enable)
1595{
1596 struct macio_chip* macio = &macio_chips[0];
1597
1598 /* Hack for doing clock spreading on some machines PowerBooks and
1599 * iBooks. This implements the "platform-do-clockspreading" OF
1600 * property as decoded manually on various models. For safety, we also
1601 * check the product ID in the device-tree in cases we'll whack the i2c
1602 * chip to make reasonably sure we won't set wrong values in there
1603 *
1604 * Of course, ultimately, we have to implement a real parser for
1605 * the platform-do-* stuff...
1606 */
1607
1608 if (macio->type == macio_intrepid) {
1609 struct device_node *clock =
1610 of_find_node_by_path("/uni-n@f8000000/hw-clock");
1611 if (clock && get_property(clock, "platform-do-clockspreading",
1612 NULL)) {
1613 printk(KERN_INFO "%sabling clock spreading on Intrepid"
1614 " ASIC\n", enable ? "En" : "Dis");
1615 if (enable)
1616 UN_OUT(UNI_N_CLOCK_SPREADING, 2);
1617 else
1618 UN_OUT(UNI_N_CLOCK_SPREADING, 0);
1619 mdelay(40);
1620 }
1621 of_node_put(clock);
1622 }
1623
1624 while (machine_is_compatible("PowerBook5,2") ||
1625 machine_is_compatible("PowerBook5,3") ||
1626 machine_is_compatible("PowerBook6,2") ||
1627 machine_is_compatible("PowerBook6,3")) {
1628 struct device_node *ui2c = of_find_node_by_type(NULL, "i2c");
1629 struct device_node *dt = of_find_node_by_name(NULL, "device-tree");
1630 u8 buffer[9];
1631 u32 *productID;
1632 int i, rc, changed = 0;
1633
1634 if (dt == NULL)
1635 break;
1636 productID = (u32 *)get_property(dt, "pid#", NULL);
1637 if (productID == NULL)
1638 break;
1639 while(ui2c) {
1640 struct device_node *p = of_get_parent(ui2c);
1641 if (p && !strcmp(p->name, "uni-n"))
1642 break;
1643 ui2c = of_find_node_by_type(ui2c, "i2c");
1644 }
1645 if (ui2c == NULL)
1646 break;
1647 DBG("Trying to bump clock speed for PID: %08x...\n", *productID);
1648 rc = pmac_low_i2c_open(ui2c, 1);
1649 if (rc != 0)
1650 break;
1651 pmac_low_i2c_setmode(ui2c, pmac_low_i2c_mode_combined);
1652 rc = pmac_low_i2c_xfer(ui2c, 0xd2 | pmac_low_i2c_read, 0x80, buffer, 9);
1653 DBG("read result: %d,", rc);
1654 if (rc != 0) {
1655 pmac_low_i2c_close(ui2c);
1656 break;
1657 }
1658 for (i=0; i<9; i++)
1659 DBG(" %02x", buffer[i]);
1660 DBG("\n");
1661
1662 switch(*productID) {
1663 case 0x1182: /* AlBook 12" rev 2 */
1664 case 0x1183: /* iBook G4 12" */
1665 buffer[0] = (buffer[0] & 0x8f) | 0x70;
1666 buffer[2] = (buffer[2] & 0x7f) | 0x00;
1667 buffer[5] = (buffer[5] & 0x80) | 0x31;
1668 buffer[6] = (buffer[6] & 0x40) | 0xb0;
1669 buffer[7] = (buffer[7] & 0x00) | (enable ? 0xc0 : 0xba);
1670 buffer[8] = (buffer[8] & 0x00) | 0x30;
1671 changed = 1;
1672 break;
1673 case 0x3142: /* AlBook 15" (ATI M10) */
1674 case 0x3143: /* AlBook 17" (ATI M10) */
1675 buffer[0] = (buffer[0] & 0xaf) | 0x50;
1676 buffer[2] = (buffer[2] & 0x7f) | 0x00;
1677 buffer[5] = (buffer[5] & 0x80) | 0x31;
1678 buffer[6] = (buffer[6] & 0x40) | 0xb0;
1679 buffer[7] = (buffer[7] & 0x00) | (enable ? 0xd0 : 0xc0);
1680 buffer[8] = (buffer[8] & 0x00) | 0x30;
1681 changed = 1;
1682 break;
1683 default:
1684 DBG("i2c-hwclock: Machine model not handled\n");
1685 break;
1686 }
1687 if (!changed) {
1688 pmac_low_i2c_close(ui2c);
1689 break;
1690 }
1691 printk(KERN_INFO "%sabling clock spreading on i2c clock chip\n",
1692 enable ? "En" : "Dis");
1693 pmac_low_i2c_setmode(ui2c, pmac_low_i2c_mode_stdsub);
1694 rc = pmac_low_i2c_xfer(ui2c, 0xd2 | pmac_low_i2c_write, 0x80, buffer, 9);
1695 DBG("write result: %d,", rc);
1696 pmac_low_i2c_setmode(ui2c, pmac_low_i2c_mode_combined);
1697 rc = pmac_low_i2c_xfer(ui2c, 0xd2 | pmac_low_i2c_read, 0x80, buffer, 9);
1698 DBG("read result: %d,", rc);
1699 if (rc != 0) {
1700 pmac_low_i2c_close(ui2c);
1701 break;
1702 }
1703 for (i=0; i<9; i++)
1704 DBG(" %02x", buffer[i]);
1705 pmac_low_i2c_close(ui2c);
1706 break;
1707 }
1708}
1709
1710
1711static int
1712core99_sleep(void)
1713{
1714 struct macio_chip* macio;
1715 int i;
1716
1717 macio = &macio_chips[0];
1718 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1719 macio->type != macio_intrepid)
1720 return -ENODEV;
1721
1722 /* We power off the wireless slot in case it was not done
1723 * by the driver. We don't power it on automatically however
1724 */
1725 if (macio->flags & MACIO_FLAG_AIRPORT_ON)
1726 core99_airport_enable(macio->of_node, 0, 0);
1727
1728 /* We power off the FW cable. Should be done by the driver... */
1729 if (macio->flags & MACIO_FLAG_FW_SUPPORTED) {
1730 core99_firewire_enable(NULL, 0, 0);
1731 core99_firewire_cable_power(NULL, 0, 0);
1732 }
1733
1734 /* We make sure int. modem is off (in case driver lost it) */
1735 if (macio->type == macio_keylargo)
1736 core99_modem_enable(macio->of_node, 0, 0);
1737 else
1738 pangea_modem_enable(macio->of_node, 0, 0);
1739
1740 /* We make sure the sound is off as well */
1741 core99_sound_chip_enable(macio->of_node, 0, 0);
1742
1743 /*
1744 * Save various bits of KeyLargo
1745 */
1746
1747 /* Save the state of the various GPIOs */
1748 save_gpio_levels[0] = MACIO_IN32(KEYLARGO_GPIO_LEVELS0);
1749 save_gpio_levels[1] = MACIO_IN32(KEYLARGO_GPIO_LEVELS1);
1750 for (i=0; i<KEYLARGO_GPIO_EXTINT_CNT; i++)
1751 save_gpio_extint[i] = MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+i);
1752 for (i=0; i<KEYLARGO_GPIO_CNT; i++)
1753 save_gpio_normal[i] = MACIO_IN8(KEYLARGO_GPIO_0+i);
1754
1755 /* Save the FCRs */
1756 if (macio->type == macio_keylargo)
1757 save_mbcr = MACIO_IN32(KEYLARGO_MBCR);
1758 save_fcr[0] = MACIO_IN32(KEYLARGO_FCR0);
1759 save_fcr[1] = MACIO_IN32(KEYLARGO_FCR1);
1760 save_fcr[2] = MACIO_IN32(KEYLARGO_FCR2);
1761 save_fcr[3] = MACIO_IN32(KEYLARGO_FCR3);
1762 save_fcr[4] = MACIO_IN32(KEYLARGO_FCR4);
1763 if (macio->type == macio_pangea || macio->type == macio_intrepid)
1764 save_fcr[5] = MACIO_IN32(KEYLARGO_FCR5);
1765
1766 /* Save state & config of DBDMA channels */
1767 dbdma_save(macio, save_dbdma);
1768
1769 /*
1770 * Turn off as much as we can
1771 */
1772 if (macio->type == macio_pangea)
1773 pangea_shutdown(macio, 1);
1774 else if (macio->type == macio_intrepid)
1775 intrepid_shutdown(macio, 1);
1776 else if (macio->type == macio_keylargo)
1777 keylargo_shutdown(macio, 1);
1778
1779 /*
1780 * Put the host bridge to sleep
1781 */
1782
1783 save_unin_clock_ctl = UN_IN(UNI_N_CLOCK_CNTL);
1784 /* Note: do not switch GMAC off, driver does it when necessary, WOL must keep it
1785 * enabled !
1786 */
1787 UN_OUT(UNI_N_CLOCK_CNTL, save_unin_clock_ctl &
1788 ~(/*UNI_N_CLOCK_CNTL_GMAC|*/UNI_N_CLOCK_CNTL_FW/*|UNI_N_CLOCK_CNTL_PCI*/));
1789 udelay(100);
1790 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_SLEEPING);
1791 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_SLEEP);
1792 mdelay(10);
1793
1794 /*
1795 * FIXME: A bit of black magic with OpenPIC (don't ask me why)
1796 */
1797 if (pmac_mb.model_id == PMAC_TYPE_SAWTOOTH) {
1798 MACIO_BIS(0x506e0, 0x00400000);
1799 MACIO_BIS(0x506e0, 0x80000000);
1800 }
1801 return 0;
1802}
1803
1804static int
1805core99_wake_up(void)
1806{
1807 struct macio_chip* macio;
1808 int i;
1809
1810 macio = &macio_chips[0];
1811 if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1812 macio->type != macio_intrepid)
1813 return -ENODEV;
1814
1815 /*
1816 * Wakeup the host bridge
1817 */
1818 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_NORMAL);
1819 udelay(10);
1820 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_RUNNING);
1821 udelay(10);
1822
1823 /*
1824 * Restore KeyLargo
1825 */
1826
1827 if (macio->type == macio_keylargo) {
1828 MACIO_OUT32(KEYLARGO_MBCR, save_mbcr);
1829 (void)MACIO_IN32(KEYLARGO_MBCR); udelay(10);
1830 }
1831 MACIO_OUT32(KEYLARGO_FCR0, save_fcr[0]);
1832 (void)MACIO_IN32(KEYLARGO_FCR0); udelay(10);
1833 MACIO_OUT32(KEYLARGO_FCR1, save_fcr[1]);
1834 (void)MACIO_IN32(KEYLARGO_FCR1); udelay(10);
1835 MACIO_OUT32(KEYLARGO_FCR2, save_fcr[2]);
1836 (void)MACIO_IN32(KEYLARGO_FCR2); udelay(10);
1837 MACIO_OUT32(KEYLARGO_FCR3, save_fcr[3]);
1838 (void)MACIO_IN32(KEYLARGO_FCR3); udelay(10);
1839 MACIO_OUT32(KEYLARGO_FCR4, save_fcr[4]);
1840 (void)MACIO_IN32(KEYLARGO_FCR4); udelay(10);
1841 if (macio->type == macio_pangea || macio->type == macio_intrepid) {
1842 MACIO_OUT32(KEYLARGO_FCR5, save_fcr[5]);
1843 (void)MACIO_IN32(KEYLARGO_FCR5); udelay(10);
1844 }
1845
1846 dbdma_restore(macio, save_dbdma);
1847
1848 MACIO_OUT32(KEYLARGO_GPIO_LEVELS0, save_gpio_levels[0]);
1849 MACIO_OUT32(KEYLARGO_GPIO_LEVELS1, save_gpio_levels[1]);
1850 for (i=0; i<KEYLARGO_GPIO_EXTINT_CNT; i++)
1851 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+i, save_gpio_extint[i]);
1852 for (i=0; i<KEYLARGO_GPIO_CNT; i++)
1853 MACIO_OUT8(KEYLARGO_GPIO_0+i, save_gpio_normal[i]);
1854
1855 /* FIXME more black magic with OpenPIC ... */
1856 if (pmac_mb.model_id == PMAC_TYPE_SAWTOOTH) {
1857 MACIO_BIC(0x506e0, 0x00400000);
1858 MACIO_BIC(0x506e0, 0x80000000);
1859 }
1860
1861 UN_OUT(UNI_N_CLOCK_CNTL, save_unin_clock_ctl);
1862 udelay(100);
1863
1864 return 0;
1865}
1866
1867static long
1868core99_sleep_state(struct device_node* node, long param, long value)
1869{
1870 /* Param == 1 means to enter the "fake sleep" mode that is
1871 * used for CPU speed switch
1872 */
1873 if (param == 1) {
1874 if (value == 1) {
1875 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_SLEEPING);
1876 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_IDLE2);
1877 } else {
1878 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_NORMAL);
1879 udelay(10);
1880 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_RUNNING);
1881 udelay(10);
1882 }
1883 return 0;
1884 }
1885 if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0)
1886 return -EPERM;
1887
1888 if (value == 1)
1889 return core99_sleep();
1890 else if (value == 0)
1891 return core99_wake_up();
1892 return 0;
1893}
1894
1895#endif /* CONFIG_POWER4 */
1896
1897static long
1898generic_dev_can_wake(struct device_node* node, long param, long value)
1899{
1900 /* Todo: eventually check we are really dealing with on-board
1901 * video device ...
1902 */
1903
1904 if (pmac_mb.board_flags & PMAC_MB_MAY_SLEEP)
1905 pmac_mb.board_flags |= PMAC_MB_CAN_SLEEP;
1906 return 0;
1907}
1908
1909static long
1910generic_get_mb_info(struct device_node* node, long param, long value)
1911{
1912 switch(param) {
1913 case PMAC_MB_INFO_MODEL:
1914 return pmac_mb.model_id;
1915 case PMAC_MB_INFO_FLAGS:
1916 return pmac_mb.board_flags;
1917 case PMAC_MB_INFO_NAME:
1918 /* hack hack hack... but should work */
1919 *((const char **)value) = pmac_mb.model_name;
1920 return 0;
1921 }
1922 return -EINVAL;
1923}
1924
1925
1926/*
1927 * Table definitions
1928 */
1929
1930/* Used on any machine
1931 */
1932static struct feature_table_entry any_features[] = {
1933 { PMAC_FTR_GET_MB_INFO, generic_get_mb_info },
1934 { PMAC_FTR_DEVICE_CAN_WAKE, generic_dev_can_wake },
1935 { 0, NULL }
1936};
1937
1938#ifndef CONFIG_POWER4
1939
1940/* OHare based motherboards. Currently, we only use these on the
1941 * 2400,3400 and 3500 series powerbooks. Some older desktops seem
1942 * to have issues with turning on/off those asic cells
1943 */
1944static struct feature_table_entry ohare_features[] = {
1945 { PMAC_FTR_SCC_ENABLE, ohare_htw_scc_enable },
1946 { PMAC_FTR_SWIM3_ENABLE, ohare_floppy_enable },
1947 { PMAC_FTR_MESH_ENABLE, ohare_mesh_enable },
1948 { PMAC_FTR_IDE_ENABLE, ohare_ide_enable},
1949 { PMAC_FTR_IDE_RESET, ohare_ide_reset},
1950 { PMAC_FTR_SLEEP_STATE, ohare_sleep_state },
1951 { 0, NULL }
1952};
1953
1954/* Heathrow desktop machines (Beige G3).
1955 * Separated as some features couldn't be properly tested
1956 * and the serial port control bits appear to confuse it.
1957 */
1958static struct feature_table_entry heathrow_desktop_features[] = {
1959 { PMAC_FTR_SWIM3_ENABLE, heathrow_floppy_enable },
1960 { PMAC_FTR_MESH_ENABLE, heathrow_mesh_enable },
1961 { PMAC_FTR_IDE_ENABLE, heathrow_ide_enable },
1962 { PMAC_FTR_IDE_RESET, heathrow_ide_reset },
1963 { PMAC_FTR_BMAC_ENABLE, heathrow_bmac_enable },
1964 { 0, NULL }
1965};
1966
1967/* Heathrow based laptop, that is the Wallstreet and mainstreet
1968 * powerbooks.
1969 */
1970static struct feature_table_entry heathrow_laptop_features[] = {
1971 { PMAC_FTR_SCC_ENABLE, ohare_htw_scc_enable },
1972 { PMAC_FTR_MODEM_ENABLE, heathrow_modem_enable },
1973 { PMAC_FTR_SWIM3_ENABLE, heathrow_floppy_enable },
1974 { PMAC_FTR_MESH_ENABLE, heathrow_mesh_enable },
1975 { PMAC_FTR_IDE_ENABLE, heathrow_ide_enable },
1976 { PMAC_FTR_IDE_RESET, heathrow_ide_reset },
1977 { PMAC_FTR_BMAC_ENABLE, heathrow_bmac_enable },
1978 { PMAC_FTR_SOUND_CHIP_ENABLE, heathrow_sound_enable },
1979 { PMAC_FTR_SLEEP_STATE, heathrow_sleep_state },
1980 { 0, NULL }
1981};
1982
1983/* Paddington based machines
1984 * The lombard (101) powerbook, first iMac models, B&W G3 and Yikes G4.
1985 */
1986static struct feature_table_entry paddington_features[] = {
1987 { PMAC_FTR_SCC_ENABLE, ohare_htw_scc_enable },
1988 { PMAC_FTR_MODEM_ENABLE, heathrow_modem_enable },
1989 { PMAC_FTR_SWIM3_ENABLE, heathrow_floppy_enable },
1990 { PMAC_FTR_MESH_ENABLE, heathrow_mesh_enable },
1991 { PMAC_FTR_IDE_ENABLE, heathrow_ide_enable },
1992 { PMAC_FTR_IDE_RESET, heathrow_ide_reset },
1993 { PMAC_FTR_BMAC_ENABLE, heathrow_bmac_enable },
1994 { PMAC_FTR_SOUND_CHIP_ENABLE, heathrow_sound_enable },
1995 { PMAC_FTR_SLEEP_STATE, heathrow_sleep_state },
1996 { 0, NULL }
1997};
1998
1999/* Core99 & MacRISC 2 machines (all machines released since the
2000 * iBook (included), that is all AGP machines, except pangea
2001 * chipset. The pangea chipset is the "combo" UniNorth/KeyLargo
2002 * used on iBook2 & iMac "flow power".
2003 */
2004static struct feature_table_entry core99_features[] = {
2005 { PMAC_FTR_SCC_ENABLE, core99_scc_enable },
2006 { PMAC_FTR_MODEM_ENABLE, core99_modem_enable },
2007 { PMAC_FTR_IDE_ENABLE, core99_ide_enable },
2008 { PMAC_FTR_IDE_RESET, core99_ide_reset },
2009 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable },
2010 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset },
2011 { PMAC_FTR_SOUND_CHIP_ENABLE, core99_sound_chip_enable },
2012 { PMAC_FTR_AIRPORT_ENABLE, core99_airport_enable },
2013 { PMAC_FTR_USB_ENABLE, core99_usb_enable },
2014 { PMAC_FTR_1394_ENABLE, core99_firewire_enable },
2015 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power },
2016 { PMAC_FTR_SLEEP_STATE, core99_sleep_state },
2017#ifdef CONFIG_SMP
2018 { PMAC_FTR_RESET_CPU, core99_reset_cpu },
2019#endif /* CONFIG_SMP */
2020 { PMAC_FTR_READ_GPIO, core99_read_gpio },
2021 { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
2022 { 0, NULL }
2023};
2024
2025/* RackMac
2026 */
2027static struct feature_table_entry rackmac_features[] = {
2028 { PMAC_FTR_SCC_ENABLE, core99_scc_enable },
2029 { PMAC_FTR_IDE_ENABLE, core99_ide_enable },
2030 { PMAC_FTR_IDE_RESET, core99_ide_reset },
2031 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable },
2032 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset },
2033 { PMAC_FTR_USB_ENABLE, core99_usb_enable },
2034 { PMAC_FTR_1394_ENABLE, core99_firewire_enable },
2035 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power },
2036 { PMAC_FTR_SLEEP_STATE, core99_sleep_state },
2037#ifdef CONFIG_SMP
2038 { PMAC_FTR_RESET_CPU, core99_reset_cpu },
2039#endif /* CONFIG_SMP */
2040 { PMAC_FTR_READ_GPIO, core99_read_gpio },
2041 { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
2042 { 0, NULL }
2043};
2044
2045/* Pangea features
2046 */
2047static struct feature_table_entry pangea_features[] = {
2048 { PMAC_FTR_SCC_ENABLE, core99_scc_enable },
2049 { PMAC_FTR_MODEM_ENABLE, pangea_modem_enable },
2050 { PMAC_FTR_IDE_ENABLE, core99_ide_enable },
2051 { PMAC_FTR_IDE_RESET, core99_ide_reset },
2052 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable },
2053 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset },
2054 { PMAC_FTR_SOUND_CHIP_ENABLE, core99_sound_chip_enable },
2055 { PMAC_FTR_AIRPORT_ENABLE, core99_airport_enable },
2056 { PMAC_FTR_USB_ENABLE, core99_usb_enable },
2057 { PMAC_FTR_1394_ENABLE, core99_firewire_enable },
2058 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power },
2059 { PMAC_FTR_SLEEP_STATE, core99_sleep_state },
2060 { PMAC_FTR_READ_GPIO, core99_read_gpio },
2061 { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
2062 { 0, NULL }
2063};
2064
2065/* Intrepid features
2066 */
2067static struct feature_table_entry intrepid_features[] = {
2068 { PMAC_FTR_SCC_ENABLE, core99_scc_enable },
2069 { PMAC_FTR_MODEM_ENABLE, pangea_modem_enable },
2070 { PMAC_FTR_IDE_ENABLE, core99_ide_enable },
2071 { PMAC_FTR_IDE_RESET, core99_ide_reset },
2072 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable },
2073 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset },
2074 { PMAC_FTR_SOUND_CHIP_ENABLE, core99_sound_chip_enable },
2075 { PMAC_FTR_AIRPORT_ENABLE, core99_airport_enable },
2076 { PMAC_FTR_USB_ENABLE, core99_usb_enable },
2077 { PMAC_FTR_1394_ENABLE, core99_firewire_enable },
2078 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power },
2079 { PMAC_FTR_SLEEP_STATE, core99_sleep_state },
2080 { PMAC_FTR_READ_GPIO, core99_read_gpio },
2081 { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
2082 { PMAC_FTR_AACK_DELAY_ENABLE, intrepid_aack_delay_enable },
2083 { 0, NULL }
2084};
2085
2086#else /* CONFIG_POWER4 */
2087
2088/* G5 features
2089 */
2090static struct feature_table_entry g5_features[] = {
2091 { PMAC_FTR_GMAC_ENABLE, g5_gmac_enable },
2092 { PMAC_FTR_1394_ENABLE, g5_fw_enable },
2093 { PMAC_FTR_ENABLE_MPIC, g5_mpic_enable },
2094#ifdef CONFIG_SMP
2095 { PMAC_FTR_RESET_CPU, g5_reset_cpu },
2096#endif /* CONFIG_SMP */
2097 { PMAC_FTR_READ_GPIO, core99_read_gpio },
2098 { PMAC_FTR_WRITE_GPIO, core99_write_gpio },
2099 { 0, NULL }
2100};
2101
2102#endif /* CONFIG_POWER4 */
2103
2104static struct pmac_mb_def pmac_mb_defs[] = {
2105#ifndef CONFIG_POWER4
2106 /*
2107 * Desktops
2108 */
2109
2110 { "AAPL,8500", "PowerMac 8500/8600",
2111 PMAC_TYPE_PSURGE, NULL,
2112 0
2113 },
2114 { "AAPL,9500", "PowerMac 9500/9600",
2115 PMAC_TYPE_PSURGE, NULL,
2116 0
2117 },
2118 { "AAPL,7200", "PowerMac 7200",
2119 PMAC_TYPE_PSURGE, NULL,
2120 0
2121 },
2122 { "AAPL,7300", "PowerMac 7200/7300",
2123 PMAC_TYPE_PSURGE, NULL,
2124 0
2125 },
2126 { "AAPL,7500", "PowerMac 7500",
2127 PMAC_TYPE_PSURGE, NULL,
2128 0
2129 },
2130 { "AAPL,ShinerESB", "Apple Network Server",
2131 PMAC_TYPE_ANS, NULL,
2132 0
2133 },
2134 { "AAPL,e407", "Alchemy",
2135 PMAC_TYPE_ALCHEMY, NULL,
2136 0
2137 },
2138 { "AAPL,e411", "Gazelle",
2139 PMAC_TYPE_GAZELLE, NULL,
2140 0
2141 },
2142 { "AAPL,Gossamer", "PowerMac G3 (Gossamer)",
2143 PMAC_TYPE_GOSSAMER, heathrow_desktop_features,
2144 0
2145 },
2146 { "AAPL,PowerMac G3", "PowerMac G3 (Silk)",
2147 PMAC_TYPE_SILK, heathrow_desktop_features,
2148 0
2149 },
2150 { "PowerMac1,1", "Blue&White G3",
2151 PMAC_TYPE_YOSEMITE, paddington_features,
2152 0
2153 },
2154 { "PowerMac1,2", "PowerMac G4 PCI Graphics",
2155 PMAC_TYPE_YIKES, paddington_features,
2156 0
2157 },
2158 { "PowerMac2,1", "iMac FireWire",
2159 PMAC_TYPE_FW_IMAC, core99_features,
2160 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
2161 },
2162 { "PowerMac2,2", "iMac FireWire",
2163 PMAC_TYPE_FW_IMAC, core99_features,
2164 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
2165 },
2166 { "PowerMac3,1", "PowerMac G4 AGP Graphics",
2167 PMAC_TYPE_SAWTOOTH, core99_features,
2168 PMAC_MB_OLD_CORE99
2169 },
2170 { "PowerMac3,2", "PowerMac G4 AGP Graphics",
2171 PMAC_TYPE_SAWTOOTH, core99_features,
2172 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
2173 },
2174 { "PowerMac3,3", "PowerMac G4 AGP Graphics",
2175 PMAC_TYPE_SAWTOOTH, core99_features,
2176 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
2177 },
2178 { "PowerMac3,4", "PowerMac G4 Silver",
2179 PMAC_TYPE_QUICKSILVER, core99_features,
2180 PMAC_MB_MAY_SLEEP
2181 },
2182 { "PowerMac3,5", "PowerMac G4 Silver",
2183 PMAC_TYPE_QUICKSILVER, core99_features,
2184 PMAC_MB_MAY_SLEEP
2185 },
2186 { "PowerMac3,6", "PowerMac G4 Windtunnel",
2187 PMAC_TYPE_WINDTUNNEL, core99_features,
2188 PMAC_MB_MAY_SLEEP,
2189 },
2190 { "PowerMac4,1", "iMac \"Flower Power\"",
2191 PMAC_TYPE_PANGEA_IMAC, pangea_features,
2192 PMAC_MB_MAY_SLEEP
2193 },
2194 { "PowerMac4,2", "Flat panel iMac",
2195 PMAC_TYPE_FLAT_PANEL_IMAC, pangea_features,
2196 PMAC_MB_CAN_SLEEP
2197 },
2198 { "PowerMac4,4", "eMac",
2199 PMAC_TYPE_EMAC, core99_features,
2200 PMAC_MB_MAY_SLEEP
2201 },
2202 { "PowerMac5,1", "PowerMac G4 Cube",
2203 PMAC_TYPE_CUBE, core99_features,
2204 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
2205 },
2206 { "PowerMac6,1", "Flat panel iMac",
2207 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2208 PMAC_MB_MAY_SLEEP,
2209 },
2210 { "PowerMac6,3", "Flat panel iMac",
2211 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2212 PMAC_MB_MAY_SLEEP,
2213 },
2214 { "PowerMac6,4", "eMac",
2215 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2216 PMAC_MB_MAY_SLEEP,
2217 },
2218 { "PowerMac10,1", "Mac mini",
2219 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2220 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER,
2221 },
2222 { "iMac,1", "iMac (first generation)",
2223 PMAC_TYPE_ORIG_IMAC, paddington_features,
2224 0
2225 },
2226
2227 /*
2228 * Xserve's
2229 */
2230
2231 { "RackMac1,1", "XServe",
2232 PMAC_TYPE_RACKMAC, rackmac_features,
2233 0,
2234 },
2235 { "RackMac1,2", "XServe rev. 2",
2236 PMAC_TYPE_RACKMAC, rackmac_features,
2237 0,
2238 },
2239
2240 /*
2241 * Laptops
2242 */
2243
2244 { "AAPL,3400/2400", "PowerBook 3400",
2245 PMAC_TYPE_HOOPER, ohare_features,
2246 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE
2247 },
2248 { "AAPL,3500", "PowerBook 3500",
2249 PMAC_TYPE_KANGA, ohare_features,
2250 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE
2251 },
2252 { "AAPL,PowerBook1998", "PowerBook Wallstreet",
2253 PMAC_TYPE_WALLSTREET, heathrow_laptop_features,
2254 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE
2255 },
2256 { "PowerBook1,1", "PowerBook 101 (Lombard)",
2257 PMAC_TYPE_101_PBOOK, paddington_features,
2258 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE
2259 },
2260 { "PowerBook2,1", "iBook (first generation)",
2261 PMAC_TYPE_ORIG_IBOOK, core99_features,
2262 PMAC_MB_CAN_SLEEP | PMAC_MB_OLD_CORE99 | PMAC_MB_MOBILE
2263 },
2264 { "PowerBook2,2", "iBook FireWire",
2265 PMAC_TYPE_FW_IBOOK, core99_features,
2266 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER |
2267 PMAC_MB_OLD_CORE99 | PMAC_MB_MOBILE
2268 },
2269 { "PowerBook3,1", "PowerBook Pismo",
2270 PMAC_TYPE_PISMO, core99_features,
2271 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER |
2272 PMAC_MB_OLD_CORE99 | PMAC_MB_MOBILE
2273 },
2274 { "PowerBook3,2", "PowerBook Titanium",
2275 PMAC_TYPE_TITANIUM, core99_features,
2276 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2277 },
2278 { "PowerBook3,3", "PowerBook Titanium II",
2279 PMAC_TYPE_TITANIUM2, core99_features,
2280 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2281 },
2282 { "PowerBook3,4", "PowerBook Titanium III",
2283 PMAC_TYPE_TITANIUM3, core99_features,
2284 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2285 },
2286 { "PowerBook3,5", "PowerBook Titanium IV",
2287 PMAC_TYPE_TITANIUM4, core99_features,
2288 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2289 },
2290 { "PowerBook4,1", "iBook 2",
2291 PMAC_TYPE_IBOOK2, pangea_features,
2292 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2293 },
2294 { "PowerBook4,2", "iBook 2",
2295 PMAC_TYPE_IBOOK2, pangea_features,
2296 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2297 },
2298 { "PowerBook4,3", "iBook 2 rev. 2",
2299 PMAC_TYPE_IBOOK2, pangea_features,
2300 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2301 },
2302 { "PowerBook5,1", "PowerBook G4 17\"",
2303 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2304 PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2305 },
2306 { "PowerBook5,2", "PowerBook G4 15\"",
2307 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2308 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2309 },
2310 { "PowerBook5,3", "PowerBook G4 17\"",
2311 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2312 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2313 },
2314 { "PowerBook5,4", "PowerBook G4 15\"",
2315 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2316 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2317 },
2318 { "PowerBook5,5", "PowerBook G4 17\"",
2319 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2320 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2321 },
2322 { "PowerBook5,6", "PowerBook G4 15\"",
2323 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2324 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2325 },
2326 { "PowerBook5,7", "PowerBook G4 17\"",
2327 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2328 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2329 },
2330 { "PowerBook5,8", "PowerBook G4 15\"",
2331 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2332 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2333 },
2334 { "PowerBook5,9", "PowerBook G4 17\"",
2335 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2336 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2337 },
2338 { "PowerBook6,1", "PowerBook G4 12\"",
2339 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2340 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2341 },
2342 { "PowerBook6,2", "PowerBook G4",
2343 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2344 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2345 },
2346 { "PowerBook6,3", "iBook G4",
2347 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2348 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2349 },
2350 { "PowerBook6,4", "PowerBook G4 12\"",
2351 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2352 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2353 },
2354 { "PowerBook6,5", "iBook G4",
2355 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2356 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2357 },
2358 { "PowerBook6,7", "iBook G4",
2359 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2360 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2361 },
2362 { "PowerBook6,8", "PowerBook G4 12\"",
2363 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features,
2364 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2365 },
2366#else /* CONFIG_POWER4 */
2367 { "PowerMac7,2", "PowerMac G5",
2368 PMAC_TYPE_POWERMAC_G5, g5_features,
2369 0,
2370 },
2371#endif /* CONFIG_POWER4 */
2372};
2373
2374/*
2375 * The toplevel feature_call callback
2376 */
2377long
2378pmac_do_feature_call(unsigned int selector, ...)
2379{
2380 struct device_node* node;
2381 long param, value;
2382 int i;
2383 feature_call func = NULL;
2384 va_list args;
2385
2386 if (pmac_mb.features)
2387 for (i=0; pmac_mb.features[i].function; i++)
2388 if (pmac_mb.features[i].selector == selector) {
2389 func = pmac_mb.features[i].function;
2390 break;
2391 }
2392 if (!func)
2393 for (i=0; any_features[i].function; i++)
2394 if (any_features[i].selector == selector) {
2395 func = any_features[i].function;
2396 break;
2397 }
2398 if (!func)
2399 return -ENODEV;
2400
2401 va_start(args, selector);
2402 node = (struct device_node*)va_arg(args, void*);
2403 param = va_arg(args, long);
2404 value = va_arg(args, long);
2405 va_end(args);
2406
2407 return func(node, param, value);
2408}
2409
2410static int __init
2411probe_motherboard(void)
2412{
2413 int i;
2414 struct macio_chip* macio = &macio_chips[0];
2415 const char* model = NULL;
2416 struct device_node *dt;
2417
2418 /* Lookup known motherboard type in device-tree. First try an
2419 * exact match on the "model" property, then try a "compatible"
2420 * match is none is found.
2421 */
2422 dt = find_devices("device-tree");
2423 if (dt != NULL)
2424 model = (const char *) get_property(dt, "model", NULL);
2425 for(i=0; model && i<(sizeof(pmac_mb_defs)/sizeof(struct pmac_mb_def)); i++) {
2426 if (strcmp(model, pmac_mb_defs[i].model_string) == 0) {
2427 pmac_mb = pmac_mb_defs[i];
2428 goto found;
2429 }
2430 }
2431 for(i=0; i<(sizeof(pmac_mb_defs)/sizeof(struct pmac_mb_def)); i++) {
2432 if (machine_is_compatible(pmac_mb_defs[i].model_string)) {
2433 pmac_mb = pmac_mb_defs[i];
2434 goto found;
2435 }
2436 }
2437
2438 /* Fallback to selection depending on mac-io chip type */
2439 switch(macio->type) {
2440#ifndef CONFIG_POWER4
2441 case macio_grand_central:
2442 pmac_mb.model_id = PMAC_TYPE_PSURGE;
2443 pmac_mb.model_name = "Unknown PowerSurge";
2444 break;
2445 case macio_ohare:
2446 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_OHARE;
2447 pmac_mb.model_name = "Unknown OHare-based";
2448 break;
2449 case macio_heathrow:
2450 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_HEATHROW;
2451 pmac_mb.model_name = "Unknown Heathrow-based";
2452 pmac_mb.features = heathrow_desktop_features;
2453 break;
2454 case macio_paddington:
2455 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_PADDINGTON;
2456 pmac_mb.model_name = "Unknown Paddington-based";
2457 pmac_mb.features = paddington_features;
2458 break;
2459 case macio_keylargo:
2460 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_CORE99;
2461 pmac_mb.model_name = "Unknown Keylargo-based";
2462 pmac_mb.features = core99_features;
2463 break;
2464 case macio_pangea:
2465 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_PANGEA;
2466 pmac_mb.model_name = "Unknown Pangea-based";
2467 pmac_mb.features = pangea_features;
2468 break;
2469 case macio_intrepid:
2470 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_INTREPID;
2471 pmac_mb.model_name = "Unknown Intrepid-based";
2472 pmac_mb.features = intrepid_features;
2473 break;
2474#else /* CONFIG_POWER4 */
2475 case macio_keylargo2:
2476 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_K2;
2477 pmac_mb.model_name = "Unknown G5";
2478 pmac_mb.features = g5_features;
2479 break;
2480#endif /* CONFIG_POWER4 */
2481 default:
2482 return -ENODEV;
2483 }
2484found:
2485#ifndef CONFIG_POWER4
2486 /* Fixup Hooper vs. Comet */
2487 if (pmac_mb.model_id == PMAC_TYPE_HOOPER) {
2488 u32 __iomem * mach_id_ptr = ioremap(0xf3000034, 4);
2489 if (!mach_id_ptr)
2490 return -ENODEV;
2491 /* Here, I used to disable the media-bay on comet. It
2492 * appears this is wrong, the floppy connector is actually
2493 * a kind of media-bay and works with the current driver.
2494 */
2495 if (__raw_readl(mach_id_ptr) & 0x20000000UL)
2496 pmac_mb.model_id = PMAC_TYPE_COMET;
2497 iounmap(mach_id_ptr);
2498 }
2499#endif /* CONFIG_POWER4 */
2500
2501#ifdef CONFIG_6xx
2502 /* Set default value of powersave_nap on machines that support it.
2503 * It appears that uninorth rev 3 has a problem with it, we don't
2504 * enable it on those. In theory, the flush-on-lock property is
2505 * supposed to be set when not supported, but I'm not very confident
2506 * that all Apple OF revs did it properly, I do it the paranoid way.
2507 */
2508 while (uninorth_base && uninorth_rev > 3) {
2509 struct device_node* np = find_path_device("/cpus");
2510 if (!np || !np->child) {
2511 printk(KERN_WARNING "Can't find CPU(s) in device tree !\n");
2512 break;
2513 }
2514 np = np->child;
2515 /* Nap mode not supported on SMP */
2516 if (np->sibling)
2517 break;
2518 /* Nap mode not supported if flush-on-lock property is present */
2519 if (get_property(np, "flush-on-lock", NULL))
2520 break;
2521 powersave_nap = 1;
2522 printk(KERN_INFO "Processor NAP mode on idle enabled.\n");
2523 break;
2524 }
2525
2526 /* On CPUs that support it (750FX), lowspeed by default during
2527 * NAP mode
2528 */
2529 powersave_lowspeed = 1;
2530#endif /* CONFIG_6xx */
2531#ifdef CONFIG_POWER4
2532 powersave_nap = 1;
2533#endif
2534 /* Check for "mobile" machine */
2535 if (model && (strncmp(model, "PowerBook", 9) == 0
2536 || strncmp(model, "iBook", 5) == 0))
2537 pmac_mb.board_flags |= PMAC_MB_MOBILE;
2538
2539
2540 printk(KERN_INFO "PowerMac motherboard: %s\n", pmac_mb.model_name);
2541 return 0;
2542}
2543
2544/* Initialize the Core99 UniNorth host bridge and memory controller
2545 */
2546static void __init
2547probe_uninorth(void)
2548{
2549 unsigned long actrl;
2550
2551 /* Locate core99 Uni-N */
2552 uninorth_node = of_find_node_by_name(NULL, "uni-n");
2553 /* Locate G5 u3 */
2554 if (uninorth_node == NULL) {
2555 uninorth_node = of_find_node_by_name(NULL, "u3");
2556 uninorth_u3 = 1;
2557 }
2558 if (uninorth_node && uninorth_node->n_addrs > 0) {
2559 unsigned long address = uninorth_node->addrs[0].address;
2560 uninorth_base = ioremap(address, 0x40000);
2561 uninorth_rev = in_be32(UN_REG(UNI_N_VERSION));
2562 if (uninorth_u3)
2563 u3_ht = ioremap(address + U3_HT_CONFIG_BASE, 0x1000);
2564 } else
2565 uninorth_node = NULL;
2566
2567 if (!uninorth_node)
2568 return;
2569
2570 printk(KERN_INFO "Found %s memory controller & host bridge, revision: %d\n",
2571 uninorth_u3 ? "U3" : "UniNorth", uninorth_rev);
2572 printk(KERN_INFO "Mapped at 0x%08lx\n", (unsigned long)uninorth_base);
2573
2574 /* Set the arbitrer QAck delay according to what Apple does
2575 */
2576 if (uninorth_rev < 0x11) {
2577 actrl = UN_IN(UNI_N_ARB_CTRL) & ~UNI_N_ARB_CTRL_QACK_DELAY_MASK;
2578 actrl |= ((uninorth_rev < 3) ? UNI_N_ARB_CTRL_QACK_DELAY105 :
2579 UNI_N_ARB_CTRL_QACK_DELAY) << UNI_N_ARB_CTRL_QACK_DELAY_SHIFT;
2580 UN_OUT(UNI_N_ARB_CTRL, actrl);
2581 }
2582
2583 /* Some more magic as done by them in recent MacOS X on UniNorth
2584 * revs 1.5 to 2.O and Pangea. Seem to toggle the UniN Maxbus/PCI
2585 * memory timeout
2586 */
2587 if ((uninorth_rev >= 0x11 && uninorth_rev <= 0x24) || uninorth_rev == 0xc0)
2588 UN_OUT(0x2160, UN_IN(0x2160) & 0x00ffffff);
2589}
2590
2591static void __init
2592probe_one_macio(const char* name, const char* compat, int type)
2593{
2594 struct device_node* node;
2595 int i;
2596 volatile u32 __iomem * base;
2597 u32* revp;
2598
2599 node = find_devices(name);
2600 if (!node || !node->n_addrs)
2601 return;
2602 if (compat)
2603 do {
2604 if (device_is_compatible(node, compat))
2605 break;
2606 node = node->next;
2607 } while (node);
2608 if (!node)
2609 return;
2610 for(i=0; i<MAX_MACIO_CHIPS; i++) {
2611 if (!macio_chips[i].of_node)
2612 break;
2613 if (macio_chips[i].of_node == node)
2614 return;
2615 }
2616 if (i >= MAX_MACIO_CHIPS) {
2617 printk(KERN_ERR "pmac_feature: Please increase MAX_MACIO_CHIPS !\n");
2618 printk(KERN_ERR "pmac_feature: %s skipped\n", node->full_name);
2619 return;
2620 }
2621 base = ioremap(node->addrs[0].address, node->addrs[0].size);
2622 if (!base) {
2623 printk(KERN_ERR "pmac_feature: Can't map mac-io chip !\n");
2624 return;
2625 }
2626 if (type == macio_keylargo) {
2627 u32* did = (u32 *)get_property(node, "device-id", NULL);
2628 if (*did == 0x00000025)
2629 type = macio_pangea;
2630 if (*did == 0x0000003e)
2631 type = macio_intrepid;
2632 }
2633 macio_chips[i].of_node = node;
2634 macio_chips[i].type = type;
2635 macio_chips[i].base = base;
2636 macio_chips[i].flags = MACIO_FLAG_SCCB_ON | MACIO_FLAG_SCCB_ON;
2637 macio_chips[i].name = macio_names[type];
2638 revp = (u32 *)get_property(node, "revision-id", NULL);
2639 if (revp)
2640 macio_chips[i].rev = *revp;
2641 printk(KERN_INFO "Found a %s mac-io controller, rev: %d, mapped at 0x%p\n",
2642 macio_names[type], macio_chips[i].rev, macio_chips[i].base);
2643}
2644
2645static int __init
2646probe_macios(void)
2647{
2648 /* Warning, ordering is important */
2649 probe_one_macio("gc", NULL, macio_grand_central);
2650 probe_one_macio("ohare", NULL, macio_ohare);
2651 probe_one_macio("pci106b,7", NULL, macio_ohareII);
2652 probe_one_macio("mac-io", "keylargo", macio_keylargo);
2653 probe_one_macio("mac-io", "paddington", macio_paddington);
2654 probe_one_macio("mac-io", "gatwick", macio_gatwick);
2655 probe_one_macio("mac-io", "heathrow", macio_heathrow);
2656 probe_one_macio("mac-io", "K2-Keylargo", macio_keylargo2);
2657
2658 /* Make sure the "main" macio chip appear first */
2659 if (macio_chips[0].type == macio_gatwick
2660 && macio_chips[1].type == macio_heathrow) {
2661 struct macio_chip temp = macio_chips[0];
2662 macio_chips[0] = macio_chips[1];
2663 macio_chips[1] = temp;
2664 }
2665 if (macio_chips[0].type == macio_ohareII
2666 && macio_chips[1].type == macio_ohare) {
2667 struct macio_chip temp = macio_chips[0];
2668 macio_chips[0] = macio_chips[1];
2669 macio_chips[1] = temp;
2670 }
2671 macio_chips[0].lbus.index = 0;
2672 macio_chips[1].lbus.index = 1;
2673
2674 return (macio_chips[0].of_node == NULL) ? -ENODEV : 0;
2675}
2676
2677static void __init
2678initial_serial_shutdown(struct device_node* np)
2679{
2680 int len;
2681 struct slot_names_prop {
2682 int count;
2683 char name[1];
2684 } *slots;
2685 char *conn;
2686 int port_type = PMAC_SCC_ASYNC;
2687 int modem = 0;
2688
2689 slots = (struct slot_names_prop *)get_property(np, "slot-names", &len);
2690 conn = get_property(np, "AAPL,connector", &len);
2691 if (conn && (strcmp(conn, "infrared") == 0))
2692 port_type = PMAC_SCC_IRDA;
2693 else if (device_is_compatible(np, "cobalt"))
2694 modem = 1;
2695 else if (slots && slots->count > 0) {
2696 if (strcmp(slots->name, "IrDA") == 0)
2697 port_type = PMAC_SCC_IRDA;
2698 else if (strcmp(slots->name, "Modem") == 0)
2699 modem = 1;
2700 }
2701 if (modem)
2702 pmac_call_feature(PMAC_FTR_MODEM_ENABLE, np, 0, 0);
2703 pmac_call_feature(PMAC_FTR_SCC_ENABLE, np, port_type, 0);
2704}
2705
2706static void __init
2707set_initial_features(void)
2708{
2709 struct device_node* np;
2710
2711 /* That hack appears to be necessary for some StarMax motherboards
2712 * but I'm not too sure it was audited for side-effects on other
2713 * ohare based machines...
2714 * Since I still have difficulties figuring the right way to
2715 * differenciate them all and since that hack was there for a long
2716 * time, I'll keep it around
2717 */
2718 if (macio_chips[0].type == macio_ohare && !find_devices("via-pmu")) {
2719 struct macio_chip* macio = &macio_chips[0];
2720 MACIO_OUT32(OHARE_FCR, STARMAX_FEATURES);
2721 } else if (macio_chips[0].type == macio_ohare) {
2722 struct macio_chip* macio = &macio_chips[0];
2723 MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE);
2724 } else if (macio_chips[1].type == macio_ohare) {
2725 struct macio_chip* macio = &macio_chips[1];
2726 MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE);
2727 }
2728
2729#ifdef CONFIG_POWER4
2730 if (macio_chips[0].type == macio_keylargo2) {
2731#ifndef CONFIG_SMP
2732 /* On SMP machines running UP, we have the second CPU eating
2733 * bus cycles. We need to take it off the bus. This is done
2734 * from pmac_smp for SMP kernels running on one CPU
2735 */
2736 np = of_find_node_by_type(NULL, "cpu");
2737 if (np != NULL)
2738 np = of_find_node_by_type(np, "cpu");
2739 if (np != NULL) {
2740 g5_phy_disable_cpu1();
2741 of_node_put(np);
2742 }
2743#endif /* CONFIG_SMP */
2744 /* Enable GMAC for now for PCI probing. It will be disabled
2745 * later on after PCI probe
2746 */
2747 np = of_find_node_by_name(NULL, "ethernet");
2748 while(np) {
2749 if (device_is_compatible(np, "K2-GMAC"))
2750 g5_gmac_enable(np, 0, 1);
2751 np = of_find_node_by_name(np, "ethernet");
2752 }
2753
2754 /* Enable FW before PCI probe. Will be disabled later on
2755 * Note: We should have a batter way to check that we are
2756 * dealing with uninorth internal cell and not a PCI cell
2757 * on the external PCI. The code below works though.
2758 */
2759 np = of_find_node_by_name(NULL, "firewire");
2760 while(np) {
2761 if (device_is_compatible(np, "pci106b,5811")) {
2762 macio_chips[0].flags |= MACIO_FLAG_FW_SUPPORTED;
2763 g5_fw_enable(np, 0, 1);
2764 }
2765 np = of_find_node_by_name(np, "firewire");
2766 }
2767 }
2768#else /* CONFIG_POWER4 */
2769
2770 if (macio_chips[0].type == macio_keylargo ||
2771 macio_chips[0].type == macio_pangea ||
2772 macio_chips[0].type == macio_intrepid) {
2773 /* Enable GMAC for now for PCI probing. It will be disabled
2774 * later on after PCI probe
2775 */
2776 np = of_find_node_by_name(NULL, "ethernet");
2777 while(np) {
2778 if (np->parent
2779 && device_is_compatible(np->parent, "uni-north")
2780 && device_is_compatible(np, "gmac"))
2781 core99_gmac_enable(np, 0, 1);
2782 np = of_find_node_by_name(np, "ethernet");
2783 }
2784
2785 /* Enable FW before PCI probe. Will be disabled later on
2786 * Note: We should have a batter way to check that we are
2787 * dealing with uninorth internal cell and not a PCI cell
2788 * on the external PCI. The code below works though.
2789 */
2790 np = of_find_node_by_name(NULL, "firewire");
2791 while(np) {
2792 if (np->parent
2793 && device_is_compatible(np->parent, "uni-north")
2794 && (device_is_compatible(np, "pci106b,18") ||
2795 device_is_compatible(np, "pci106b,30") ||
2796 device_is_compatible(np, "pci11c1,5811"))) {
2797 macio_chips[0].flags |= MACIO_FLAG_FW_SUPPORTED;
2798 core99_firewire_enable(np, 0, 1);
2799 }
2800 np = of_find_node_by_name(np, "firewire");
2801 }
2802
2803 /* Enable ATA-100 before PCI probe. */
2804 np = of_find_node_by_name(NULL, "ata-6");
2805 while(np) {
2806 if (np->parent
2807 && device_is_compatible(np->parent, "uni-north")
2808 && device_is_compatible(np, "kauai-ata")) {
2809 core99_ata100_enable(np, 1);
2810 }
2811 np = of_find_node_by_name(np, "ata-6");
2812 }
2813
2814 /* Switch airport off */
2815 np = find_devices("radio");
2816 while(np) {
2817 if (np && np->parent == macio_chips[0].of_node) {
2818 macio_chips[0].flags |= MACIO_FLAG_AIRPORT_ON;
2819 core99_airport_enable(np, 0, 0);
2820 }
2821 np = np->next;
2822 }
2823 }
2824
2825 /* On all machines that support sound PM, switch sound off */
2826 if (macio_chips[0].of_node)
2827 pmac_do_feature_call(PMAC_FTR_SOUND_CHIP_ENABLE,
2828 macio_chips[0].of_node, 0, 0);
2829
2830 /* While on some desktop G3s, we turn it back on */
2831 if (macio_chips[0].of_node && macio_chips[0].type == macio_heathrow
2832 && (pmac_mb.model_id == PMAC_TYPE_GOSSAMER ||
2833 pmac_mb.model_id == PMAC_TYPE_SILK)) {
2834 struct macio_chip* macio = &macio_chips[0];
2835 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE);
2836 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_POWER_N);
2837 }
2838
2839 /* Some machine models need the clock chip to be properly setup for
2840 * clock spreading now. This should be a platform function but we
2841 * don't do these at the moment
2842 */
2843 pmac_tweak_clock_spreading(1);
2844
2845#endif /* CONFIG_POWER4 */
2846
2847 /* On all machines, switch modem & serial ports off */
2848 np = find_devices("ch-a");
2849 while(np) {
2850 initial_serial_shutdown(np);
2851 np = np->next;
2852 }
2853 np = find_devices("ch-b");
2854 while(np) {
2855 initial_serial_shutdown(np);
2856 np = np->next;
2857 }
2858}
2859
2860void __init
2861pmac_feature_init(void)
2862{
2863 /* Detect the UniNorth memory controller */
2864 probe_uninorth();
2865
2866 /* Probe mac-io controllers */
2867 if (probe_macios()) {
2868 printk(KERN_WARNING "No mac-io chip found\n");
2869 return;
2870 }
2871
2872 /* Setup low-level i2c stuffs */
2873 pmac_init_low_i2c();
2874
2875 /* Probe machine type */
2876 if (probe_motherboard())
2877 printk(KERN_WARNING "Unknown PowerMac !\n");
2878
2879 /* Set some initial features (turn off some chips that will
2880 * be later turned on)
2881 */
2882 set_initial_features();
2883}
2884
2885int __init
2886pmac_feature_late_init(void)
2887{
2888 struct device_node* np;
2889
2890 /* Request some resources late */
2891 if (uninorth_node)
2892 request_OF_resource(uninorth_node, 0, NULL);
2893 np = find_devices("hammerhead");
2894 if (np)
2895 request_OF_resource(np, 0, NULL);
2896 np = find_devices("interrupt-controller");
2897 if (np)
2898 request_OF_resource(np, 0, NULL);
2899 return 0;
2900}
2901
2902device_initcall(pmac_feature_late_init);
2903
2904#ifdef CONFIG_POWER4
2905
2906static void dump_HT_speeds(char *name, u32 cfg, u32 frq)
2907{
2908 int freqs[16] = { 200,300,400,500,600,800,1000,0,0,0,0,0,0,0,0,0 };
2909 int bits[8] = { 8,16,0,32,2,4,0,0 };
2910 int freq = (frq >> 8) & 0xf;
2911
2912 if (freqs[freq] == 0)
2913 printk("%s: Unknown HT link frequency %x\n", name, freq);
2914 else
2915 printk("%s: %d MHz on main link, (%d in / %d out) bits width\n",
2916 name, freqs[freq],
2917 bits[(cfg >> 28) & 0x7], bits[(cfg >> 24) & 0x7]);
2918}
2919
2920void __init pmac_check_ht_link(void)
2921{
2922 u32 ufreq, freq, ucfg, cfg;
2923 struct device_node *pcix_node;
2924 u8 px_bus, px_devfn;
2925 struct pci_controller *px_hose;
2926
2927 (void)in_be32(u3_ht + U3_HT_LINK_COMMAND);
2928 ucfg = cfg = in_be32(u3_ht + U3_HT_LINK_CONFIG);
2929 ufreq = freq = in_be32(u3_ht + U3_HT_LINK_FREQ);
2930 dump_HT_speeds("U3 HyperTransport", cfg, freq);
2931
2932 pcix_node = of_find_compatible_node(NULL, "pci", "pci-x");
2933 if (pcix_node == NULL) {
2934 printk("No PCI-X bridge found\n");
2935 return;
2936 }
2937 if (pci_device_from_OF_node(pcix_node, &px_bus, &px_devfn) != 0) {
2938 printk("PCI-X bridge found but not matched to pci\n");
2939 return;
2940 }
2941 px_hose = pci_find_hose_for_OF_device(pcix_node);
2942 if (px_hose == NULL) {
2943 printk("PCI-X bridge found but not matched to host\n");
2944 return;
2945 }
2946 early_read_config_dword(px_hose, px_bus, px_devfn, 0xc4, &cfg);
2947 early_read_config_dword(px_hose, px_bus, px_devfn, 0xcc, &freq);
2948 dump_HT_speeds("PCI-X HT Uplink", cfg, freq);
2949 early_read_config_dword(px_hose, px_bus, px_devfn, 0xc8, &cfg);
2950 early_read_config_dword(px_hose, px_bus, px_devfn, 0xd0, &freq);
2951 dump_HT_speeds("PCI-X HT Downlink", cfg, freq);
2952}
2953
2954#endif /* CONFIG_POWER4 */
2955
2956/*
2957 * Early video resume hook
2958 */
2959
2960static void (*pmac_early_vresume_proc)(void *data);
2961static void *pmac_early_vresume_data;
2962
2963void pmac_set_early_video_resume(void (*proc)(void *data), void *data)
2964{
2965 if (_machine != _MACH_Pmac)
2966 return;
2967 preempt_disable();
2968 pmac_early_vresume_proc = proc;
2969 pmac_early_vresume_data = data;
2970 preempt_enable();
2971}
2972EXPORT_SYMBOL(pmac_set_early_video_resume);
2973
2974void pmac_call_early_video_resume(void)
2975{
2976 if (pmac_early_vresume_proc)
2977 pmac_early_vresume_proc(pmac_early_vresume_data);
2978}
2979
2980/*
2981 * AGP related suspend/resume code
2982 */
2983
2984static struct pci_dev *pmac_agp_bridge;
2985static int (*pmac_agp_suspend)(struct pci_dev *bridge);
2986static int (*pmac_agp_resume)(struct pci_dev *bridge);
2987
2988void pmac_register_agp_pm(struct pci_dev *bridge,
2989 int (*suspend)(struct pci_dev *bridge),
2990 int (*resume)(struct pci_dev *bridge))
2991{
2992 if (suspend || resume) {
2993 pmac_agp_bridge = bridge;
2994 pmac_agp_suspend = suspend;
2995 pmac_agp_resume = resume;
2996 return;
2997 }
2998 if (bridge != pmac_agp_bridge)
2999 return;
3000 pmac_agp_suspend = pmac_agp_resume = NULL;
3001 return;
3002}
3003EXPORT_SYMBOL(pmac_register_agp_pm);
3004
3005void pmac_suspend_agp_for_card(struct pci_dev *dev)
3006{
3007 if (pmac_agp_bridge == NULL || pmac_agp_suspend == NULL)
3008 return;
3009 if (pmac_agp_bridge->bus != dev->bus)
3010 return;
3011 pmac_agp_suspend(pmac_agp_bridge);
3012}
3013EXPORT_SYMBOL(pmac_suspend_agp_for_card);
3014
3015void pmac_resume_agp_for_card(struct pci_dev *dev)
3016{
3017 if (pmac_agp_bridge == NULL || pmac_agp_resume == NULL)
3018 return;
3019 if (pmac_agp_bridge->bus != dev->bus)
3020 return;
3021 pmac_agp_resume(pmac_agp_bridge);
3022}
3023EXPORT_SYMBOL(pmac_resume_agp_for_card);
diff --git a/arch/ppc/platforms/pmac_low_i2c.c b/arch/ppc/platforms/pmac_low_i2c.c
deleted file mode 100644
index 08583fce169..00000000000
--- a/arch/ppc/platforms/pmac_low_i2c.c
+++ /dev/null
@@ -1,511 +0,0 @@
1/*
2 * arch/ppc/platforms/pmac_low_i2c.c
3 *
4 * Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * This file contains some low-level i2c access routines that
12 * need to be used by various bits of the PowerMac platform code
13 * at times where the real asynchronous & interrupt driven driver
14 * cannot be used. The API borrows some semantics from the darwin
15 * driver in order to ease the implementation of the platform
16 * properties parser
17 */
18
19#include <linux/config.h>
20#include <linux/types.h>
21#include <linux/delay.h>
22#include <linux/sched.h>
23#include <linux/init.h>
24#include <linux/module.h>
25#include <linux/adb.h>
26#include <linux/pmu.h>
27#include <asm/keylargo.h>
28#include <asm/uninorth.h>
29#include <asm/io.h>
30#include <asm/prom.h>
31#include <asm/machdep.h>
32#include <asm/pmac_low_i2c.h>
33
34#define MAX_LOW_I2C_HOST 4
35
36#if 1
37#define DBG(x...) do {\
38 printk(KERN_DEBUG "KW:" x); \
39 } while(0)
40#else
41#define DBGG(x...)
42#endif
43
44struct low_i2c_host;
45
46typedef int (*low_i2c_func_t)(struct low_i2c_host *host, u8 addr, u8 sub, u8 *data, int len);
47
48struct low_i2c_host
49{
50 struct device_node *np; /* OF device node */
51 struct semaphore mutex; /* Access mutex for use by i2c-keywest */
52 low_i2c_func_t func; /* Access function */
53 int is_open : 1; /* Poor man's access control */
54 int mode; /* Current mode */
55 int channel; /* Current channel */
56 int num_channels; /* Number of channels */
57 void __iomem * base; /* For keywest-i2c, base address */
58 int bsteps; /* And register stepping */
59 int speed; /* And speed */
60};
61
62static struct low_i2c_host low_i2c_hosts[MAX_LOW_I2C_HOST];
63
64/* No locking is necessary on allocation, we are running way before
65 * anything can race with us
66 */
67static struct low_i2c_host *find_low_i2c_host(struct device_node *np)
68{
69 int i;
70
71 for (i = 0; i < MAX_LOW_I2C_HOST; i++)
72 if (low_i2c_hosts[i].np == np)
73 return &low_i2c_hosts[i];
74 return NULL;
75}
76
77/*
78 *
79 * i2c-keywest implementation (UniNorth, U2, U3, Keylargo's)
80 *
81 */
82
83/*
84 * Keywest i2c definitions borrowed from drivers/i2c/i2c-keywest.h,
85 * should be moved somewhere in include/asm-ppc/
86 */
87/* Register indices */
88typedef enum {
89 reg_mode = 0,
90 reg_control,
91 reg_status,
92 reg_isr,
93 reg_ier,
94 reg_addr,
95 reg_subaddr,
96 reg_data
97} reg_t;
98
99
100/* Mode register */
101#define KW_I2C_MODE_100KHZ 0x00
102#define KW_I2C_MODE_50KHZ 0x01
103#define KW_I2C_MODE_25KHZ 0x02
104#define KW_I2C_MODE_DUMB 0x00
105#define KW_I2C_MODE_STANDARD 0x04
106#define KW_I2C_MODE_STANDARDSUB 0x08
107#define KW_I2C_MODE_COMBINED 0x0C
108#define KW_I2C_MODE_MODE_MASK 0x0C
109#define KW_I2C_MODE_CHAN_MASK 0xF0
110
111/* Control register */
112#define KW_I2C_CTL_AAK 0x01
113#define KW_I2C_CTL_XADDR 0x02
114#define KW_I2C_CTL_STOP 0x04
115#define KW_I2C_CTL_START 0x08
116
117/* Status register */
118#define KW_I2C_STAT_BUSY 0x01
119#define KW_I2C_STAT_LAST_AAK 0x02
120#define KW_I2C_STAT_LAST_RW 0x04
121#define KW_I2C_STAT_SDA 0x08
122#define KW_I2C_STAT_SCL 0x10
123
124/* IER & ISR registers */
125#define KW_I2C_IRQ_DATA 0x01
126#define KW_I2C_IRQ_ADDR 0x02
127#define KW_I2C_IRQ_STOP 0x04
128#define KW_I2C_IRQ_START 0x08
129#define KW_I2C_IRQ_MASK 0x0F
130
131/* State machine states */
132enum {
133 state_idle,
134 state_addr,
135 state_read,
136 state_write,
137 state_stop,
138 state_dead
139};
140
141#define WRONG_STATE(name) do {\
142 printk(KERN_DEBUG "KW: wrong state. Got %s, state: %s (isr: %02x)\n", \
143 name, __kw_state_names[state], isr); \
144 } while(0)
145
146static const char *__kw_state_names[] = {
147 "state_idle",
148 "state_addr",
149 "state_read",
150 "state_write",
151 "state_stop",
152 "state_dead"
153};
154
155static inline u8 __kw_read_reg(struct low_i2c_host *host, reg_t reg)
156{
157 return in_8(host->base + (((unsigned)reg) << host->bsteps));
158}
159
160static inline void __kw_write_reg(struct low_i2c_host *host, reg_t reg, u8 val)
161{
162 out_8(host->base + (((unsigned)reg) << host->bsteps), val);
163 (void)__kw_read_reg(host, reg_subaddr);
164}
165
166#define kw_write_reg(reg, val) __kw_write_reg(host, reg, val)
167#define kw_read_reg(reg) __kw_read_reg(host, reg)
168
169
170/* Don't schedule, the g5 fan controller is too
171 * timing sensitive
172 */
173static u8 kw_wait_interrupt(struct low_i2c_host* host)
174{
175 int i;
176 u8 isr;
177
178 for (i = 0; i < 200000; i++) {
179 isr = kw_read_reg(reg_isr) & KW_I2C_IRQ_MASK;
180 if (isr != 0)
181 return isr;
182 udelay(1);
183 }
184 return isr;
185}
186
187static int kw_handle_interrupt(struct low_i2c_host *host, int state, int rw, int *rc, u8 **data, int *len, u8 isr)
188{
189 u8 ack;
190
191 if (isr == 0) {
192 if (state != state_stop) {
193 DBG("KW: Timeout !\n");
194 *rc = -EIO;
195 goto stop;
196 }
197 if (state == state_stop) {
198 ack = kw_read_reg(reg_status);
199 if (!(ack & KW_I2C_STAT_BUSY)) {
200 state = state_idle;
201 kw_write_reg(reg_ier, 0x00);
202 }
203 }
204 return state;
205 }
206
207 if (isr & KW_I2C_IRQ_ADDR) {
208 ack = kw_read_reg(reg_status);
209 if (state != state_addr) {
210 kw_write_reg(reg_isr, KW_I2C_IRQ_ADDR);
211 WRONG_STATE("KW_I2C_IRQ_ADDR");
212 *rc = -EIO;
213 goto stop;
214 }
215 if ((ack & KW_I2C_STAT_LAST_AAK) == 0) {
216 *rc = -ENODEV;
217 DBG("KW: NAK on address\n");
218 return state_stop;
219 } else {
220 if (rw) {
221 state = state_read;
222 if (*len > 1)
223 kw_write_reg(reg_control, KW_I2C_CTL_AAK);
224 } else {
225 state = state_write;
226 kw_write_reg(reg_data, **data);
227 (*data)++; (*len)--;
228 }
229 }
230 kw_write_reg(reg_isr, KW_I2C_IRQ_ADDR);
231 }
232
233 if (isr & KW_I2C_IRQ_DATA) {
234 if (state == state_read) {
235 **data = kw_read_reg(reg_data);
236 (*data)++; (*len)--;
237 kw_write_reg(reg_isr, KW_I2C_IRQ_DATA);
238 if ((*len) == 0)
239 state = state_stop;
240 else if ((*len) == 1)
241 kw_write_reg(reg_control, 0);
242 } else if (state == state_write) {
243 ack = kw_read_reg(reg_status);
244 if ((ack & KW_I2C_STAT_LAST_AAK) == 0) {
245 DBG("KW: nack on data write\n");
246 *rc = -EIO;
247 goto stop;
248 } else if (*len) {
249 kw_write_reg(reg_data, **data);
250 (*data)++; (*len)--;
251 } else {
252 kw_write_reg(reg_control, KW_I2C_CTL_STOP);
253 state = state_stop;
254 *rc = 0;
255 }
256 kw_write_reg(reg_isr, KW_I2C_IRQ_DATA);
257 } else {
258 kw_write_reg(reg_isr, KW_I2C_IRQ_DATA);
259 WRONG_STATE("KW_I2C_IRQ_DATA");
260 if (state != state_stop) {
261 *rc = -EIO;
262 goto stop;
263 }
264 }
265 }
266
267 if (isr & KW_I2C_IRQ_STOP) {
268 kw_write_reg(reg_isr, KW_I2C_IRQ_STOP);
269 if (state != state_stop) {
270 WRONG_STATE("KW_I2C_IRQ_STOP");
271 *rc = -EIO;
272 }
273 return state_idle;
274 }
275
276 if (isr & KW_I2C_IRQ_START)
277 kw_write_reg(reg_isr, KW_I2C_IRQ_START);
278
279 return state;
280
281 stop:
282 kw_write_reg(reg_control, KW_I2C_CTL_STOP);
283 return state_stop;
284}
285
286static int keywest_low_i2c_func(struct low_i2c_host *host, u8 addr, u8 subaddr, u8 *data, int len)
287{
288 u8 mode_reg = host->speed;
289 int state = state_addr;
290 int rc = 0;
291
292 /* Setup mode & subaddress if any */
293 switch(host->mode) {
294 case pmac_low_i2c_mode_dumb:
295 printk(KERN_ERR "low_i2c: Dumb mode not supported !\n");
296 return -EINVAL;
297 case pmac_low_i2c_mode_std:
298 mode_reg |= KW_I2C_MODE_STANDARD;
299 break;
300 case pmac_low_i2c_mode_stdsub:
301 mode_reg |= KW_I2C_MODE_STANDARDSUB;
302 kw_write_reg(reg_subaddr, subaddr);
303 break;
304 case pmac_low_i2c_mode_combined:
305 mode_reg |= KW_I2C_MODE_COMBINED;
306 kw_write_reg(reg_subaddr, subaddr);
307 break;
308 }
309
310 /* Setup channel & clear pending irqs */
311 kw_write_reg(reg_isr, kw_read_reg(reg_isr));
312 kw_write_reg(reg_mode, mode_reg | (host->channel << 4));
313 kw_write_reg(reg_status, 0);
314
315 /* Set up address and r/w bit */
316 kw_write_reg(reg_addr, addr);
317
318 /* Start sending address & disable interrupt*/
319 kw_write_reg(reg_ier, 0 /*KW_I2C_IRQ_MASK*/);
320 kw_write_reg(reg_control, KW_I2C_CTL_XADDR);
321
322 /* State machine, to turn into an interrupt handler */
323 while(state != state_idle) {
324 u8 isr = kw_wait_interrupt(host);
325 state = kw_handle_interrupt(host, state, addr & 1, &rc, &data, &len, isr);
326 }
327
328 return rc;
329}
330
331static void keywest_low_i2c_add(struct device_node *np)
332{
333 struct low_i2c_host *host = find_low_i2c_host(NULL);
334 unsigned long *psteps, *prate, steps, aoffset = 0;
335 struct device_node *parent;
336
337 if (host == NULL) {
338 printk(KERN_ERR "low_i2c: Can't allocate host for %s\n",
339 np->full_name);
340 return;
341 }
342 memset(host, 0, sizeof(*host));
343
344 init_MUTEX(&host->mutex);
345 host->np = of_node_get(np);
346 psteps = (unsigned long *)get_property(np, "AAPL,address-step", NULL);
347 steps = psteps ? (*psteps) : 0x10;
348 for (host->bsteps = 0; (steps & 0x01) == 0; host->bsteps++)
349 steps >>= 1;
350 parent = of_get_parent(np);
351 host->num_channels = 1;
352 if (parent && parent->name[0] == 'u') {
353 host->num_channels = 2;
354 aoffset = 3;
355 }
356 /* Select interface rate */
357 host->speed = KW_I2C_MODE_100KHZ;
358 prate = (unsigned long *)get_property(np, "AAPL,i2c-rate", NULL);
359 if (prate) switch(*prate) {
360 case 100:
361 host->speed = KW_I2C_MODE_100KHZ;
362 break;
363 case 50:
364 host->speed = KW_I2C_MODE_50KHZ;
365 break;
366 case 25:
367 host->speed = KW_I2C_MODE_25KHZ;
368 break;
369 }
370 host->mode = pmac_low_i2c_mode_std;
371 host->base = ioremap(np->addrs[0].address + aoffset,
372 np->addrs[0].size);
373 host->func = keywest_low_i2c_func;
374}
375
376/*
377 *
378 * PMU implementation
379 *
380 */
381
382
383#ifdef CONFIG_ADB_PMU
384
385static int pmu_low_i2c_func(struct low_i2c_host *host, u8 addr, u8 sub, u8 *data, int len)
386{
387 // TODO
388 return -ENODEV;
389}
390
391static void pmu_low_i2c_add(struct device_node *np)
392{
393 struct low_i2c_host *host = find_low_i2c_host(NULL);
394
395 if (host == NULL) {
396 printk(KERN_ERR "low_i2c: Can't allocate host for %s\n",
397 np->full_name);
398 return;
399 }
400 memset(host, 0, sizeof(*host));
401
402 init_MUTEX(&host->mutex);
403 host->np = of_node_get(np);
404 host->num_channels = 3;
405 host->mode = pmac_low_i2c_mode_std;
406 host->func = pmu_low_i2c_func;
407}
408
409#endif /* CONFIG_ADB_PMU */
410
411void __init pmac_init_low_i2c(void)
412{
413 struct device_node *np;
414
415 /* Probe keywest-i2c busses */
416 np = of_find_compatible_node(NULL, "i2c", "keywest-i2c");
417 while(np) {
418 keywest_low_i2c_add(np);
419 np = of_find_compatible_node(np, "i2c", "keywest-i2c");
420 }
421
422#ifdef CONFIG_ADB_PMU
423 /* Probe PMU busses */
424 np = of_find_node_by_name(NULL, "via-pmu");
425 if (np)
426 pmu_low_i2c_add(np);
427#endif /* CONFIG_ADB_PMU */
428
429 /* TODO: Add CUDA support as well */
430}
431
432int pmac_low_i2c_lock(struct device_node *np)
433{
434 struct low_i2c_host *host = find_low_i2c_host(np);
435
436 if (!host)
437 return -ENODEV;
438 down(&host->mutex);
439 return 0;
440}
441EXPORT_SYMBOL(pmac_low_i2c_lock);
442
443int pmac_low_i2c_unlock(struct device_node *np)
444{
445 struct low_i2c_host *host = find_low_i2c_host(np);
446
447 if (!host)
448 return -ENODEV;
449 up(&host->mutex);
450 return 0;
451}
452EXPORT_SYMBOL(pmac_low_i2c_unlock);
453
454
455int pmac_low_i2c_open(struct device_node *np, int channel)
456{
457 struct low_i2c_host *host = find_low_i2c_host(np);
458
459 if (!host)
460 return -ENODEV;
461
462 if (channel >= host->num_channels)
463 return -EINVAL;
464
465 down(&host->mutex);
466 host->is_open = 1;
467 host->channel = channel;
468
469 return 0;
470}
471EXPORT_SYMBOL(pmac_low_i2c_open);
472
473int pmac_low_i2c_close(struct device_node *np)
474{
475 struct low_i2c_host *host = find_low_i2c_host(np);
476
477 if (!host)
478 return -ENODEV;
479
480 host->is_open = 0;
481 up(&host->mutex);
482
483 return 0;
484}
485EXPORT_SYMBOL(pmac_low_i2c_close);
486
487int pmac_low_i2c_setmode(struct device_node *np, int mode)
488{
489 struct low_i2c_host *host = find_low_i2c_host(np);
490
491 if (!host)
492 return -ENODEV;
493 WARN_ON(!host->is_open);
494 host->mode = mode;
495
496 return 0;
497}
498EXPORT_SYMBOL(pmac_low_i2c_setmode);
499
500int pmac_low_i2c_xfer(struct device_node *np, u8 addrdir, u8 subaddr, u8 *data, int len)
501{
502 struct low_i2c_host *host = find_low_i2c_host(np);
503
504 if (!host)
505 return -ENODEV;
506 WARN_ON(!host->is_open);
507
508 return host->func(host, addrdir, subaddr, data, len);
509}
510EXPORT_SYMBOL(pmac_low_i2c_xfer);
511
diff --git a/arch/ppc/platforms/pmac_nvram.c b/arch/ppc/platforms/pmac_nvram.c
deleted file mode 100644
index 8c9b008c722..00000000000
--- a/arch/ppc/platforms/pmac_nvram.c
+++ /dev/null
@@ -1,584 +0,0 @@
1/*
2 * arch/ppc/platforms/pmac_nvram.c
3 *
4 * Copyright (C) 2002 Benjamin Herrenschmidt (benh@kernel.crashing.org)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * Todo: - add support for the OF persistent properties
12 */
13#include <linux/config.h>
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/stddef.h>
17#include <linux/string.h>
18#include <linux/nvram.h>
19#include <linux/init.h>
20#include <linux/slab.h>
21#include <linux/delay.h>
22#include <linux/errno.h>
23#include <linux/adb.h>
24#include <linux/pmu.h>
25#include <linux/bootmem.h>
26#include <linux/completion.h>
27#include <linux/spinlock.h>
28#include <asm/sections.h>
29#include <asm/io.h>
30#include <asm/system.h>
31#include <asm/prom.h>
32#include <asm/machdep.h>
33#include <asm/nvram.h>
34
35#define DEBUG
36
37#ifdef DEBUG
38#define DBG(x...) printk(x)
39#else
40#define DBG(x...)
41#endif
42
43#define NVRAM_SIZE 0x2000 /* 8kB of non-volatile RAM */
44
45#define CORE99_SIGNATURE 0x5a
46#define CORE99_ADLER_START 0x14
47
48/* On Core99, nvram is either a sharp, a micron or an AMD flash */
49#define SM_FLASH_STATUS_DONE 0x80
50#define SM_FLASH_STATUS_ERR 0x38
51#define SM_FLASH_CMD_ERASE_CONFIRM 0xd0
52#define SM_FLASH_CMD_ERASE_SETUP 0x20
53#define SM_FLASH_CMD_RESET 0xff
54#define SM_FLASH_CMD_WRITE_SETUP 0x40
55#define SM_FLASH_CMD_CLEAR_STATUS 0x50
56#define SM_FLASH_CMD_READ_STATUS 0x70
57
58/* CHRP NVRAM header */
59struct chrp_header {
60 u8 signature;
61 u8 cksum;
62 u16 len;
63 char name[12];
64 u8 data[0];
65};
66
67struct core99_header {
68 struct chrp_header hdr;
69 u32 adler;
70 u32 generation;
71 u32 reserved[2];
72};
73
74/*
75 * Read and write the non-volatile RAM on PowerMacs and CHRP machines.
76 */
77static int nvram_naddrs;
78static volatile unsigned char *nvram_addr;
79static volatile unsigned char *nvram_data;
80static int nvram_mult, is_core_99;
81static int core99_bank = 0;
82static int nvram_partitions[3];
83static DEFINE_SPINLOCK(nv_lock);
84
85extern int pmac_newworld;
86extern int system_running;
87
88static int (*core99_write_bank)(int bank, u8* datas);
89static int (*core99_erase_bank)(int bank);
90
91static char *nvram_image;
92
93
94static unsigned char core99_nvram_read_byte(int addr)
95{
96 if (nvram_image == NULL)
97 return 0xff;
98 return nvram_image[addr];
99}
100
101static void core99_nvram_write_byte(int addr, unsigned char val)
102{
103 if (nvram_image == NULL)
104 return;
105 nvram_image[addr] = val;
106}
107
108
109static unsigned char direct_nvram_read_byte(int addr)
110{
111 return in_8(&nvram_data[(addr & (NVRAM_SIZE - 1)) * nvram_mult]);
112}
113
114static void direct_nvram_write_byte(int addr, unsigned char val)
115{
116 out_8(&nvram_data[(addr & (NVRAM_SIZE - 1)) * nvram_mult], val);
117}
118
119
120static unsigned char indirect_nvram_read_byte(int addr)
121{
122 unsigned char val;
123 unsigned long flags;
124
125 spin_lock_irqsave(&nv_lock, flags);
126 out_8(nvram_addr, addr >> 5);
127 val = in_8(&nvram_data[(addr & 0x1f) << 4]);
128 spin_unlock_irqrestore(&nv_lock, flags);
129
130 return val;
131}
132
133static void indirect_nvram_write_byte(int addr, unsigned char val)
134{
135 unsigned long flags;
136
137 spin_lock_irqsave(&nv_lock, flags);
138 out_8(nvram_addr, addr >> 5);
139 out_8(&nvram_data[(addr & 0x1f) << 4], val);
140 spin_unlock_irqrestore(&nv_lock, flags);
141}
142
143
144#ifdef CONFIG_ADB_PMU
145
146static void pmu_nvram_complete(struct adb_request *req)
147{
148 if (req->arg)
149 complete((struct completion *)req->arg);
150}
151
152static unsigned char pmu_nvram_read_byte(int addr)
153{
154 struct adb_request req;
155 DECLARE_COMPLETION(req_complete);
156
157 req.arg = system_state == SYSTEM_RUNNING ? &req_complete : NULL;
158 if (pmu_request(&req, pmu_nvram_complete, 3, PMU_READ_NVRAM,
159 (addr >> 8) & 0xff, addr & 0xff))
160 return 0xff;
161 if (system_state == SYSTEM_RUNNING)
162 wait_for_completion(&req_complete);
163 while (!req.complete)
164 pmu_poll();
165 return req.reply[0];
166}
167
168static void pmu_nvram_write_byte(int addr, unsigned char val)
169{
170 struct adb_request req;
171 DECLARE_COMPLETION(req_complete);
172
173 req.arg = system_state == SYSTEM_RUNNING ? &req_complete : NULL;
174 if (pmu_request(&req, pmu_nvram_complete, 4, PMU_WRITE_NVRAM,
175 (addr >> 8) & 0xff, addr & 0xff, val))
176 return;
177 if (system_state == SYSTEM_RUNNING)
178 wait_for_completion(&req_complete);
179 while (!req.complete)
180 pmu_poll();
181}
182
183#endif /* CONFIG_ADB_PMU */
184
185
186static u8 chrp_checksum(struct chrp_header* hdr)
187{
188 u8 *ptr;
189 u16 sum = hdr->signature;
190 for (ptr = (u8 *)&hdr->len; ptr < hdr->data; ptr++)
191 sum += *ptr;
192 while (sum > 0xFF)
193 sum = (sum & 0xFF) + (sum>>8);
194 return sum;
195}
196
197static u32 core99_calc_adler(u8 *buffer)
198{
199 int cnt;
200 u32 low, high;
201
202 buffer += CORE99_ADLER_START;
203 low = 1;
204 high = 0;
205 for (cnt=0; cnt<(NVRAM_SIZE-CORE99_ADLER_START); cnt++) {
206 if ((cnt % 5000) == 0) {
207 high %= 65521UL;
208 high %= 65521UL;
209 }
210 low += buffer[cnt];
211 high += low;
212 }
213 low %= 65521UL;
214 high %= 65521UL;
215
216 return (high << 16) | low;
217}
218
219static u32 core99_check(u8* datas)
220{
221 struct core99_header* hdr99 = (struct core99_header*)datas;
222
223 if (hdr99->hdr.signature != CORE99_SIGNATURE) {
224 DBG("Invalid signature\n");
225 return 0;
226 }
227 if (hdr99->hdr.cksum != chrp_checksum(&hdr99->hdr)) {
228 DBG("Invalid checksum\n");
229 return 0;
230 }
231 if (hdr99->adler != core99_calc_adler(datas)) {
232 DBG("Invalid adler\n");
233 return 0;
234 }
235 return hdr99->generation;
236}
237
238static int sm_erase_bank(int bank)
239{
240 int stat, i;
241 unsigned long timeout;
242
243 u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;
244
245 DBG("nvram: Sharp/Micron Erasing bank %d...\n", bank);
246
247 out_8(base, SM_FLASH_CMD_ERASE_SETUP);
248 out_8(base, SM_FLASH_CMD_ERASE_CONFIRM);
249 timeout = 0;
250 do {
251 if (++timeout > 1000000) {
252 printk(KERN_ERR "nvram: Sharp/Miron flash erase timeout !\n");
253 break;
254 }
255 out_8(base, SM_FLASH_CMD_READ_STATUS);
256 stat = in_8(base);
257 } while (!(stat & SM_FLASH_STATUS_DONE));
258
259 out_8(base, SM_FLASH_CMD_CLEAR_STATUS);
260 out_8(base, SM_FLASH_CMD_RESET);
261
262 for (i=0; i<NVRAM_SIZE; i++)
263 if (base[i] != 0xff) {
264 printk(KERN_ERR "nvram: Sharp/Micron flash erase failed !\n");
265 return -ENXIO;
266 }
267 return 0;
268}
269
270static int sm_write_bank(int bank, u8* datas)
271{
272 int i, stat = 0;
273 unsigned long timeout;
274
275 u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;
276
277 DBG("nvram: Sharp/Micron Writing bank %d...\n", bank);
278
279 for (i=0; i<NVRAM_SIZE; i++) {
280 out_8(base+i, SM_FLASH_CMD_WRITE_SETUP);
281 udelay(1);
282 out_8(base+i, datas[i]);
283 timeout = 0;
284 do {
285 if (++timeout > 1000000) {
286 printk(KERN_ERR "nvram: Sharp/Micron flash write timeout !\n");
287 break;
288 }
289 out_8(base, SM_FLASH_CMD_READ_STATUS);
290 stat = in_8(base);
291 } while (!(stat & SM_FLASH_STATUS_DONE));
292 if (!(stat & SM_FLASH_STATUS_DONE))
293 break;
294 }
295 out_8(base, SM_FLASH_CMD_CLEAR_STATUS);
296 out_8(base, SM_FLASH_CMD_RESET);
297 for (i=0; i<NVRAM_SIZE; i++)
298 if (base[i] != datas[i]) {
299 printk(KERN_ERR "nvram: Sharp/Micron flash write failed !\n");
300 return -ENXIO;
301 }
302 return 0;
303}
304
305static int amd_erase_bank(int bank)
306{
307 int i, stat = 0;
308 unsigned long timeout;
309
310 u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;
311
312 DBG("nvram: AMD Erasing bank %d...\n", bank);
313
314 /* Unlock 1 */
315 out_8(base+0x555, 0xaa);
316 udelay(1);
317 /* Unlock 2 */
318 out_8(base+0x2aa, 0x55);
319 udelay(1);
320
321 /* Sector-Erase */
322 out_8(base+0x555, 0x80);
323 udelay(1);
324 out_8(base+0x555, 0xaa);
325 udelay(1);
326 out_8(base+0x2aa, 0x55);
327 udelay(1);
328 out_8(base, 0x30);
329 udelay(1);
330
331 timeout = 0;
332 do {
333 if (++timeout > 1000000) {
334 printk(KERN_ERR "nvram: AMD flash erase timeout !\n");
335 break;
336 }
337 stat = in_8(base) ^ in_8(base);
338 } while (stat != 0);
339
340 /* Reset */
341 out_8(base, 0xf0);
342 udelay(1);
343
344 for (i=0; i<NVRAM_SIZE; i++)
345 if (base[i] != 0xff) {
346 printk(KERN_ERR "nvram: AMD flash erase failed !\n");
347 return -ENXIO;
348 }
349 return 0;
350}
351
352static int amd_write_bank(int bank, u8* datas)
353{
354 int i, stat = 0;
355 unsigned long timeout;
356
357 u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE;
358
359 DBG("nvram: AMD Writing bank %d...\n", bank);
360
361 for (i=0; i<NVRAM_SIZE; i++) {
362 /* Unlock 1 */
363 out_8(base+0x555, 0xaa);
364 udelay(1);
365 /* Unlock 2 */
366 out_8(base+0x2aa, 0x55);
367 udelay(1);
368
369 /* Write single word */
370 out_8(base+0x555, 0xa0);
371 udelay(1);
372 out_8(base+i, datas[i]);
373
374 timeout = 0;
375 do {
376 if (++timeout > 1000000) {
377 printk(KERN_ERR "nvram: AMD flash write timeout !\n");
378 break;
379 }
380 stat = in_8(base) ^ in_8(base);
381 } while (stat != 0);
382 if (stat != 0)
383 break;
384 }
385
386 /* Reset */
387 out_8(base, 0xf0);
388 udelay(1);
389
390 for (i=0; i<NVRAM_SIZE; i++)
391 if (base[i] != datas[i]) {
392 printk(KERN_ERR "nvram: AMD flash write failed !\n");
393 return -ENXIO;
394 }
395 return 0;
396}
397
398static void __init lookup_partitions(void)
399{
400 u8 buffer[17];
401 int i, offset;
402 struct chrp_header* hdr;
403
404 if (pmac_newworld) {
405 nvram_partitions[pmac_nvram_OF] = -1;
406 nvram_partitions[pmac_nvram_XPRAM] = -1;
407 nvram_partitions[pmac_nvram_NR] = -1;
408 hdr = (struct chrp_header *)buffer;
409
410 offset = 0;
411 buffer[16] = 0;
412 do {
413 for (i=0;i<16;i++)
414 buffer[i] = nvram_read_byte(offset+i);
415 if (!strcmp(hdr->name, "common"))
416 nvram_partitions[pmac_nvram_OF] = offset + 0x10;
417 if (!strcmp(hdr->name, "APL,MacOS75")) {
418 nvram_partitions[pmac_nvram_XPRAM] = offset + 0x10;
419 nvram_partitions[pmac_nvram_NR] = offset + 0x110;
420 }
421 offset += (hdr->len * 0x10);
422 } while(offset < NVRAM_SIZE);
423 } else {
424 nvram_partitions[pmac_nvram_OF] = 0x1800;
425 nvram_partitions[pmac_nvram_XPRAM] = 0x1300;
426 nvram_partitions[pmac_nvram_NR] = 0x1400;
427 }
428 DBG("nvram: OF partition at 0x%x\n", nvram_partitions[pmac_nvram_OF]);
429 DBG("nvram: XP partition at 0x%x\n", nvram_partitions[pmac_nvram_XPRAM]);
430 DBG("nvram: NR partition at 0x%x\n", nvram_partitions[pmac_nvram_NR]);
431}
432
433static void core99_nvram_sync(void)
434{
435 struct core99_header* hdr99;
436 unsigned long flags;
437
438 if (!is_core_99 || !nvram_data || !nvram_image)
439 return;
440
441 spin_lock_irqsave(&nv_lock, flags);
442 if (!memcmp(nvram_image, (u8*)nvram_data + core99_bank*NVRAM_SIZE,
443 NVRAM_SIZE))
444 goto bail;
445
446 DBG("Updating nvram...\n");
447
448 hdr99 = (struct core99_header*)nvram_image;
449 hdr99->generation++;
450 hdr99->hdr.signature = CORE99_SIGNATURE;
451 hdr99->hdr.cksum = chrp_checksum(&hdr99->hdr);
452 hdr99->adler = core99_calc_adler(nvram_image);
453 core99_bank = core99_bank ? 0 : 1;
454 if (core99_erase_bank)
455 if (core99_erase_bank(core99_bank)) {
456 printk("nvram: Error erasing bank %d\n", core99_bank);
457 goto bail;
458 }
459 if (core99_write_bank)
460 if (core99_write_bank(core99_bank, nvram_image))
461 printk("nvram: Error writing bank %d\n", core99_bank);
462 bail:
463 spin_unlock_irqrestore(&nv_lock, flags);
464
465#ifdef DEBUG
466 mdelay(2000);
467#endif
468}
469
470void __init pmac_nvram_init(void)
471{
472 struct device_node *dp;
473
474 nvram_naddrs = 0;
475
476 dp = find_devices("nvram");
477 if (dp == NULL) {
478 printk(KERN_ERR "Can't find NVRAM device\n");
479 return;
480 }
481 nvram_naddrs = dp->n_addrs;
482 is_core_99 = device_is_compatible(dp, "nvram,flash");
483 if (is_core_99) {
484 int i;
485 u32 gen_bank0, gen_bank1;
486
487 if (nvram_naddrs < 1) {
488 printk(KERN_ERR "nvram: no address\n");
489 return;
490 }
491 nvram_image = alloc_bootmem(NVRAM_SIZE);
492 if (nvram_image == NULL) {
493 printk(KERN_ERR "nvram: can't allocate ram image\n");
494 return;
495 }
496 nvram_data = ioremap(dp->addrs[0].address, NVRAM_SIZE*2);
497 nvram_naddrs = 1; /* Make sure we get the correct case */
498
499 DBG("nvram: Checking bank 0...\n");
500
501 gen_bank0 = core99_check((u8 *)nvram_data);
502 gen_bank1 = core99_check((u8 *)nvram_data + NVRAM_SIZE);
503 core99_bank = (gen_bank0 < gen_bank1) ? 1 : 0;
504
505 DBG("nvram: gen0=%d, gen1=%d\n", gen_bank0, gen_bank1);
506 DBG("nvram: Active bank is: %d\n", core99_bank);
507
508 for (i=0; i<NVRAM_SIZE; i++)
509 nvram_image[i] = nvram_data[i + core99_bank*NVRAM_SIZE];
510
511 ppc_md.nvram_read_val = core99_nvram_read_byte;
512 ppc_md.nvram_write_val = core99_nvram_write_byte;
513 ppc_md.nvram_sync = core99_nvram_sync;
514 /*
515 * Maybe we could be smarter here though making an exclusive list
516 * of known flash chips is a bit nasty as older OF didn't provide us
517 * with a useful "compatible" entry. A solution would be to really
518 * identify the chip using flash id commands and base ourselves on
519 * a list of known chips IDs
520 */
521 if (device_is_compatible(dp, "amd-0137")) {
522 core99_erase_bank = amd_erase_bank;
523 core99_write_bank = amd_write_bank;
524 } else {
525 core99_erase_bank = sm_erase_bank;
526 core99_write_bank = sm_write_bank;
527 }
528 } else if (_machine == _MACH_chrp && nvram_naddrs == 1) {
529 nvram_data = ioremap(dp->addrs[0].address + isa_mem_base,
530 dp->addrs[0].size);
531 nvram_mult = 1;
532 ppc_md.nvram_read_val = direct_nvram_read_byte;
533 ppc_md.nvram_write_val = direct_nvram_write_byte;
534 } else if (nvram_naddrs == 1) {
535 nvram_data = ioremap(dp->addrs[0].address, dp->addrs[0].size);
536 nvram_mult = (dp->addrs[0].size + NVRAM_SIZE - 1) / NVRAM_SIZE;
537 ppc_md.nvram_read_val = direct_nvram_read_byte;
538 ppc_md.nvram_write_val = direct_nvram_write_byte;
539 } else if (nvram_naddrs == 2) {
540 nvram_addr = ioremap(dp->addrs[0].address, dp->addrs[0].size);
541 nvram_data = ioremap(dp->addrs[1].address, dp->addrs[1].size);
542 ppc_md.nvram_read_val = indirect_nvram_read_byte;
543 ppc_md.nvram_write_val = indirect_nvram_write_byte;
544 } else if (nvram_naddrs == 0 && sys_ctrler == SYS_CTRLER_PMU) {
545#ifdef CONFIG_ADB_PMU
546 nvram_naddrs = -1;
547 ppc_md.nvram_read_val = pmu_nvram_read_byte;
548 ppc_md.nvram_write_val = pmu_nvram_write_byte;
549#endif /* CONFIG_ADB_PMU */
550 } else {
551 printk(KERN_ERR "Don't know how to access NVRAM with %d addresses\n",
552 nvram_naddrs);
553 }
554 lookup_partitions();
555}
556
557int pmac_get_partition(int partition)
558{
559 return nvram_partitions[partition];
560}
561
562u8 pmac_xpram_read(int xpaddr)
563{
564 int offset = nvram_partitions[pmac_nvram_XPRAM];
565
566 if (offset < 0)
567 return 0xff;
568
569 return ppc_md.nvram_read_val(xpaddr + offset);
570}
571
572void pmac_xpram_write(int xpaddr, u8 data)
573{
574 int offset = nvram_partitions[pmac_nvram_XPRAM];
575
576 if (offset < 0)
577 return;
578
579 ppc_md.nvram_write_val(xpaddr + offset, data);
580}
581
582EXPORT_SYMBOL(pmac_get_partition);
583EXPORT_SYMBOL(pmac_xpram_read);
584EXPORT_SYMBOL(pmac_xpram_write);
diff --git a/arch/ppc/platforms/pmac_pci.c b/arch/ppc/platforms/pmac_pci.c
deleted file mode 100644
index 786295b6ddd..00000000000
--- a/arch/ppc/platforms/pmac_pci.c
+++ /dev/null
@@ -1,1124 +0,0 @@
1/*
2 * Support for PCI bridges found on Power Macintoshes.
3 * At present the "bandit" and "chaos" bridges are supported.
4 * Fortunately you access configuration space in the same
5 * way with either bridge.
6 *
7 * Copyright (C) 1997 Paul Mackerras (paulus@cs.anu.edu.au)
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14
15#include <linux/kernel.h>
16#include <linux/pci.h>
17#include <linux/delay.h>
18#include <linux/string.h>
19#include <linux/init.h>
20
21#include <asm/sections.h>
22#include <asm/io.h>
23#include <asm/prom.h>
24#include <asm/pci-bridge.h>
25#include <asm/machdep.h>
26#include <asm/pmac_feature.h>
27
28#undef DEBUG
29
30#ifdef DEBUG
31#ifdef CONFIG_XMON
32extern void xmon_printf(const char *fmt, ...);
33#define DBG(x...) xmon_printf(x)
34#else
35#define DBG(x...) printk(x)
36#endif
37#else
38#define DBG(x...)
39#endif
40
41static int add_bridge(struct device_node *dev);
42extern void pmac_check_ht_link(void);
43
44/* XXX Could be per-controller, but I don't think we risk anything by
45 * assuming we won't have both UniNorth and Bandit */
46static int has_uninorth;
47#ifdef CONFIG_POWER4
48static struct pci_controller *u3_agp;
49#endif /* CONFIG_POWER4 */
50
51extern u8 pci_cache_line_size;
52extern int pcibios_assign_bus_offset;
53
54struct device_node *k2_skiplist[2];
55
56/*
57 * Magic constants for enabling cache coherency in the bandit/PSX bridge.
58 */
59#define BANDIT_DEVID_2 8
60#define BANDIT_REVID 3
61
62#define BANDIT_DEVNUM 11
63#define BANDIT_MAGIC 0x50
64#define BANDIT_COHERENT 0x40
65
66static int __init
67fixup_one_level_bus_range(struct device_node *node, int higher)
68{
69 for (; node != 0;node = node->sibling) {
70 int * bus_range;
71 unsigned int *class_code;
72 int len;
73
74 /* For PCI<->PCI bridges or CardBus bridges, we go down */
75 class_code = (unsigned int *) get_property(node, "class-code", NULL);
76 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
77 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
78 continue;
79 bus_range = (int *) get_property(node, "bus-range", &len);
80 if (bus_range != NULL && len > 2 * sizeof(int)) {
81 if (bus_range[1] > higher)
82 higher = bus_range[1];
83 }
84 higher = fixup_one_level_bus_range(node->child, higher);
85 }
86 return higher;
87}
88
89/* This routine fixes the "bus-range" property of all bridges in the
90 * system since they tend to have their "last" member wrong on macs
91 *
92 * Note that the bus numbers manipulated here are OF bus numbers, they
93 * are not Linux bus numbers.
94 */
95static void __init
96fixup_bus_range(struct device_node *bridge)
97{
98 int * bus_range;
99 int len;
100
101 /* Lookup the "bus-range" property for the hose */
102 bus_range = (int *) get_property(bridge, "bus-range", &len);
103 if (bus_range == NULL || len < 2 * sizeof(int)) {
104 printk(KERN_WARNING "Can't get bus-range for %s\n",
105 bridge->full_name);
106 return;
107 }
108 bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]);
109}
110
111/*
112 * Apple MacRISC (U3, UniNorth, Bandit, Chaos) PCI controllers.
113 *
114 * The "Bandit" version is present in all early PCI PowerMacs,
115 * and up to the first ones using Grackle. Some machines may
116 * have 2 bandit controllers (2 PCI busses).
117 *
118 * "Chaos" is used in some "Bandit"-type machines as a bridge
119 * for the separate display bus. It is accessed the same
120 * way as bandit, but cannot be probed for devices. It therefore
121 * has its own config access functions.
122 *
123 * The "UniNorth" version is present in all Core99 machines
124 * (iBook, G4, new IMacs, and all the recent Apple machines).
125 * It contains 3 controllers in one ASIC.
126 *
127 * The U3 is the bridge used on G5 machines. It contains an
128 * AGP bus which is dealt with the old UniNorth access routines
129 * and a HyperTransport bus which uses its own set of access
130 * functions.
131 */
132
133#define MACRISC_CFA0(devfn, off) \
134 ((1 << (unsigned long)PCI_SLOT(dev_fn)) \
135 | (((unsigned long)PCI_FUNC(dev_fn)) << 8) \
136 | (((unsigned long)(off)) & 0xFCUL))
137
138#define MACRISC_CFA1(bus, devfn, off) \
139 ((((unsigned long)(bus)) << 16) \
140 |(((unsigned long)(devfn)) << 8) \
141 |(((unsigned long)(off)) & 0xFCUL) \
142 |1UL)
143
144static void volatile __iomem *
145macrisc_cfg_access(struct pci_controller* hose, u8 bus, u8 dev_fn, u8 offset)
146{
147 unsigned int caddr;
148
149 if (bus == hose->first_busno) {
150 if (dev_fn < (11 << 3))
151 return NULL;
152 caddr = MACRISC_CFA0(dev_fn, offset);
153 } else
154 caddr = MACRISC_CFA1(bus, dev_fn, offset);
155
156 /* Uninorth will return garbage if we don't read back the value ! */
157 do {
158 out_le32(hose->cfg_addr, caddr);
159 } while (in_le32(hose->cfg_addr) != caddr);
160
161 offset &= has_uninorth ? 0x07 : 0x03;
162 return hose->cfg_data + offset;
163}
164
165static int
166macrisc_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
167 int len, u32 *val)
168{
169 struct pci_controller *hose = bus->sysdata;
170 void volatile __iomem *addr;
171
172 addr = macrisc_cfg_access(hose, bus->number, devfn, offset);
173 if (!addr)
174 return PCIBIOS_DEVICE_NOT_FOUND;
175 /*
176 * Note: the caller has already checked that offset is
177 * suitably aligned and that len is 1, 2 or 4.
178 */
179 switch (len) {
180 case 1:
181 *val = in_8(addr);
182 break;
183 case 2:
184 *val = in_le16(addr);
185 break;
186 default:
187 *val = in_le32(addr);
188 break;
189 }
190 return PCIBIOS_SUCCESSFUL;
191}
192
193static int
194macrisc_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
195 int len, u32 val)
196{
197 struct pci_controller *hose = bus->sysdata;
198 void volatile __iomem *addr;
199
200 addr = macrisc_cfg_access(hose, bus->number, devfn, offset);
201 if (!addr)
202 return PCIBIOS_DEVICE_NOT_FOUND;
203 /*
204 * Note: the caller has already checked that offset is
205 * suitably aligned and that len is 1, 2 or 4.
206 */
207 switch (len) {
208 case 1:
209 out_8(addr, val);
210 (void) in_8(addr);
211 break;
212 case 2:
213 out_le16(addr, val);
214 (void) in_le16(addr);
215 break;
216 default:
217 out_le32(addr, val);
218 (void) in_le32(addr);
219 break;
220 }
221 return PCIBIOS_SUCCESSFUL;
222}
223
224static struct pci_ops macrisc_pci_ops =
225{
226 macrisc_read_config,
227 macrisc_write_config
228};
229
230/*
231 * Verifiy that a specific (bus, dev_fn) exists on chaos
232 */
233static int
234chaos_validate_dev(struct pci_bus *bus, int devfn, int offset)
235{
236 struct device_node *np;
237 u32 *vendor, *device;
238
239 np = pci_busdev_to_OF_node(bus, devfn);
240 if (np == NULL)
241 return PCIBIOS_DEVICE_NOT_FOUND;
242
243 vendor = (u32 *)get_property(np, "vendor-id", NULL);
244 device = (u32 *)get_property(np, "device-id", NULL);
245 if (vendor == NULL || device == NULL)
246 return PCIBIOS_DEVICE_NOT_FOUND;
247
248 if ((*vendor == 0x106b) && (*device == 3) && (offset >= 0x10)
249 && (offset != 0x14) && (offset != 0x18) && (offset <= 0x24))
250 return PCIBIOS_BAD_REGISTER_NUMBER;
251
252 return PCIBIOS_SUCCESSFUL;
253}
254
255static int
256chaos_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
257 int len, u32 *val)
258{
259 int result = chaos_validate_dev(bus, devfn, offset);
260 if (result == PCIBIOS_BAD_REGISTER_NUMBER)
261 *val = ~0U;
262 if (result != PCIBIOS_SUCCESSFUL)
263 return result;
264 return macrisc_read_config(bus, devfn, offset, len, val);
265}
266
267static int
268chaos_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
269 int len, u32 val)
270{
271 int result = chaos_validate_dev(bus, devfn, offset);
272 if (result != PCIBIOS_SUCCESSFUL)
273 return result;
274 return macrisc_write_config(bus, devfn, offset, len, val);
275}
276
277static struct pci_ops chaos_pci_ops =
278{
279 chaos_read_config,
280 chaos_write_config
281};
282
283#ifdef CONFIG_POWER4
284
285/*
286 * These versions of U3 HyperTransport config space access ops do not
287 * implement self-view of the HT host yet
288 */
289
290#define U3_HT_CFA0(devfn, off) \
291 ((((unsigned long)devfn) << 8) | offset)
292#define U3_HT_CFA1(bus, devfn, off) \
293 (U3_HT_CFA0(devfn, off) \
294 + (((unsigned long)bus) << 16) \
295 + 0x01000000UL)
296
297static void volatile __iomem *
298u3_ht_cfg_access(struct pci_controller* hose, u8 bus, u8 devfn, u8 offset)
299{
300 if (bus == hose->first_busno) {
301 /* For now, we don't self probe U3 HT bridge */
302 if (PCI_FUNC(devfn) != 0 || PCI_SLOT(devfn) > 7 ||
303 PCI_SLOT(devfn) < 1)
304 return 0;
305 return hose->cfg_data + U3_HT_CFA0(devfn, offset);
306 } else
307 return hose->cfg_data + U3_HT_CFA1(bus, devfn, offset);
308}
309
310static int
311u3_ht_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
312 int len, u32 *val)
313{
314 struct pci_controller *hose = bus->sysdata;
315 void volatile __iomem *addr;
316 int i;
317
318 struct device_node *np = pci_busdev_to_OF_node(bus, devfn);
319 if (np == NULL)
320 return PCIBIOS_DEVICE_NOT_FOUND;
321
322 /*
323 * When a device in K2 is powered down, we die on config
324 * cycle accesses. Fix that here.
325 */
326 for (i=0; i<2; i++)
327 if (k2_skiplist[i] == np) {
328 switch (len) {
329 case 1:
330 *val = 0xff; break;
331 case 2:
332 *val = 0xffff; break;
333 default:
334 *val = 0xfffffffful; break;
335 }
336 return PCIBIOS_SUCCESSFUL;
337 }
338
339 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
340 if (!addr)
341 return PCIBIOS_DEVICE_NOT_FOUND;
342 /*
343 * Note: the caller has already checked that offset is
344 * suitably aligned and that len is 1, 2 or 4.
345 */
346 switch (len) {
347 case 1:
348 *val = in_8(addr);
349 break;
350 case 2:
351 *val = in_le16(addr);
352 break;
353 default:
354 *val = in_le32(addr);
355 break;
356 }
357 return PCIBIOS_SUCCESSFUL;
358}
359
360static int
361u3_ht_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
362 int len, u32 val)
363{
364 struct pci_controller *hose = bus->sysdata;
365 void volatile __iomem *addr;
366 int i;
367
368 struct device_node *np = pci_busdev_to_OF_node(bus, devfn);
369 if (np == NULL)
370 return PCIBIOS_DEVICE_NOT_FOUND;
371 /*
372 * When a device in K2 is powered down, we die on config
373 * cycle accesses. Fix that here.
374 */
375 for (i=0; i<2; i++)
376 if (k2_skiplist[i] == np)
377 return PCIBIOS_SUCCESSFUL;
378
379 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
380 if (!addr)
381 return PCIBIOS_DEVICE_NOT_FOUND;
382 /*
383 * Note: the caller has already checked that offset is
384 * suitably aligned and that len is 1, 2 or 4.
385 */
386 switch (len) {
387 case 1:
388 out_8(addr, val);
389 (void) in_8(addr);
390 break;
391 case 2:
392 out_le16(addr, val);
393 (void) in_le16(addr);
394 break;
395 default:
396 out_le32(addr, val);
397 (void) in_le32(addr);
398 break;
399 }
400 return PCIBIOS_SUCCESSFUL;
401}
402
403static struct pci_ops u3_ht_pci_ops =
404{
405 u3_ht_read_config,
406 u3_ht_write_config
407};
408
409#endif /* CONFIG_POWER4 */
410
411/*
412 * For a bandit bridge, turn on cache coherency if necessary.
413 * N.B. we could clean this up using the hose ops directly.
414 */
415static void __init
416init_bandit(struct pci_controller *bp)
417{
418 unsigned int vendev, magic;
419 int rev;
420
421 /* read the word at offset 0 in config space for device 11 */
422 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + PCI_VENDOR_ID);
423 udelay(2);
424 vendev = in_le32(bp->cfg_data);
425 if (vendev == (PCI_DEVICE_ID_APPLE_BANDIT << 16) +
426 PCI_VENDOR_ID_APPLE) {
427 /* read the revision id */
428 out_le32(bp->cfg_addr,
429 (1UL << BANDIT_DEVNUM) + PCI_REVISION_ID);
430 udelay(2);
431 rev = in_8(bp->cfg_data);
432 if (rev != BANDIT_REVID)
433 printk(KERN_WARNING
434 "Unknown revision %d for bandit\n", rev);
435 } else if (vendev != (BANDIT_DEVID_2 << 16) + PCI_VENDOR_ID_APPLE) {
436 printk(KERN_WARNING "bandit isn't? (%x)\n", vendev);
437 return;
438 }
439
440 /* read the word at offset 0x50 */
441 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + BANDIT_MAGIC);
442 udelay(2);
443 magic = in_le32(bp->cfg_data);
444 if ((magic & BANDIT_COHERENT) != 0)
445 return;
446 magic |= BANDIT_COHERENT;
447 udelay(2);
448 out_le32(bp->cfg_data, magic);
449 printk(KERN_INFO "Cache coherency enabled for bandit/PSX\n");
450}
451
452
453/*
454 * Tweak the PCI-PCI bridge chip on the blue & white G3s.
455 */
456static void __init
457init_p2pbridge(void)
458{
459 struct device_node *p2pbridge;
460 struct pci_controller* hose;
461 u8 bus, devfn;
462 u16 val;
463
464 /* XXX it would be better here to identify the specific
465 PCI-PCI bridge chip we have. */
466 if ((p2pbridge = find_devices("pci-bridge")) == 0
467 || p2pbridge->parent == NULL
468 || strcmp(p2pbridge->parent->name, "pci") != 0)
469 return;
470 if (pci_device_from_OF_node(p2pbridge, &bus, &devfn) < 0) {
471 DBG("Can't find PCI infos for PCI<->PCI bridge\n");
472 return;
473 }
474 /* Warning: At this point, we have not yet renumbered all busses.
475 * So we must use OF walking to find out hose
476 */
477 hose = pci_find_hose_for_OF_device(p2pbridge);
478 if (!hose) {
479 DBG("Can't find hose for PCI<->PCI bridge\n");
480 return;
481 }
482 if (early_read_config_word(hose, bus, devfn,
483 PCI_BRIDGE_CONTROL, &val) < 0) {
484 printk(KERN_ERR "init_p2pbridge: couldn't read bridge control\n");
485 return;
486 }
487 val &= ~PCI_BRIDGE_CTL_MASTER_ABORT;
488 early_write_config_word(hose, bus, devfn, PCI_BRIDGE_CONTROL, val);
489}
490
491/*
492 * Some Apple desktop machines have a NEC PD720100A USB2 controller
493 * on the motherboard. Open Firmware, on these, will disable the
494 * EHCI part of it so it behaves like a pair of OHCI's. This fixup
495 * code re-enables it ;)
496 */
497static void __init
498fixup_nec_usb2(void)
499{
500 struct device_node *nec;
501
502 for (nec = NULL; (nec = of_find_node_by_name(nec, "usb")) != NULL;) {
503 struct pci_controller *hose;
504 u32 data, *prop;
505 u8 bus, devfn;
506
507 prop = (u32 *)get_property(nec, "vendor-id", NULL);
508 if (prop == NULL)
509 continue;
510 if (0x1033 != *prop)
511 continue;
512 prop = (u32 *)get_property(nec, "device-id", NULL);
513 if (prop == NULL)
514 continue;
515 if (0x0035 != *prop)
516 continue;
517 prop = (u32 *)get_property(nec, "reg", NULL);
518 if (prop == NULL)
519 continue;
520 devfn = (prop[0] >> 8) & 0xff;
521 bus = (prop[0] >> 16) & 0xff;
522 if (PCI_FUNC(devfn) != 0)
523 continue;
524 hose = pci_find_hose_for_OF_device(nec);
525 if (!hose)
526 continue;
527 early_read_config_dword(hose, bus, devfn, 0xe4, &data);
528 if (data & 1UL) {
529 printk("Found NEC PD720100A USB2 chip with disabled EHCI, fixing up...\n");
530 data &= ~1UL;
531 early_write_config_dword(hose, bus, devfn, 0xe4, data);
532 early_write_config_byte(hose, bus, devfn | 2, PCI_INTERRUPT_LINE,
533 nec->intrs[0].line);
534 }
535 }
536}
537
538void __init
539pmac_find_bridges(void)
540{
541 struct device_node *np, *root;
542 struct device_node *ht = NULL;
543
544 root = of_find_node_by_path("/");
545 if (root == NULL) {
546 printk(KERN_CRIT "pmac_find_bridges: can't find root of device tree\n");
547 return;
548 }
549 for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) {
550 if (np->name == NULL)
551 continue;
552 if (strcmp(np->name, "bandit") == 0
553 || strcmp(np->name, "chaos") == 0
554 || strcmp(np->name, "pci") == 0) {
555 if (add_bridge(np) == 0)
556 of_node_get(np);
557 }
558 if (strcmp(np->name, "ht") == 0) {
559 of_node_get(np);
560 ht = np;
561 }
562 }
563 of_node_put(root);
564
565 /* Probe HT last as it relies on the agp resources to be already
566 * setup
567 */
568 if (ht && add_bridge(ht) != 0)
569 of_node_put(ht);
570
571 init_p2pbridge();
572 fixup_nec_usb2();
573
574 /* We are still having some issues with the Xserve G4, enabling
575 * some offset between bus number and domains for now when we
576 * assign all busses should help for now
577 */
578 if (pci_assign_all_buses)
579 pcibios_assign_bus_offset = 0x10;
580
581#ifdef CONFIG_POWER4
582 /* There is something wrong with DMA on U3/HT. I haven't figured out
583 * the details yet, but if I set the cache line size to 128 bytes like
584 * it should, I'm getting memory corruption caused by devices like
585 * sungem (even without the MWI bit set, but maybe sungem doesn't
586 * care). Right now, it appears that setting up a 64 bytes line size
587 * works properly, 64 bytes beeing the max transfer size of HT, I
588 * suppose this is related the way HT/PCI are hooked together. I still
589 * need to dive into more specs though to be really sure of what's
590 * going on. --BenH.
591 *
592 * Ok, apparently, it's just that HT can't do more than 64 bytes
593 * transactions. MWI seem to be meaningless there as well, it may
594 * be worth nop'ing out pci_set_mwi too though I haven't done that
595 * yet.
596 *
597 * Note that it's a bit different for whatever is in the AGP slot.
598 * For now, I don't care, but this can become a real issue, we
599 * should probably hook pci_set_mwi anyway to make sure it sets
600 * the real cache line size in there.
601 */
602 if (machine_is_compatible("MacRISC4"))
603 pci_cache_line_size = 16; /* 64 bytes */
604
605 pmac_check_ht_link();
606#endif /* CONFIG_POWER4 */
607}
608
609#define GRACKLE_CFA(b, d, o) (0x80 | ((b) << 8) | ((d) << 16) \
610 | (((o) & ~3) << 24))
611
612#define GRACKLE_PICR1_STG 0x00000040
613#define GRACKLE_PICR1_LOOPSNOOP 0x00000010
614
615/* N.B. this is called before bridges is initialized, so we can't
616 use grackle_pcibios_{read,write}_config_dword. */
617static inline void grackle_set_stg(struct pci_controller* bp, int enable)
618{
619 unsigned int val;
620
621 out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8));
622 val = in_le32(bp->cfg_data);
623 val = enable? (val | GRACKLE_PICR1_STG) :
624 (val & ~GRACKLE_PICR1_STG);
625 out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8));
626 out_le32(bp->cfg_data, val);
627 (void)in_le32(bp->cfg_data);
628}
629
630static inline void grackle_set_loop_snoop(struct pci_controller *bp, int enable)
631{
632 unsigned int val;
633
634 out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8));
635 val = in_le32(bp->cfg_data);
636 val = enable? (val | GRACKLE_PICR1_LOOPSNOOP) :
637 (val & ~GRACKLE_PICR1_LOOPSNOOP);
638 out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8));
639 out_le32(bp->cfg_data, val);
640 (void)in_le32(bp->cfg_data);
641}
642
643static int __init
644setup_uninorth(struct pci_controller* hose, struct reg_property* addr)
645{
646 pci_assign_all_buses = 1;
647 has_uninorth = 1;
648 hose->ops = &macrisc_pci_ops;
649 hose->cfg_addr = ioremap(addr->address + 0x800000, 0x1000);
650 hose->cfg_data = ioremap(addr->address + 0xc00000, 0x1000);
651 /* We "know" that the bridge at f2000000 has the PCI slots. */
652 return addr->address == 0xf2000000;
653}
654
655static void __init
656setup_bandit(struct pci_controller* hose, struct reg_property* addr)
657{
658 hose->ops = &macrisc_pci_ops;
659 hose->cfg_addr = ioremap(addr->address + 0x800000, 0x1000);
660 hose->cfg_data = ioremap(addr->address + 0xc00000, 0x1000);
661 init_bandit(hose);
662}
663
664static void __init
665setup_chaos(struct pci_controller* hose, struct reg_property* addr)
666{
667 /* assume a `chaos' bridge */
668 hose->ops = &chaos_pci_ops;
669 hose->cfg_addr = ioremap(addr->address + 0x800000, 0x1000);
670 hose->cfg_data = ioremap(addr->address + 0xc00000, 0x1000);
671}
672
673#ifdef CONFIG_POWER4
674
675static void __init
676setup_u3_agp(struct pci_controller* hose, struct reg_property* addr)
677{
678 /* On G5, we move AGP up to high bus number so we don't need
679 * to reassign bus numbers for HT. If we ever have P2P bridges
680 * on AGP, we'll have to move pci_assign_all_buses to the
681 * pci_controller structure so we enable it for AGP and not for
682 * HT childs.
683 * We hard code the address because of the different size of
684 * the reg address cell, we shall fix that by killing struct
685 * reg_property and using some accessor functions instead
686 */
687 hose->first_busno = 0xf0;
688 hose->last_busno = 0xff;
689 has_uninorth = 1;
690 hose->ops = &macrisc_pci_ops;
691 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
692 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
693
694 u3_agp = hose;
695}
696
697static void __init
698setup_u3_ht(struct pci_controller* hose, struct reg_property *addr)
699{
700 struct device_node *np = (struct device_node *)hose->arch_data;
701 int i, cur;
702
703 hose->ops = &u3_ht_pci_ops;
704
705 /* We hard code the address because of the different size of
706 * the reg address cell, we shall fix that by killing struct
707 * reg_property and using some accessor functions instead
708 */
709 hose->cfg_data = ioremap(0xf2000000, 0x02000000);
710
711 /*
712 * /ht node doesn't expose a "ranges" property, so we "remove" regions that
713 * have been allocated to AGP. So far, this version of the code doesn't assign
714 * any of the 0xfxxxxxxx "fine" memory regions to /ht.
715 * We need to fix that sooner or later by either parsing all child "ranges"
716 * properties or figuring out the U3 address space decoding logic and
717 * then read its configuration register (if any).
718 */
719 hose->io_base_phys = 0xf4000000;
720 hose->io_base_virt = ioremap(hose->io_base_phys, 0x00400000);
721 isa_io_base = (unsigned long) hose->io_base_virt;
722 hose->io_resource.name = np->full_name;
723 hose->io_resource.start = 0;
724 hose->io_resource.end = 0x003fffff;
725 hose->io_resource.flags = IORESOURCE_IO;
726 hose->pci_mem_offset = 0;
727 hose->first_busno = 0;
728 hose->last_busno = 0xef;
729 hose->mem_resources[0].name = np->full_name;
730 hose->mem_resources[0].start = 0x80000000;
731 hose->mem_resources[0].end = 0xefffffff;
732 hose->mem_resources[0].flags = IORESOURCE_MEM;
733
734 if (u3_agp == NULL) {
735 DBG("U3 has no AGP, using full resource range\n");
736 return;
737 }
738
739 /* We "remove" the AGP resources from the resources allocated to HT, that
740 * is we create "holes". However, that code does assumptions that so far
741 * happen to be true (cross fingers...), typically that resources in the
742 * AGP node are properly ordered
743 */
744 cur = 0;
745 for (i=0; i<3; i++) {
746 struct resource *res = &u3_agp->mem_resources[i];
747 if (res->flags != IORESOURCE_MEM)
748 continue;
749 /* We don't care about "fine" resources */
750 if (res->start >= 0xf0000000)
751 continue;
752 /* Check if it's just a matter of "shrinking" us in one direction */
753 if (hose->mem_resources[cur].start == res->start) {
754 DBG("U3/HT: shrink start of %d, %08lx -> %08lx\n",
755 cur, hose->mem_resources[cur].start, res->end + 1);
756 hose->mem_resources[cur].start = res->end + 1;
757 continue;
758 }
759 if (hose->mem_resources[cur].end == res->end) {
760 DBG("U3/HT: shrink end of %d, %08lx -> %08lx\n",
761 cur, hose->mem_resources[cur].end, res->start - 1);
762 hose->mem_resources[cur].end = res->start - 1;
763 continue;
764 }
765 /* No, it's not the case, we need a hole */
766 if (cur == 2) {
767 /* not enough resources to make a hole, we drop part of the range */
768 printk(KERN_WARNING "Running out of resources for /ht host !\n");
769 hose->mem_resources[cur].end = res->start - 1;
770 continue;
771 }
772 cur++;
773 DBG("U3/HT: hole, %d end at %08lx, %d start at %08lx\n",
774 cur-1, res->start - 1, cur, res->end + 1);
775 hose->mem_resources[cur].name = np->full_name;
776 hose->mem_resources[cur].flags = IORESOURCE_MEM;
777 hose->mem_resources[cur].start = res->end + 1;
778 hose->mem_resources[cur].end = hose->mem_resources[cur-1].end;
779 hose->mem_resources[cur-1].end = res->start - 1;
780 }
781}
782
783#endif /* CONFIG_POWER4 */
784
785void __init
786setup_grackle(struct pci_controller *hose)
787{
788 setup_indirect_pci(hose, 0xfec00000, 0xfee00000);
789 if (machine_is_compatible("AAPL,PowerBook1998"))
790 grackle_set_loop_snoop(hose, 1);
791#if 0 /* Disabled for now, HW problems ??? */
792 grackle_set_stg(hose, 1);
793#endif
794}
795
796/*
797 * We assume that if we have a G3 powermac, we have one bridge called
798 * "pci" (a MPC106) and no bandit or chaos bridges, and contrariwise,
799 * if we have one or more bandit or chaos bridges, we don't have a MPC106.
800 */
801static int __init
802add_bridge(struct device_node *dev)
803{
804 int len;
805 struct pci_controller *hose;
806 struct reg_property *addr;
807 char* disp_name;
808 int *bus_range;
809 int primary = 1;
810
811 DBG("Adding PCI host bridge %s\n", dev->full_name);
812
813 addr = (struct reg_property *) get_property(dev, "reg", &len);
814 if (addr == NULL || len < sizeof(*addr)) {
815 printk(KERN_WARNING "Can't use %s: no address\n",
816 dev->full_name);
817 return -ENODEV;
818 }
819 bus_range = (int *) get_property(dev, "bus-range", &len);
820 if (bus_range == NULL || len < 2 * sizeof(int)) {
821 printk(KERN_WARNING "Can't get bus-range for %s, assume bus 0\n",
822 dev->full_name);
823 }
824
825 hose = pcibios_alloc_controller();
826 if (!hose)
827 return -ENOMEM;
828 hose->arch_data = dev;
829 hose->first_busno = bus_range ? bus_range[0] : 0;
830 hose->last_busno = bus_range ? bus_range[1] : 0xff;
831
832 disp_name = NULL;
833#ifdef CONFIG_POWER4
834 if (device_is_compatible(dev, "u3-agp")) {
835 setup_u3_agp(hose, addr);
836 disp_name = "U3-AGP";
837 primary = 0;
838 } else if (device_is_compatible(dev, "u3-ht")) {
839 setup_u3_ht(hose, addr);
840 disp_name = "U3-HT";
841 primary = 1;
842 } else
843#endif /* CONFIG_POWER4 */
844 if (device_is_compatible(dev, "uni-north")) {
845 primary = setup_uninorth(hose, addr);
846 disp_name = "UniNorth";
847 } else if (strcmp(dev->name, "pci") == 0) {
848 /* XXX assume this is a mpc106 (grackle) */
849 setup_grackle(hose);
850 disp_name = "Grackle (MPC106)";
851 } else if (strcmp(dev->name, "bandit") == 0) {
852 setup_bandit(hose, addr);
853 disp_name = "Bandit";
854 } else if (strcmp(dev->name, "chaos") == 0) {
855 setup_chaos(hose, addr);
856 disp_name = "Chaos";
857 primary = 0;
858 }
859 printk(KERN_INFO "Found %s PCI host bridge at 0x%08x. Firmware bus number: %d->%d\n",
860 disp_name, addr->address, hose->first_busno, hose->last_busno);
861 DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
862 hose, hose->cfg_addr, hose->cfg_data);
863
864 /* Interpret the "ranges" property */
865 /* This also maps the I/O region and sets isa_io/mem_base */
866 pci_process_bridge_OF_ranges(hose, dev, primary);
867
868 /* Fixup "bus-range" OF property */
869 fixup_bus_range(dev);
870
871 return 0;
872}
873
874static void __init
875pcibios_fixup_OF_interrupts(void)
876{
877 struct pci_dev* dev = NULL;
878
879 /*
880 * Open Firmware often doesn't initialize the
881 * PCI_INTERRUPT_LINE config register properly, so we
882 * should find the device node and apply the interrupt
883 * obtained from the OF device-tree
884 */
885 for_each_pci_dev(dev) {
886 struct device_node *node;
887 node = pci_device_to_OF_node(dev);
888 /* this is the node, see if it has interrupts */
889 if (node && node->n_intrs > 0)
890 dev->irq = node->intrs[0].line;
891 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
892 }
893}
894
895void __init
896pmac_pcibios_fixup(void)
897{
898 /* Fixup interrupts according to OF tree */
899 pcibios_fixup_OF_interrupts();
900}
901
902int
903pmac_pci_enable_device_hook(struct pci_dev *dev, int initial)
904{
905 struct device_node* node;
906 int updatecfg = 0;
907 int uninorth_child;
908
909 node = pci_device_to_OF_node(dev);
910
911 /* We don't want to enable USB controllers absent from the OF tree
912 * (iBook second controller)
913 */
914 if (dev->vendor == PCI_VENDOR_ID_APPLE
915 && (dev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x10))
916 && !node) {
917 printk(KERN_INFO "Apple USB OHCI %s disabled by firmware\n",
918 pci_name(dev));
919 return -EINVAL;
920 }
921
922 if (!node)
923 return 0;
924
925 uninorth_child = node->parent &&
926 device_is_compatible(node->parent, "uni-north");
927
928 /* Firewire & GMAC were disabled after PCI probe, the driver is
929 * claiming them, we must re-enable them now.
930 */
931 if (uninorth_child && !strcmp(node->name, "firewire") &&
932 (device_is_compatible(node, "pci106b,18") ||
933 device_is_compatible(node, "pci106b,30") ||
934 device_is_compatible(node, "pci11c1,5811"))) {
935 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, node, 0, 1);
936 pmac_call_feature(PMAC_FTR_1394_ENABLE, node, 0, 1);
937 updatecfg = 1;
938 }
939 if (uninorth_child && !strcmp(node->name, "ethernet") &&
940 device_is_compatible(node, "gmac")) {
941 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, node, 0, 1);
942 updatecfg = 1;
943 }
944
945 if (updatecfg) {
946 u16 cmd;
947
948 /*
949 * Make sure PCI is correctly configured
950 *
951 * We use old pci_bios versions of the function since, by
952 * default, gmac is not powered up, and so will be absent
953 * from the kernel initial PCI lookup.
954 *
955 * Should be replaced by 2.4 new PCI mechanisms and really
956 * register the device.
957 */
958 pci_read_config_word(dev, PCI_COMMAND, &cmd);
959 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
960 pci_write_config_word(dev, PCI_COMMAND, cmd);
961 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 16);
962 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
963 }
964
965 return 0;
966}
967
968/* We power down some devices after they have been probed. They'll
969 * be powered back on later on
970 */
971void __init
972pmac_pcibios_after_init(void)
973{
974 struct device_node* nd;
975
976#ifdef CONFIG_BLK_DEV_IDE
977 struct pci_dev *dev = NULL;
978
979 /* OF fails to initialize IDE controllers on macs
980 * (and maybe other machines)
981 *
982 * Ideally, this should be moved to the IDE layer, but we need
983 * to check specifically with Andre Hedrick how to do it cleanly
984 * since the common IDE code seem to care about the fact that the
985 * BIOS may have disabled a controller.
986 *
987 * -- BenH
988 */
989 for_each_pci_dev(dev) {
990 if ((dev->class >> 16) == PCI_BASE_CLASS_STORAGE)
991 pci_enable_device(dev);
992 }
993#endif /* CONFIG_BLK_DEV_IDE */
994
995 nd = find_devices("firewire");
996 while (nd) {
997 if (nd->parent && (device_is_compatible(nd, "pci106b,18") ||
998 device_is_compatible(nd, "pci106b,30") ||
999 device_is_compatible(nd, "pci11c1,5811"))
1000 && device_is_compatible(nd->parent, "uni-north")) {
1001 pmac_call_feature(PMAC_FTR_1394_ENABLE, nd, 0, 0);
1002 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, nd, 0, 0);
1003 }
1004 nd = nd->next;
1005 }
1006 nd = find_devices("ethernet");
1007 while (nd) {
1008 if (nd->parent && device_is_compatible(nd, "gmac")
1009 && device_is_compatible(nd->parent, "uni-north"))
1010 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, nd, 0, 0);
1011 nd = nd->next;
1012 }
1013}
1014
1015void pmac_pci_fixup_cardbus(struct pci_dev* dev)
1016{
1017 if (_machine != _MACH_Pmac)
1018 return;
1019 /*
1020 * Fix the interrupt routing on the various cardbus bridges
1021 * used on powerbooks
1022 */
1023 if (dev->vendor != PCI_VENDOR_ID_TI)
1024 return;
1025 if (dev->device == PCI_DEVICE_ID_TI_1130 ||
1026 dev->device == PCI_DEVICE_ID_TI_1131) {
1027 u8 val;
1028 /* Enable PCI interrupt */
1029 if (pci_read_config_byte(dev, 0x91, &val) == 0)
1030 pci_write_config_byte(dev, 0x91, val | 0x30);
1031 /* Disable ISA interrupt mode */
1032 if (pci_read_config_byte(dev, 0x92, &val) == 0)
1033 pci_write_config_byte(dev, 0x92, val & ~0x06);
1034 }
1035 if (dev->device == PCI_DEVICE_ID_TI_1210 ||
1036 dev->device == PCI_DEVICE_ID_TI_1211 ||
1037 dev->device == PCI_DEVICE_ID_TI_1410 ||
1038 dev->device == PCI_DEVICE_ID_TI_1510) {
1039 u8 val;
1040 /* 0x8c == TI122X_IRQMUX, 2 says to route the INTA
1041 signal out the MFUNC0 pin */
1042 if (pci_read_config_byte(dev, 0x8c, &val) == 0)
1043 pci_write_config_byte(dev, 0x8c, (val & ~0x0f) | 2);
1044 /* Disable ISA interrupt mode */
1045 if (pci_read_config_byte(dev, 0x92, &val) == 0)
1046 pci_write_config_byte(dev, 0x92, val & ~0x06);
1047 }
1048}
1049
1050DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_ANY_ID, pmac_pci_fixup_cardbus);
1051
1052void pmac_pci_fixup_pciata(struct pci_dev* dev)
1053{
1054 u8 progif = 0;
1055
1056 /*
1057 * On PowerMacs, we try to switch any PCI ATA controller to
1058 * fully native mode
1059 */
1060 if (_machine != _MACH_Pmac)
1061 return;
1062 /* Some controllers don't have the class IDE */
1063 if (dev->vendor == PCI_VENDOR_ID_PROMISE)
1064 switch(dev->device) {
1065 case PCI_DEVICE_ID_PROMISE_20246:
1066 case PCI_DEVICE_ID_PROMISE_20262:
1067 case PCI_DEVICE_ID_PROMISE_20263:
1068 case PCI_DEVICE_ID_PROMISE_20265:
1069 case PCI_DEVICE_ID_PROMISE_20267:
1070 case PCI_DEVICE_ID_PROMISE_20268:
1071 case PCI_DEVICE_ID_PROMISE_20269:
1072 case PCI_DEVICE_ID_PROMISE_20270:
1073 case PCI_DEVICE_ID_PROMISE_20271:
1074 case PCI_DEVICE_ID_PROMISE_20275:
1075 case PCI_DEVICE_ID_PROMISE_20276:
1076 case PCI_DEVICE_ID_PROMISE_20277:
1077 goto good;
1078 }
1079 /* Others, check PCI class */
1080 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
1081 return;
1082 good:
1083 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1084 if ((progif & 5) != 5) {
1085 printk(KERN_INFO "Forcing PCI IDE into native mode: %s\n", pci_name(dev));
1086 (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5);
1087 if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) ||
1088 (progif & 5) != 5)
1089 printk(KERN_ERR "Rewrite of PROGIF failed !\n");
1090 }
1091}
1092DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pmac_pci_fixup_pciata);
1093
1094
1095/*
1096 * Disable second function on K2-SATA, it's broken
1097 * and disable IO BARs on first one
1098 */
1099void pmac_pci_fixup_k2_sata(struct pci_dev* dev)
1100{
1101 int i;
1102 u16 cmd;
1103
1104 if (PCI_FUNC(dev->devfn) > 0) {
1105 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1106 cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1107 pci_write_config_word(dev, PCI_COMMAND, cmd);
1108 for (i = 0; i < 6; i++) {
1109 dev->resource[i].start = dev->resource[i].end = 0;
1110 dev->resource[i].flags = 0;
1111 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 0);
1112 }
1113 } else {
1114 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1115 cmd &= ~PCI_COMMAND_IO;
1116 pci_write_config_word(dev, PCI_COMMAND, cmd);
1117 for (i = 0; i < 5; i++) {
1118 dev->resource[i].start = dev->resource[i].end = 0;
1119 dev->resource[i].flags = 0;
1120 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 0);
1121 }
1122 }
1123}
1124DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 0x0240, pmac_pci_fixup_k2_sata);
diff --git a/arch/ppc/platforms/pmac_pic.c b/arch/ppc/platforms/pmac_pic.c
deleted file mode 100644
index 4742bf60935..00000000000
--- a/arch/ppc/platforms/pmac_pic.c
+++ /dev/null
@@ -1,693 +0,0 @@
1/*
2 * Support for the interrupt controllers found on Power Macintosh,
3 * currently Apple's "Grand Central" interrupt controller in all
4 * it's incarnations. OpenPIC support used on newer machines is
5 * in a separate file
6 *
7 * Copyright (C) 1997 Paul Mackerras (paulus@cs.anu.edu.au)
8 *
9 * Maintained by Benjamin Herrenschmidt (benh@kernel.crashing.org)
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
15 *
16 */
17
18#include <linux/config.h>
19#include <linux/stddef.h>
20#include <linux/init.h>
21#include <linux/sched.h>
22#include <linux/signal.h>
23#include <linux/pci.h>
24#include <linux/interrupt.h>
25#include <linux/sysdev.h>
26#include <linux/adb.h>
27#include <linux/pmu.h>
28
29#include <asm/sections.h>
30#include <asm/io.h>
31#include <asm/smp.h>
32#include <asm/prom.h>
33#include <asm/pci-bridge.h>
34#include <asm/time.h>
35#include <asm/open_pic.h>
36#include <asm/xmon.h>
37#include <asm/pmac_feature.h>
38#include <asm/machdep.h>
39
40#include "pmac_pic.h"
41
42/*
43 * XXX this should be in xmon.h, but putting it there means xmon.h
44 * has to include <linux/interrupt.h> (to get irqreturn_t), which
45 * causes all sorts of problems. -- paulus
46 */
47extern irqreturn_t xmon_irq(int, void *, struct pt_regs *);
48
49struct pmac_irq_hw {
50 unsigned int event;
51 unsigned int enable;
52 unsigned int ack;
53 unsigned int level;
54};
55
56/* Default addresses */
57static volatile struct pmac_irq_hw *pmac_irq_hw[4] = {
58 (struct pmac_irq_hw *) 0xf3000020,
59 (struct pmac_irq_hw *) 0xf3000010,
60 (struct pmac_irq_hw *) 0xf4000020,
61 (struct pmac_irq_hw *) 0xf4000010,
62};
63
64#define GC_LEVEL_MASK 0x3ff00000
65#define OHARE_LEVEL_MASK 0x1ff00000
66#define HEATHROW_LEVEL_MASK 0x1ff00000
67
68static int max_irqs;
69static int max_real_irqs;
70static u32 level_mask[4];
71
72static DEFINE_SPINLOCK(pmac_pic_lock);
73
74
75#define GATWICK_IRQ_POOL_SIZE 10
76static struct interrupt_info gatwick_int_pool[GATWICK_IRQ_POOL_SIZE];
77
78#define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
79static unsigned long ppc_lost_interrupts[NR_MASK_WORDS];
80
81/*
82 * Mark an irq as "lost". This is only used on the pmac
83 * since it can lose interrupts (see pmac_set_irq_mask).
84 * -- Cort
85 */
86void
87__set_lost(unsigned long irq_nr, int nokick)
88{
89 if (!test_and_set_bit(irq_nr, ppc_lost_interrupts)) {
90 atomic_inc(&ppc_n_lost_interrupts);
91 if (!nokick)
92 set_dec(1);
93 }
94}
95
96static void
97pmac_mask_and_ack_irq(unsigned int irq_nr)
98{
99 unsigned long bit = 1UL << (irq_nr & 0x1f);
100 int i = irq_nr >> 5;
101 unsigned long flags;
102
103 if ((unsigned)irq_nr >= max_irqs)
104 return;
105
106 clear_bit(irq_nr, ppc_cached_irq_mask);
107 if (test_and_clear_bit(irq_nr, ppc_lost_interrupts))
108 atomic_dec(&ppc_n_lost_interrupts);
109 spin_lock_irqsave(&pmac_pic_lock, flags);
110 out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
111 out_le32(&pmac_irq_hw[i]->ack, bit);
112 do {
113 /* make sure ack gets to controller before we enable
114 interrupts */
115 mb();
116 } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
117 != (ppc_cached_irq_mask[i] & bit));
118 spin_unlock_irqrestore(&pmac_pic_lock, flags);
119}
120
121static void pmac_set_irq_mask(unsigned int irq_nr, int nokicklost)
122{
123 unsigned long bit = 1UL << (irq_nr & 0x1f);
124 int i = irq_nr >> 5;
125 unsigned long flags;
126
127 if ((unsigned)irq_nr >= max_irqs)
128 return;
129
130 spin_lock_irqsave(&pmac_pic_lock, flags);
131 /* enable unmasked interrupts */
132 out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
133
134 do {
135 /* make sure mask gets to controller before we
136 return to user */
137 mb();
138 } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
139 != (ppc_cached_irq_mask[i] & bit));
140
141 /*
142 * Unfortunately, setting the bit in the enable register
143 * when the device interrupt is already on *doesn't* set
144 * the bit in the flag register or request another interrupt.
145 */
146 if (bit & ppc_cached_irq_mask[i] & in_le32(&pmac_irq_hw[i]->level))
147 __set_lost((ulong)irq_nr, nokicklost);
148 spin_unlock_irqrestore(&pmac_pic_lock, flags);
149}
150
151/* When an irq gets requested for the first client, if it's an
152 * edge interrupt, we clear any previous one on the controller
153 */
154static unsigned int pmac_startup_irq(unsigned int irq_nr)
155{
156 unsigned long bit = 1UL << (irq_nr & 0x1f);
157 int i = irq_nr >> 5;
158
159 if ((irq_desc[irq_nr].status & IRQ_LEVEL) == 0)
160 out_le32(&pmac_irq_hw[i]->ack, bit);
161 set_bit(irq_nr, ppc_cached_irq_mask);
162 pmac_set_irq_mask(irq_nr, 0);
163
164 return 0;
165}
166
167static void pmac_mask_irq(unsigned int irq_nr)
168{
169 clear_bit(irq_nr, ppc_cached_irq_mask);
170 pmac_set_irq_mask(irq_nr, 0);
171 mb();
172}
173
174static void pmac_unmask_irq(unsigned int irq_nr)
175{
176 set_bit(irq_nr, ppc_cached_irq_mask);
177 pmac_set_irq_mask(irq_nr, 0);
178}
179
180static void pmac_end_irq(unsigned int irq_nr)
181{
182 if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))
183 && irq_desc[irq_nr].action) {
184 set_bit(irq_nr, ppc_cached_irq_mask);
185 pmac_set_irq_mask(irq_nr, 1);
186 }
187}
188
189
190struct hw_interrupt_type pmac_pic = {
191 .typename = " PMAC-PIC ",
192 .startup = pmac_startup_irq,
193 .enable = pmac_unmask_irq,
194 .disable = pmac_mask_irq,
195 .ack = pmac_mask_and_ack_irq,
196 .end = pmac_end_irq,
197};
198
199struct hw_interrupt_type gatwick_pic = {
200 .typename = " GATWICK ",
201 .startup = pmac_startup_irq,
202 .enable = pmac_unmask_irq,
203 .disable = pmac_mask_irq,
204 .ack = pmac_mask_and_ack_irq,
205 .end = pmac_end_irq,
206};
207
208static irqreturn_t gatwick_action(int cpl, void *dev_id, struct pt_regs *regs)
209{
210 int irq, bits;
211
212 for (irq = max_irqs; (irq -= 32) >= max_real_irqs; ) {
213 int i = irq >> 5;
214 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
215 /* We must read level interrupts from the level register */
216 bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]);
217 bits &= ppc_cached_irq_mask[i];
218 if (bits == 0)
219 continue;
220 irq += __ilog2(bits);
221 __do_IRQ(irq, regs);
222 return IRQ_HANDLED;
223 }
224 printk("gatwick irq not from gatwick pic\n");
225 return IRQ_NONE;
226}
227
228int
229pmac_get_irq(struct pt_regs *regs)
230{
231 int irq;
232 unsigned long bits = 0;
233
234#ifdef CONFIG_SMP
235 void psurge_smp_message_recv(struct pt_regs *);
236
237 /* IPI's are a hack on the powersurge -- Cort */
238 if ( smp_processor_id() != 0 ) {
239 psurge_smp_message_recv(regs);
240 return -2; /* ignore, already handled */
241 }
242#endif /* CONFIG_SMP */
243 for (irq = max_real_irqs; (irq -= 32) >= 0; ) {
244 int i = irq >> 5;
245 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
246 /* We must read level interrupts from the level register */
247 bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]);
248 bits &= ppc_cached_irq_mask[i];
249 if (bits == 0)
250 continue;
251 irq += __ilog2(bits);
252 break;
253 }
254
255 return irq;
256}
257
258/* This routine will fix some missing interrupt values in the device tree
259 * on the gatwick mac-io controller used by some PowerBooks
260 */
261static void __init
262pmac_fix_gatwick_interrupts(struct device_node *gw, int irq_base)
263{
264 struct device_node *node;
265 int count;
266
267 memset(gatwick_int_pool, 0, sizeof(gatwick_int_pool));
268 node = gw->child;
269 count = 0;
270 while(node)
271 {
272 /* Fix SCC */
273 if (strcasecmp(node->name, "escc") == 0)
274 if (node->child) {
275 if (node->child->n_intrs < 3) {
276 node->child->intrs = &gatwick_int_pool[count];
277 count += 3;
278 }
279 node->child->n_intrs = 3;
280 node->child->intrs[0].line = 15+irq_base;
281 node->child->intrs[1].line = 4+irq_base;
282 node->child->intrs[2].line = 5+irq_base;
283 printk(KERN_INFO "irq: fixed SCC on second controller (%d,%d,%d)\n",
284 node->child->intrs[0].line,
285 node->child->intrs[1].line,
286 node->child->intrs[2].line);
287 }
288 /* Fix media-bay & left SWIM */
289 if (strcasecmp(node->name, "media-bay") == 0) {
290 struct device_node* ya_node;
291
292 if (node->n_intrs == 0)
293 node->intrs = &gatwick_int_pool[count++];
294 node->n_intrs = 1;
295 node->intrs[0].line = 29+irq_base;
296 printk(KERN_INFO "irq: fixed media-bay on second controller (%d)\n",
297 node->intrs[0].line);
298
299 ya_node = node->child;
300 while(ya_node)
301 {
302 if (strcasecmp(ya_node->name, "floppy") == 0) {
303 if (ya_node->n_intrs < 2) {
304 ya_node->intrs = &gatwick_int_pool[count];
305 count += 2;
306 }
307 ya_node->n_intrs = 2;
308 ya_node->intrs[0].line = 19+irq_base;
309 ya_node->intrs[1].line = 1+irq_base;
310 printk(KERN_INFO "irq: fixed floppy on second controller (%d,%d)\n",
311 ya_node->intrs[0].line, ya_node->intrs[1].line);
312 }
313 if (strcasecmp(ya_node->name, "ata4") == 0) {
314 if (ya_node->n_intrs < 2) {
315 ya_node->intrs = &gatwick_int_pool[count];
316 count += 2;
317 }
318 ya_node->n_intrs = 2;
319 ya_node->intrs[0].line = 14+irq_base;
320 ya_node->intrs[1].line = 3+irq_base;
321 printk(KERN_INFO "irq: fixed ide on second controller (%d,%d)\n",
322 ya_node->intrs[0].line, ya_node->intrs[1].line);
323 }
324 ya_node = ya_node->sibling;
325 }
326 }
327 node = node->sibling;
328 }
329 if (count > 10) {
330 printk("WARNING !! Gatwick interrupt pool overflow\n");
331 printk(" GATWICK_IRQ_POOL_SIZE = %d\n", GATWICK_IRQ_POOL_SIZE);
332 printk(" requested = %d\n", count);
333 }
334}
335
336/*
337 * The PowerBook 3400/2400/3500 can have a combo ethernet/modem
338 * card which includes an ohare chip that acts as a second interrupt
339 * controller. If we find this second ohare, set it up and fix the
340 * interrupt value in the device tree for the ethernet chip.
341 */
342static int __init enable_second_ohare(void)
343{
344 unsigned char bus, devfn;
345 unsigned short cmd;
346 unsigned long addr;
347 struct device_node *irqctrler = find_devices("pci106b,7");
348 struct device_node *ether;
349
350 if (irqctrler == NULL || irqctrler->n_addrs <= 0)
351 return -1;
352 addr = (unsigned long) ioremap(irqctrler->addrs[0].address, 0x40);
353 pmac_irq_hw[1] = (volatile struct pmac_irq_hw *)(addr + 0x20);
354 max_irqs = 64;
355 if (pci_device_from_OF_node(irqctrler, &bus, &devfn) == 0) {
356 struct pci_controller* hose = pci_find_hose_for_OF_device(irqctrler);
357 if (!hose)
358 printk(KERN_ERR "Can't find PCI hose for OHare2 !\n");
359 else {
360 early_read_config_word(hose, bus, devfn, PCI_COMMAND, &cmd);
361 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
362 cmd &= ~PCI_COMMAND_IO;
363 early_write_config_word(hose, bus, devfn, PCI_COMMAND, cmd);
364 }
365 }
366
367 /* Fix interrupt for the modem/ethernet combo controller. The number
368 in the device tree (27) is bogus (correct for the ethernet-only
369 board but not the combo ethernet/modem board).
370 The real interrupt is 28 on the second controller -> 28+32 = 60.
371 */
372 ether = find_devices("pci1011,14");
373 if (ether && ether->n_intrs > 0) {
374 ether->intrs[0].line = 60;
375 printk(KERN_INFO "irq: Fixed ethernet IRQ to %d\n",
376 ether->intrs[0].line);
377 }
378
379 /* Return the interrupt number of the cascade */
380 return irqctrler->intrs[0].line;
381}
382
383#ifdef CONFIG_POWER4
384static irqreturn_t k2u3_action(int cpl, void *dev_id, struct pt_regs *regs)
385{
386 int irq;
387
388 irq = openpic2_get_irq(regs);
389 if (irq != -1)
390 __do_IRQ(irq, regs);
391 return IRQ_HANDLED;
392}
393
394static struct irqaction k2u3_cascade_action = {
395 .handler = k2u3_action,
396 .flags = 0,
397 .mask = CPU_MASK_NONE,
398 .name = "U3->K2 Cascade",
399};
400#endif /* CONFIG_POWER4 */
401
402#ifdef CONFIG_XMON
403static struct irqaction xmon_action = {
404 .handler = xmon_irq,
405 .flags = 0,
406 .mask = CPU_MASK_NONE,
407 .name = "NMI - XMON"
408};
409#endif
410
411static struct irqaction gatwick_cascade_action = {
412 .handler = gatwick_action,
413 .flags = SA_INTERRUPT,
414 .mask = CPU_MASK_NONE,
415 .name = "cascade",
416};
417
418void __init pmac_pic_init(void)
419{
420 int i;
421 struct device_node *irqctrler = NULL;
422 struct device_node *irqctrler2 = NULL;
423 struct device_node *np;
424 unsigned long addr;
425 int irq_cascade = -1;
426
427 /* We first try to detect Apple's new Core99 chipset, since mac-io
428 * is quite different on those machines and contains an IBM MPIC2.
429 */
430 np = find_type_devices("open-pic");
431 while(np) {
432 if (np->parent && !strcmp(np->parent->name, "u3"))
433 irqctrler2 = np;
434 else
435 irqctrler = np;
436 np = np->next;
437 }
438 if (irqctrler != NULL)
439 {
440 if (irqctrler->n_addrs > 0)
441 {
442 unsigned char senses[128];
443
444 printk(KERN_INFO "PowerMac using OpenPIC irq controller at 0x%08x\n",
445 irqctrler->addrs[0].address);
446
447 prom_get_irq_senses(senses, 0, 128);
448 OpenPIC_InitSenses = senses;
449 OpenPIC_NumInitSenses = 128;
450 ppc_md.get_irq = openpic_get_irq;
451 pmac_call_feature(PMAC_FTR_ENABLE_MPIC, irqctrler, 0, 0);
452 OpenPIC_Addr = ioremap(irqctrler->addrs[0].address,
453 irqctrler->addrs[0].size);
454 openpic_init(0);
455
456#ifdef CONFIG_POWER4
457 if (irqctrler2 != NULL && irqctrler2->n_intrs > 0 &&
458 irqctrler2->n_addrs > 0) {
459 printk(KERN_INFO "Slave OpenPIC at 0x%08x hooked on IRQ %d\n",
460 irqctrler2->addrs[0].address,
461 irqctrler2->intrs[0].line);
462 pmac_call_feature(PMAC_FTR_ENABLE_MPIC, irqctrler2, 0, 0);
463 OpenPIC2_Addr = ioremap(irqctrler2->addrs[0].address,
464 irqctrler2->addrs[0].size);
465 prom_get_irq_senses(senses, PMAC_OPENPIC2_OFFSET,
466 PMAC_OPENPIC2_OFFSET+128);
467 OpenPIC_InitSenses = senses;
468 OpenPIC_NumInitSenses = 128;
469 openpic2_init(PMAC_OPENPIC2_OFFSET);
470
471 if (setup_irq(irqctrler2->intrs[0].line,
472 &k2u3_cascade_action))
473 printk("Unable to get OpenPIC IRQ for cascade\n");
474 }
475#endif /* CONFIG_POWER4 */
476
477#ifdef CONFIG_XMON
478 {
479 struct device_node* pswitch;
480 int nmi_irq;
481
482 pswitch = find_devices("programmer-switch");
483 if (pswitch && pswitch->n_intrs) {
484 nmi_irq = pswitch->intrs[0].line;
485 openpic_init_nmi_irq(nmi_irq);
486 setup_irq(nmi_irq, &xmon_action);
487 }
488 }
489#endif /* CONFIG_XMON */
490 return;
491 }
492 irqctrler = NULL;
493 }
494
495 /* Get the level/edge settings, assume if it's not
496 * a Grand Central nor an OHare, then it's an Heathrow
497 * (or Paddington).
498 */
499 if (find_devices("gc"))
500 level_mask[0] = GC_LEVEL_MASK;
501 else if (find_devices("ohare")) {
502 level_mask[0] = OHARE_LEVEL_MASK;
503 /* We might have a second cascaded ohare */
504 level_mask[1] = OHARE_LEVEL_MASK;
505 } else {
506 level_mask[0] = HEATHROW_LEVEL_MASK;
507 level_mask[1] = 0;
508 /* We might have a second cascaded heathrow */
509 level_mask[2] = HEATHROW_LEVEL_MASK;
510 level_mask[3] = 0;
511 }
512
513 /*
514 * G3 powermacs and 1999 G3 PowerBooks have 64 interrupts,
515 * 1998 G3 Series PowerBooks have 128,
516 * other powermacs have 32.
517 * The combo ethernet/modem card for the Powerstar powerbooks
518 * (2400/3400/3500, ohare based) has a second ohare chip
519 * effectively making a total of 64.
520 */
521 max_irqs = max_real_irqs = 32;
522 irqctrler = find_devices("mac-io");
523 if (irqctrler)
524 {
525 max_real_irqs = 64;
526 if (irqctrler->next)
527 max_irqs = 128;
528 else
529 max_irqs = 64;
530 }
531 for ( i = 0; i < max_real_irqs ; i++ )
532 irq_desc[i].handler = &pmac_pic;
533
534 /* get addresses of first controller */
535 if (irqctrler) {
536 if (irqctrler->n_addrs > 0) {
537 addr = (unsigned long)
538 ioremap(irqctrler->addrs[0].address, 0x40);
539 for (i = 0; i < 2; ++i)
540 pmac_irq_hw[i] = (volatile struct pmac_irq_hw*)
541 (addr + (2 - i) * 0x10);
542 }
543
544 /* get addresses of second controller */
545 irqctrler = irqctrler->next;
546 if (irqctrler && irqctrler->n_addrs > 0) {
547 addr = (unsigned long)
548 ioremap(irqctrler->addrs[0].address, 0x40);
549 for (i = 2; i < 4; ++i)
550 pmac_irq_hw[i] = (volatile struct pmac_irq_hw*)
551 (addr + (4 - i) * 0x10);
552 irq_cascade = irqctrler->intrs[0].line;
553 if (device_is_compatible(irqctrler, "gatwick"))
554 pmac_fix_gatwick_interrupts(irqctrler, max_real_irqs);
555 }
556 } else {
557 /* older powermacs have a GC (grand central) or ohare at
558 f3000000, with interrupt control registers at f3000020. */
559 addr = (unsigned long) ioremap(0xf3000000, 0x40);
560 pmac_irq_hw[0] = (volatile struct pmac_irq_hw *) (addr + 0x20);
561 }
562
563 /* PowerBooks 3400 and 3500 can have a second controller in a second
564 ohare chip, on the combo ethernet/modem card */
565 if (machine_is_compatible("AAPL,3400/2400")
566 || machine_is_compatible("AAPL,3500"))
567 irq_cascade = enable_second_ohare();
568
569 /* disable all interrupts in all controllers */
570 for (i = 0; i * 32 < max_irqs; ++i)
571 out_le32(&pmac_irq_hw[i]->enable, 0);
572 /* mark level interrupts */
573 for (i = 0; i < max_irqs; i++)
574 if (level_mask[i >> 5] & (1UL << (i & 0x1f)))
575 irq_desc[i].status = IRQ_LEVEL;
576
577 /* get interrupt line of secondary interrupt controller */
578 if (irq_cascade >= 0) {
579 printk(KERN_INFO "irq: secondary controller on irq %d\n",
580 (int)irq_cascade);
581 for ( i = max_real_irqs ; i < max_irqs ; i++ )
582 irq_desc[i].handler = &gatwick_pic;
583 setup_irq(irq_cascade, &gatwick_cascade_action);
584 }
585 printk("System has %d possible interrupts\n", max_irqs);
586 if (max_irqs != max_real_irqs)
587 printk(KERN_DEBUG "%d interrupts on main controller\n",
588 max_real_irqs);
589
590#ifdef CONFIG_XMON
591 setup_irq(20, &xmon_action);
592#endif /* CONFIG_XMON */
593}
594
595#ifdef CONFIG_PM
596/*
597 * These procedures are used in implementing sleep on the powerbooks.
598 * sleep_save_intrs() saves the states of all interrupt enables
599 * and disables all interrupts except for the nominated one.
600 * sleep_restore_intrs() restores the states of all interrupt enables.
601 */
602unsigned long sleep_save_mask[2];
603
604/* This used to be passed by the PMU driver but that link got
605 * broken with the new driver model. We use this tweak for now...
606 */
607static int pmacpic_find_viaint(void)
608{
609 int viaint = -1;
610
611#ifdef CONFIG_ADB_PMU
612 struct device_node *np;
613
614 if (pmu_get_model() != PMU_OHARE_BASED)
615 goto not_found;
616 np = of_find_node_by_name(NULL, "via-pmu");
617 if (np == NULL)
618 goto not_found;
619 viaint = np->intrs[0].line;
620#endif /* CONFIG_ADB_PMU */
621
622not_found:
623 return viaint;
624}
625
626static int pmacpic_suspend(struct sys_device *sysdev, pm_message_t state)
627{
628 int viaint = pmacpic_find_viaint();
629
630 sleep_save_mask[0] = ppc_cached_irq_mask[0];
631 sleep_save_mask[1] = ppc_cached_irq_mask[1];
632 ppc_cached_irq_mask[0] = 0;
633 ppc_cached_irq_mask[1] = 0;
634 if (viaint > 0)
635 set_bit(viaint, ppc_cached_irq_mask);
636 out_le32(&pmac_irq_hw[0]->enable, ppc_cached_irq_mask[0]);
637 if (max_real_irqs > 32)
638 out_le32(&pmac_irq_hw[1]->enable, ppc_cached_irq_mask[1]);
639 (void)in_le32(&pmac_irq_hw[0]->event);
640 /* make sure mask gets to controller before we return to caller */
641 mb();
642 (void)in_le32(&pmac_irq_hw[0]->enable);
643
644 return 0;
645}
646
647static int pmacpic_resume(struct sys_device *sysdev)
648{
649 int i;
650
651 out_le32(&pmac_irq_hw[0]->enable, 0);
652 if (max_real_irqs > 32)
653 out_le32(&pmac_irq_hw[1]->enable, 0);
654 mb();
655 for (i = 0; i < max_real_irqs; ++i)
656 if (test_bit(i, sleep_save_mask))
657 pmac_unmask_irq(i);
658
659 return 0;
660}
661
662#endif /* CONFIG_PM */
663
664static struct sysdev_class pmacpic_sysclass = {
665 set_kset_name("pmac_pic"),
666};
667
668static struct sys_device device_pmacpic = {
669 .id = 0,
670 .cls = &pmacpic_sysclass,
671};
672
673static struct sysdev_driver driver_pmacpic = {
674#ifdef CONFIG_PM
675 .suspend = &pmacpic_suspend,
676 .resume = &pmacpic_resume,
677#endif /* CONFIG_PM */
678};
679
680static int __init init_pmacpic_sysfs(void)
681{
682 if (max_irqs == 0)
683 return -ENODEV;
684
685 printk(KERN_DEBUG "Registering pmac pic with sysfs...\n");
686 sysdev_class_register(&pmacpic_sysclass);
687 sysdev_register(&device_pmacpic);
688 sysdev_driver_register(&pmacpic_sysclass, &driver_pmacpic);
689 return 0;
690}
691
692subsys_initcall(init_pmacpic_sysfs);
693
diff --git a/arch/ppc/platforms/pmac_pic.h b/arch/ppc/platforms/pmac_pic.h
deleted file mode 100644
index 664103dfeef..00000000000
--- a/arch/ppc/platforms/pmac_pic.h
+++ /dev/null
@@ -1,11 +0,0 @@
1#ifndef __PPC_PLATFORMS_PMAC_PIC_H
2#define __PPC_PLATFORMS_PMAC_PIC_H
3
4#include <linux/irq.h>
5
6extern struct hw_interrupt_type pmac_pic;
7
8void pmac_pic_init(void);
9int pmac_get_irq(struct pt_regs *regs);
10
11#endif /* __PPC_PLATFORMS_PMAC_PIC_H */
diff --git a/arch/ppc/platforms/pmac_setup.c b/arch/ppc/platforms/pmac_setup.c
deleted file mode 100644
index 55d2beffe56..00000000000
--- a/arch/ppc/platforms/pmac_setup.c
+++ /dev/null
@@ -1,745 +0,0 @@
1/*
2 * arch/ppc/platforms/setup.c
3 *
4 * PowerPC version
5 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
6 *
7 * Adapted for Power Macintosh by Paul Mackerras
8 * Copyright (C) 1996 Paul Mackerras (paulus@cs.anu.edu.au)
9 *
10 * Derived from "arch/alpha/kernel/setup.c"
11 * Copyright (C) 1995 Linus Torvalds
12 *
13 * Maintained by Benjamin Herrenschmidt (benh@kernel.crashing.org)
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
19 *
20 */
21
22/*
23 * bootup setup stuff..
24 */
25
26#include <linux/config.h>
27#include <linux/init.h>
28#include <linux/errno.h>
29#include <linux/sched.h>
30#include <linux/kernel.h>
31#include <linux/mm.h>
32#include <linux/stddef.h>
33#include <linux/unistd.h>
34#include <linux/ptrace.h>
35#include <linux/slab.h>
36#include <linux/user.h>
37#include <linux/a.out.h>
38#include <linux/tty.h>
39#include <linux/string.h>
40#include <linux/delay.h>
41#include <linux/ioport.h>
42#include <linux/major.h>
43#include <linux/initrd.h>
44#include <linux/vt_kern.h>
45#include <linux/console.h>
46#include <linux/ide.h>
47#include <linux/pci.h>
48#include <linux/adb.h>
49#include <linux/cuda.h>
50#include <linux/pmu.h>
51#include <linux/seq_file.h>
52#include <linux/root_dev.h>
53#include <linux/bitops.h>
54#include <linux/suspend.h>
55
56#include <asm/reg.h>
57#include <asm/sections.h>
58#include <asm/prom.h>
59#include <asm/system.h>
60#include <asm/pgtable.h>
61#include <asm/io.h>
62#include <asm/pci-bridge.h>
63#include <asm/ohare.h>
64#include <asm/mediabay.h>
65#include <asm/machdep.h>
66#include <asm/dma.h>
67#include <asm/bootx.h>
68#include <asm/cputable.h>
69#include <asm/btext.h>
70#include <asm/pmac_feature.h>
71#include <asm/time.h>
72#include <asm/of_device.h>
73#include <asm/mmu_context.h>
74
75#include "pmac_pic.h"
76#include "mem_pieces.h"
77
78#undef SHOW_GATWICK_IRQS
79
80extern long pmac_time_init(void);
81extern unsigned long pmac_get_rtc_time(void);
82extern int pmac_set_rtc_time(unsigned long nowtime);
83extern void pmac_read_rtc_time(void);
84extern void pmac_calibrate_decr(void);
85extern void pmac_pcibios_fixup(void);
86extern void pmac_find_bridges(void);
87extern unsigned long pmac_ide_get_base(int index);
88extern void pmac_ide_init_hwif_ports(hw_regs_t *hw,
89 unsigned long data_port, unsigned long ctrl_port, int *irq);
90
91extern void pmac_nvram_update(void);
92extern unsigned char pmac_nvram_read_byte(int addr);
93extern void pmac_nvram_write_byte(int addr, unsigned char val);
94extern int pmac_pci_enable_device_hook(struct pci_dev *dev, int initial);
95extern void pmac_pcibios_after_init(void);
96extern int of_show_percpuinfo(struct seq_file *m, int i);
97
98struct device_node *memory_node;
99
100unsigned char drive_info;
101
102int ppc_override_l2cr = 0;
103int ppc_override_l2cr_value;
104int has_l2cache = 0;
105
106static int current_root_goodness = -1;
107
108extern int pmac_newworld;
109
110#define DEFAULT_ROOT_DEVICE Root_SDA1 /* sda1 - slightly silly choice */
111
112extern void zs_kgdb_hook(int tty_num);
113static void ohare_init(void);
114#ifdef CONFIG_BOOTX_TEXT
115static void pmac_progress(char *s, unsigned short hex);
116#endif
117
118sys_ctrler_t sys_ctrler = SYS_CTRLER_UNKNOWN;
119
120#ifdef CONFIG_SMP
121extern struct smp_ops_t psurge_smp_ops;
122extern struct smp_ops_t core99_smp_ops;
123#endif /* CONFIG_SMP */
124
125static int
126pmac_show_cpuinfo(struct seq_file *m)
127{
128 struct device_node *np;
129 char *pp;
130 int plen;
131 int mbmodel = pmac_call_feature(PMAC_FTR_GET_MB_INFO,
132 NULL, PMAC_MB_INFO_MODEL, 0);
133 unsigned int mbflags = (unsigned int)pmac_call_feature(PMAC_FTR_GET_MB_INFO,
134 NULL, PMAC_MB_INFO_FLAGS, 0);
135 char* mbname;
136
137 if (pmac_call_feature(PMAC_FTR_GET_MB_INFO, NULL, PMAC_MB_INFO_NAME, (int)&mbname) != 0)
138 mbname = "Unknown";
139
140 /* find motherboard type */
141 seq_printf(m, "machine\t\t: ");
142 np = find_devices("device-tree");
143 if (np != NULL) {
144 pp = (char *) get_property(np, "model", NULL);
145 if (pp != NULL)
146 seq_printf(m, "%s\n", pp);
147 else
148 seq_printf(m, "PowerMac\n");
149 pp = (char *) get_property(np, "compatible", &plen);
150 if (pp != NULL) {
151 seq_printf(m, "motherboard\t:");
152 while (plen > 0) {
153 int l = strlen(pp) + 1;
154 seq_printf(m, " %s", pp);
155 plen -= l;
156 pp += l;
157 }
158 seq_printf(m, "\n");
159 }
160 } else
161 seq_printf(m, "PowerMac\n");
162
163 /* print parsed model */
164 seq_printf(m, "detected as\t: %d (%s)\n", mbmodel, mbname);
165 seq_printf(m, "pmac flags\t: %08x\n", mbflags);
166
167 /* find l2 cache info */
168 np = find_devices("l2-cache");
169 if (np == 0)
170 np = find_type_devices("cache");
171 if (np != 0) {
172 unsigned int *ic = (unsigned int *)
173 get_property(np, "i-cache-size", NULL);
174 unsigned int *dc = (unsigned int *)
175 get_property(np, "d-cache-size", NULL);
176 seq_printf(m, "L2 cache\t:");
177 has_l2cache = 1;
178 if (get_property(np, "cache-unified", NULL) != 0 && dc) {
179 seq_printf(m, " %dK unified", *dc / 1024);
180 } else {
181 if (ic)
182 seq_printf(m, " %dK instruction", *ic / 1024);
183 if (dc)
184 seq_printf(m, "%s %dK data",
185 (ic? " +": ""), *dc / 1024);
186 }
187 pp = get_property(np, "ram-type", NULL);
188 if (pp)
189 seq_printf(m, " %s", pp);
190 seq_printf(m, "\n");
191 }
192
193 /* find ram info */
194 np = find_devices("memory");
195 if (np != 0) {
196 int n;
197 struct reg_property *reg = (struct reg_property *)
198 get_property(np, "reg", &n);
199
200 if (reg != 0) {
201 unsigned long total = 0;
202
203 for (n /= sizeof(struct reg_property); n > 0; --n)
204 total += (reg++)->size;
205 seq_printf(m, "memory\t\t: %luMB\n", total >> 20);
206 }
207 }
208
209 /* Checks "l2cr-value" property in the registry */
210 np = find_devices("cpus");
211 if (np == 0)
212 np = find_type_devices("cpu");
213 if (np != 0) {
214 unsigned int *l2cr = (unsigned int *)
215 get_property(np, "l2cr-value", NULL);
216 if (l2cr != 0) {
217 seq_printf(m, "l2cr override\t: 0x%x\n", *l2cr);
218 }
219 }
220
221 /* Indicate newworld/oldworld */
222 seq_printf(m, "pmac-generation\t: %s\n",
223 pmac_newworld ? "NewWorld" : "OldWorld");
224
225
226 return 0;
227}
228
229static int
230pmac_show_percpuinfo(struct seq_file *m, int i)
231{
232#ifdef CONFIG_CPU_FREQ_PMAC
233 extern unsigned int pmac_get_one_cpufreq(int i);
234 unsigned int freq = pmac_get_one_cpufreq(i);
235 if (freq != 0) {
236 seq_printf(m, "clock\t\t: %dMHz\n", freq/1000);
237 return 0;
238 }
239#endif /* CONFIG_CPU_FREQ_PMAC */
240 return of_show_percpuinfo(m, i);
241}
242
243static volatile u32 *sysctrl_regs;
244
245void __init
246pmac_setup_arch(void)
247{
248 struct device_node *cpu;
249 int *fp;
250 unsigned long pvr;
251
252 pvr = PVR_VER(mfspr(SPRN_PVR));
253
254 /* Set loops_per_jiffy to a half-way reasonable value,
255 for use until calibrate_delay gets called. */
256 cpu = find_type_devices("cpu");
257 if (cpu != 0) {
258 fp = (int *) get_property(cpu, "clock-frequency", NULL);
259 if (fp != 0) {
260 if (pvr == 4 || pvr >= 8)
261 /* 604, G3, G4 etc. */
262 loops_per_jiffy = *fp / HZ;
263 else
264 /* 601, 603, etc. */
265 loops_per_jiffy = *fp / (2*HZ);
266 } else
267 loops_per_jiffy = 50000000 / HZ;
268 }
269
270 /* this area has the CPU identification register
271 and some registers used by smp boards */
272 sysctrl_regs = (volatile u32 *) ioremap(0xf8000000, 0x1000);
273 ohare_init();
274
275 /* Lookup PCI hosts */
276 pmac_find_bridges();
277
278 /* Checks "l2cr-value" property in the registry */
279 if (cpu_has_feature(CPU_FTR_L2CR)) {
280 struct device_node *np = find_devices("cpus");
281 if (np == 0)
282 np = find_type_devices("cpu");
283 if (np != 0) {
284 unsigned int *l2cr = (unsigned int *)
285 get_property(np, "l2cr-value", NULL);
286 if (l2cr != 0) {
287 ppc_override_l2cr = 1;
288 ppc_override_l2cr_value = *l2cr;
289 _set_L2CR(0);
290 _set_L2CR(ppc_override_l2cr_value);
291 }
292 }
293 }
294
295 if (ppc_override_l2cr)
296 printk(KERN_INFO "L2CR overriden (0x%x), backside cache is %s\n",
297 ppc_override_l2cr_value, (ppc_override_l2cr_value & 0x80000000)
298 ? "enabled" : "disabled");
299
300#ifdef CONFIG_KGDB
301 zs_kgdb_hook(0);
302#endif
303
304#ifdef CONFIG_ADB_CUDA
305 find_via_cuda();
306#else
307 if (find_devices("via-cuda")) {
308 printk("WARNING ! Your machine is Cuda based but your kernel\n");
309 printk(" wasn't compiled with CONFIG_ADB_CUDA option !\n");
310 }
311#endif
312#ifdef CONFIG_ADB_PMU
313 find_via_pmu();
314#else
315 if (find_devices("via-pmu")) {
316 printk("WARNING ! Your machine is PMU based but your kernel\n");
317 printk(" wasn't compiled with CONFIG_ADB_PMU option !\n");
318 }
319#endif
320#ifdef CONFIG_NVRAM
321 pmac_nvram_init();
322#endif
323#ifdef CONFIG_BLK_DEV_INITRD
324 if (initrd_start)
325 ROOT_DEV = Root_RAM0;
326 else
327#endif
328 ROOT_DEV = DEFAULT_ROOT_DEVICE;
329
330#ifdef CONFIG_SMP
331 /* Check for Core99 */
332 if (find_devices("uni-n") || find_devices("u3"))
333 smp_ops = &core99_smp_ops;
334 else
335 smp_ops = &psurge_smp_ops;
336#endif /* CONFIG_SMP */
337
338 pci_create_OF_bus_map();
339}
340
341static void __init ohare_init(void)
342{
343 /*
344 * Turn on the L2 cache.
345 * We assume that we have a PSX memory controller iff
346 * we have an ohare I/O controller.
347 */
348 if (find_devices("ohare") != NULL) {
349 if (((sysctrl_regs[2] >> 24) & 0xf) >= 3) {
350 if (sysctrl_regs[4] & 0x10)
351 sysctrl_regs[4] |= 0x04000020;
352 else
353 sysctrl_regs[4] |= 0x04000000;
354 if(has_l2cache)
355 printk(KERN_INFO "Level 2 cache enabled\n");
356 }
357 }
358}
359
360extern char *bootpath;
361extern char *bootdevice;
362void *boot_host;
363int boot_target;
364int boot_part;
365extern dev_t boot_dev;
366
367#ifdef CONFIG_SCSI
368void __init
369note_scsi_host(struct device_node *node, void *host)
370{
371 int l;
372 char *p;
373
374 l = strlen(node->full_name);
375 if (bootpath != NULL && bootdevice != NULL
376 && strncmp(node->full_name, bootdevice, l) == 0
377 && (bootdevice[l] == '/' || bootdevice[l] == 0)) {
378 boot_host = host;
379 /*
380 * There's a bug in OF 1.0.5. (Why am I not surprised.)
381 * If you pass a path like scsi/sd@1:0 to canon, it returns
382 * something like /bandit@F2000000/gc@10/53c94@10000/sd@0,0
383 * That is, the scsi target number doesn't get preserved.
384 * So we pick the target number out of bootpath and use that.
385 */
386 p = strstr(bootpath, "/sd@");
387 if (p != NULL) {
388 p += 4;
389 boot_target = simple_strtoul(p, NULL, 10);
390 p = strchr(p, ':');
391 if (p != NULL)
392 boot_part = simple_strtoul(p + 1, NULL, 10);
393 }
394 }
395}
396#endif
397
398#if defined(CONFIG_BLK_DEV_IDE) && defined(CONFIG_BLK_DEV_IDE_PMAC)
399static dev_t __init
400find_ide_boot(void)
401{
402 char *p;
403 int n;
404 dev_t __init pmac_find_ide_boot(char *bootdevice, int n);
405
406 if (bootdevice == NULL)
407 return 0;
408 p = strrchr(bootdevice, '/');
409 if (p == NULL)
410 return 0;
411 n = p - bootdevice;
412
413 return pmac_find_ide_boot(bootdevice, n);
414}
415#endif /* CONFIG_BLK_DEV_IDE && CONFIG_BLK_DEV_IDE_PMAC */
416
417static void __init
418find_boot_device(void)
419{
420#if defined(CONFIG_BLK_DEV_IDE) && defined(CONFIG_BLK_DEV_IDE_PMAC)
421 boot_dev = find_ide_boot();
422#endif
423}
424
425static int initializing = 1;
426/* TODO: Merge the suspend-to-ram with the common code !!!
427 * currently, this is a stub implementation for suspend-to-disk
428 * only
429 */
430
431#ifdef CONFIG_SOFTWARE_SUSPEND
432
433static int pmac_pm_prepare(suspend_state_t state)
434{
435 printk(KERN_DEBUG "%s(%d)\n", __FUNCTION__, state);
436
437 return 0;
438}
439
440static int pmac_pm_enter(suspend_state_t state)
441{
442 printk(KERN_DEBUG "%s(%d)\n", __FUNCTION__, state);
443
444 /* Giveup the lazy FPU & vec so we don't have to back them
445 * up from the low level code
446 */
447 enable_kernel_fp();
448
449#ifdef CONFIG_ALTIVEC
450 if (cur_cpu_spec->cpu_features & CPU_FTR_ALTIVEC)
451 enable_kernel_altivec();
452#endif /* CONFIG_ALTIVEC */
453
454 return 0;
455}
456
457static int pmac_pm_finish(suspend_state_t state)
458{
459 printk(KERN_DEBUG "%s(%d)\n", __FUNCTION__, state);
460
461 /* Restore userland MMU context */
462 set_context(current->active_mm->context, current->active_mm->pgd);
463
464 return 0;
465}
466
467static struct pm_ops pmac_pm_ops = {
468 .pm_disk_mode = PM_DISK_SHUTDOWN,
469 .prepare = pmac_pm_prepare,
470 .enter = pmac_pm_enter,
471 .finish = pmac_pm_finish,
472};
473
474#endif /* CONFIG_SOFTWARE_SUSPEND */
475
476static int pmac_late_init(void)
477{
478 initializing = 0;
479#ifdef CONFIG_SOFTWARE_SUSPEND
480 pm_set_ops(&pmac_pm_ops);
481#endif /* CONFIG_SOFTWARE_SUSPEND */
482 return 0;
483}
484
485late_initcall(pmac_late_init);
486
487/* can't be __init - can be called whenever a disk is first accessed */
488void
489note_bootable_part(dev_t dev, int part, int goodness)
490{
491 static int found_boot = 0;
492 char *p;
493
494 if (!initializing)
495 return;
496 if ((goodness <= current_root_goodness) &&
497 ROOT_DEV != DEFAULT_ROOT_DEVICE)
498 return;
499 p = strstr(saved_command_line, "root=");
500 if (p != NULL && (p == saved_command_line || p[-1] == ' '))
501 return;
502
503 if (!found_boot) {
504 find_boot_device();
505 found_boot = 1;
506 }
507 if (!boot_dev || dev == boot_dev) {
508 ROOT_DEV = dev + part;
509 boot_dev = 0;
510 current_root_goodness = goodness;
511 }
512}
513
514static void
515pmac_restart(char *cmd)
516{
517#ifdef CONFIG_ADB_CUDA
518 struct adb_request req;
519#endif /* CONFIG_ADB_CUDA */
520
521 switch (sys_ctrler) {
522#ifdef CONFIG_ADB_CUDA
523 case SYS_CTRLER_CUDA:
524 cuda_request(&req, NULL, 2, CUDA_PACKET,
525 CUDA_RESET_SYSTEM);
526 for (;;)
527 cuda_poll();
528 break;
529#endif /* CONFIG_ADB_CUDA */
530#ifdef CONFIG_ADB_PMU
531 case SYS_CTRLER_PMU:
532 pmu_restart();
533 break;
534#endif /* CONFIG_ADB_PMU */
535 default: ;
536 }
537}
538
539static void
540pmac_power_off(void)
541{
542#ifdef CONFIG_ADB_CUDA
543 struct adb_request req;
544#endif /* CONFIG_ADB_CUDA */
545
546 switch (sys_ctrler) {
547#ifdef CONFIG_ADB_CUDA
548 case SYS_CTRLER_CUDA:
549 cuda_request(&req, NULL, 2, CUDA_PACKET,
550 CUDA_POWERDOWN);
551 for (;;)
552 cuda_poll();
553 break;
554#endif /* CONFIG_ADB_CUDA */
555#ifdef CONFIG_ADB_PMU
556 case SYS_CTRLER_PMU:
557 pmu_shutdown();
558 break;
559#endif /* CONFIG_ADB_PMU */
560 default: ;
561 }
562}
563
564static void
565pmac_halt(void)
566{
567 pmac_power_off();
568}
569
570/*
571 * Read in a property describing some pieces of memory.
572 */
573
574static int __init
575get_mem_prop(char *name, struct mem_pieces *mp)
576{
577 struct reg_property *rp;
578 int i, s;
579 unsigned int *ip;
580 int nac = prom_n_addr_cells(memory_node);
581 int nsc = prom_n_size_cells(memory_node);
582
583 ip = (unsigned int *) get_property(memory_node, name, &s);
584 if (ip == NULL) {
585 printk(KERN_ERR "error: couldn't get %s property on /memory\n",
586 name);
587 return 0;
588 }
589 s /= (nsc + nac) * 4;
590 rp = mp->regions;
591 for (i = 0; i < s; ++i, ip += nac+nsc) {
592 if (nac >= 2 && ip[nac-2] != 0)
593 continue;
594 rp->address = ip[nac-1];
595 if (nsc >= 2 && ip[nac+nsc-2] != 0)
596 rp->size = ~0U;
597 else
598 rp->size = ip[nac+nsc-1];
599 ++rp;
600 }
601 mp->n_regions = rp - mp->regions;
602
603 /* Make sure the pieces are sorted. */
604 mem_pieces_sort(mp);
605 mem_pieces_coalesce(mp);
606 return 1;
607}
608
609/*
610 * On systems with Open Firmware, collect information about
611 * physical RAM and which pieces are already in use.
612 * At this point, we have (at least) the first 8MB mapped with a BAT.
613 * Our text, data, bss use something over 1MB, starting at 0.
614 * Open Firmware may be using 1MB at the 4MB point.
615 */
616unsigned long __init
617pmac_find_end_of_memory(void)
618{
619 unsigned long a, total;
620 struct mem_pieces phys_mem;
621
622 /*
623 * Find out where physical memory is, and check that it
624 * starts at 0 and is contiguous. It seems that RAM is
625 * always physically contiguous on Power Macintoshes.
626 *
627 * Supporting discontiguous physical memory isn't hard,
628 * it just makes the virtual <-> physical mapping functions
629 * more complicated (or else you end up wasting space
630 * in mem_map).
631 */
632 memory_node = find_devices("memory");
633 if (memory_node == NULL || !get_mem_prop("reg", &phys_mem)
634 || phys_mem.n_regions == 0)
635 panic("No RAM??");
636 a = phys_mem.regions[0].address;
637 if (a != 0)
638 panic("RAM doesn't start at physical address 0");
639 total = phys_mem.regions[0].size;
640
641 if (phys_mem.n_regions > 1) {
642 printk("RAM starting at 0x%x is not contiguous\n",
643 phys_mem.regions[1].address);
644 printk("Using RAM from 0 to 0x%lx\n", total-1);
645 }
646
647 return total;
648}
649
650void __init
651pmac_init(unsigned long r3, unsigned long r4, unsigned long r5,
652 unsigned long r6, unsigned long r7)
653{
654 /* isa_io_base gets set in pmac_find_bridges */
655 isa_mem_base = PMAC_ISA_MEM_BASE;
656 pci_dram_offset = PMAC_PCI_DRAM_OFFSET;
657 ISA_DMA_THRESHOLD = ~0L;
658 DMA_MODE_READ = 1;
659 DMA_MODE_WRITE = 2;
660
661 ppc_md.setup_arch = pmac_setup_arch;
662 ppc_md.show_cpuinfo = pmac_show_cpuinfo;
663 ppc_md.show_percpuinfo = pmac_show_percpuinfo;
664 ppc_md.init_IRQ = pmac_pic_init;
665 ppc_md.get_irq = pmac_get_irq; /* Changed later on ... */
666
667 ppc_md.pcibios_fixup = pmac_pcibios_fixup;
668 ppc_md.pcibios_enable_device_hook = pmac_pci_enable_device_hook;
669 ppc_md.pcibios_after_init = pmac_pcibios_after_init;
670 ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
671
672 ppc_md.restart = pmac_restart;
673 ppc_md.power_off = pmac_power_off;
674 ppc_md.halt = pmac_halt;
675
676 ppc_md.time_init = pmac_time_init;
677 ppc_md.set_rtc_time = pmac_set_rtc_time;
678 ppc_md.get_rtc_time = pmac_get_rtc_time;
679 ppc_md.calibrate_decr = pmac_calibrate_decr;
680
681 ppc_md.find_end_of_memory = pmac_find_end_of_memory;
682
683 ppc_md.feature_call = pmac_do_feature_call;
684
685#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
686#ifdef CONFIG_BLK_DEV_IDE_PMAC
687 ppc_ide_md.ide_init_hwif = pmac_ide_init_hwif_ports;
688 ppc_ide_md.default_io_base = pmac_ide_get_base;
689#endif /* CONFIG_BLK_DEV_IDE_PMAC */
690#endif /* defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE) */
691
692#ifdef CONFIG_BOOTX_TEXT
693 ppc_md.progress = pmac_progress;
694#endif /* CONFIG_BOOTX_TEXT */
695
696 if (ppc_md.progress) ppc_md.progress("pmac_init(): exit", 0);
697
698}
699
700#ifdef CONFIG_BOOTX_TEXT
701static void __init
702pmac_progress(char *s, unsigned short hex)
703{
704 if (boot_text_mapped) {
705 btext_drawstring(s);
706 btext_drawchar('\n');
707 }
708}
709#endif /* CONFIG_BOOTX_TEXT */
710
711static int __init
712pmac_declare_of_platform_devices(void)
713{
714 struct device_node *np;
715
716 np = find_devices("uni-n");
717 if (np) {
718 for (np = np->child; np != NULL; np = np->sibling)
719 if (strncmp(np->name, "i2c", 3) == 0) {
720 of_platform_device_create(np, "uni-n-i2c",
721 NULL);
722 break;
723 }
724 }
725 np = find_devices("u3");
726 if (np) {
727 for (np = np->child; np != NULL; np = np->sibling)
728 if (strncmp(np->name, "i2c", 3) == 0) {
729 of_platform_device_create(np, "u3-i2c",
730 NULL);
731 break;
732 }
733 }
734
735 np = find_devices("valkyrie");
736 if (np)
737 of_platform_device_create(np, "valkyrie", NULL);
738 np = find_devices("platinum");
739 if (np)
740 of_platform_device_create(np, "platinum", NULL);
741
742 return 0;
743}
744
745device_initcall(pmac_declare_of_platform_devices);
diff --git a/arch/ppc/platforms/pmac_sleep.S b/arch/ppc/platforms/pmac_sleep.S
deleted file mode 100644
index 22b113d19b2..00000000000
--- a/arch/ppc/platforms/pmac_sleep.S
+++ /dev/null
@@ -1,396 +0,0 @@
1/*
2 * This file contains sleep low-level functions for PowerBook G3.
3 * Copyright (C) 1999 Benjamin Herrenschmidt (benh@kernel.crashing.org)
4 * and Paul Mackerras (paulus@samba.org).
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 */
12
13#include <linux/config.h>
14#include <asm/processor.h>
15#include <asm/page.h>
16#include <asm/ppc_asm.h>
17#include <asm/cputable.h>
18#include <asm/cache.h>
19#include <asm/thread_info.h>
20#include <asm/asm-offsets.h>
21
22#define MAGIC 0x4c617273 /* 'Lars' */
23
24/*
25 * Structure for storing CPU registers on the stack.
26 */
27#define SL_SP 0
28#define SL_PC 4
29#define SL_MSR 8
30#define SL_SDR1 0xc
31#define SL_SPRG0 0x10 /* 4 sprg's */
32#define SL_DBAT0 0x20
33#define SL_IBAT0 0x28
34#define SL_DBAT1 0x30
35#define SL_IBAT1 0x38
36#define SL_DBAT2 0x40
37#define SL_IBAT2 0x48
38#define SL_DBAT3 0x50
39#define SL_IBAT3 0x58
40#define SL_TB 0x60
41#define SL_R2 0x68
42#define SL_CR 0x6c
43#define SL_R12 0x70 /* r12 to r31 */
44#define SL_SIZE (SL_R12 + 80)
45
46 .section .text
47 .align 5
48
49#if defined(CONFIG_PM) || defined(CONFIG_CPU_FREQ_PMAC)
50
51/* This gets called by via-pmu.c late during the sleep process.
52 * The PMU was already send the sleep command and will shut us down
53 * soon. We need to save all that is needed and setup the wakeup
54 * vector that will be called by the ROM on wakeup
55 */
56_GLOBAL(low_sleep_handler)
57#ifndef CONFIG_6xx
58 blr
59#else
60 mflr r0
61 stw r0,4(r1)
62 stwu r1,-SL_SIZE(r1)
63 mfcr r0
64 stw r0,SL_CR(r1)
65 stw r2,SL_R2(r1)
66 stmw r12,SL_R12(r1)
67
68 /* Save MSR & SDR1 */
69 mfmsr r4
70 stw r4,SL_MSR(r1)
71 mfsdr1 r4
72 stw r4,SL_SDR1(r1)
73
74 /* Get a stable timebase and save it */
751: mftbu r4
76 stw r4,SL_TB(r1)
77 mftb r5
78 stw r5,SL_TB+4(r1)
79 mftbu r3
80 cmpw r3,r4
81 bne 1b
82
83 /* Save SPRGs */
84 mfsprg r4,0
85 stw r4,SL_SPRG0(r1)
86 mfsprg r4,1
87 stw r4,SL_SPRG0+4(r1)
88 mfsprg r4,2
89 stw r4,SL_SPRG0+8(r1)
90 mfsprg r4,3
91 stw r4,SL_SPRG0+12(r1)
92
93 /* Save BATs */
94 mfdbatu r4,0
95 stw r4,SL_DBAT0(r1)
96 mfdbatl r4,0
97 stw r4,SL_DBAT0+4(r1)
98 mfdbatu r4,1
99 stw r4,SL_DBAT1(r1)
100 mfdbatl r4,1
101 stw r4,SL_DBAT1+4(r1)
102 mfdbatu r4,2
103 stw r4,SL_DBAT2(r1)
104 mfdbatl r4,2
105 stw r4,SL_DBAT2+4(r1)
106 mfdbatu r4,3
107 stw r4,SL_DBAT3(r1)
108 mfdbatl r4,3
109 stw r4,SL_DBAT3+4(r1)
110 mfibatu r4,0
111 stw r4,SL_IBAT0(r1)
112 mfibatl r4,0
113 stw r4,SL_IBAT0+4(r1)
114 mfibatu r4,1
115 stw r4,SL_IBAT1(r1)
116 mfibatl r4,1
117 stw r4,SL_IBAT1+4(r1)
118 mfibatu r4,2
119 stw r4,SL_IBAT2(r1)
120 mfibatl r4,2
121 stw r4,SL_IBAT2+4(r1)
122 mfibatu r4,3
123 stw r4,SL_IBAT3(r1)
124 mfibatl r4,3
125 stw r4,SL_IBAT3+4(r1)
126
127 /* Backup various CPU config stuffs */
128 bl __save_cpu_setup
129
130 /* The ROM can wake us up via 2 different vectors:
131 * - On wallstreet & lombard, we must write a magic
132 * value 'Lars' at address 4 and a pointer to a
133 * memory location containing the PC to resume from
134 * at address 0.
135 * - On Core99, we must store the wakeup vector at
136 * address 0x80 and eventually it's parameters
137 * at address 0x84. I've have some trouble with those
138 * parameters however and I no longer use them.
139 */
140 lis r5,grackle_wake_up@ha
141 addi r5,r5,grackle_wake_up@l
142 tophys(r5,r5)
143 stw r5,SL_PC(r1)
144 lis r4,KERNELBASE@h
145 tophys(r5,r1)
146 addi r5,r5,SL_PC
147 lis r6,MAGIC@ha
148 addi r6,r6,MAGIC@l
149 stw r5,0(r4)
150 stw r6,4(r4)
151 /* Setup stuffs at 0x80-0x84 for Core99 */
152 lis r3,core99_wake_up@ha
153 addi r3,r3,core99_wake_up@l
154 tophys(r3,r3)
155 stw r3,0x80(r4)
156 stw r5,0x84(r4)
157 /* Store a pointer to our backup storage into
158 * a kernel global
159 */
160 lis r3,sleep_storage@ha
161 addi r3,r3,sleep_storage@l
162 stw r5,0(r3)
163
164 .globl low_cpu_die
165low_cpu_die:
166 /* Flush & disable all caches */
167 bl flush_disable_caches
168
169 /* Turn off data relocation. */
170 mfmsr r3 /* Save MSR in r7 */
171 rlwinm r3,r3,0,28,26 /* Turn off DR bit */
172 sync
173 mtmsr r3
174 isync
175
176BEGIN_FTR_SECTION
177 /* Flush any pending L2 data prefetches to work around HW bug */
178 sync
179 lis r3,0xfff0
180 lwz r0,0(r3) /* perform cache-inhibited load to ROM */
181 sync /* (caches are disabled at this point) */
182END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)
183
184/*
185 * Set the HID0 and MSR for sleep.
186 */
187 mfspr r2,SPRN_HID0
188 rlwinm r2,r2,0,10,7 /* clear doze, nap */
189 oris r2,r2,HID0_SLEEP@h
190 sync
191 isync
192 mtspr SPRN_HID0,r2
193 sync
194
195/* This loop puts us back to sleep in case we have a spurrious
196 * wakeup so that the host bridge properly stays asleep. The
197 * CPU will be turned off, either after a known time (about 1
198 * second) on wallstreet & lombard, or as soon as the CPU enters
199 * SLEEP mode on core99
200 */
201 mfmsr r2
202 oris r2,r2,MSR_POW@h
2031: sync
204 mtmsr r2
205 isync
206 b 1b
207
208/*
209 * Here is the resume code.
210 */
211
212
213/*
214 * Core99 machines resume here
215 * r4 has the physical address of SL_PC(sp) (unused)
216 */
217_GLOBAL(core99_wake_up)
218 /* Make sure HID0 no longer contains any sleep bit and that data cache
219 * is disabled
220 */
221 mfspr r3,SPRN_HID0
222 rlwinm r3,r3,0,11,7 /* clear SLEEP, NAP, DOZE bits */
223 rlwinm 3,r3,0,18,15 /* clear DCE, ICE */
224 mtspr SPRN_HID0,r3
225 sync
226 isync
227
228 /* sanitize MSR */
229 mfmsr r3
230 ori r3,r3,MSR_EE|MSR_IP
231 xori r3,r3,MSR_EE|MSR_IP
232 sync
233 isync
234 mtmsr r3
235 sync
236 isync
237
238 /* Recover sleep storage */
239 lis r3,sleep_storage@ha
240 addi r3,r3,sleep_storage@l
241 tophys(r3,r3)
242 lwz r1,0(r3)
243
244 /* Pass thru to older resume code ... */
245/*
246 * Here is the resume code for older machines.
247 * r1 has the physical address of SL_PC(sp).
248 */
249
250grackle_wake_up:
251
252 /* Restore the kernel's segment registers before
253 * we do any r1 memory access as we are not sure they
254 * are in a sane state above the first 256Mb region
255 */
256 li r0,16 /* load up segment register values */
257 mtctr r0 /* for context 0 */
258 lis r3,0x2000 /* Ku = 1, VSID = 0 */
259 li r4,0
2603: mtsrin r3,r4
261 addi r3,r3,0x111 /* increment VSID */
262 addis r4,r4,0x1000 /* address of next segment */
263 bdnz 3b
264 sync
265 isync
266
267 subi r1,r1,SL_PC
268
269 /* Restore various CPU config stuffs */
270 bl __restore_cpu_setup
271
272 /* Make sure all FPRs have been initialized */
273 bl reloc_offset
274 bl __init_fpu_registers
275
276 /* Invalidate & enable L1 cache, we don't care about
277 * whatever the ROM may have tried to write to memory
278 */
279 bl __inval_enable_L1
280
281 /* Restore the BATs, and SDR1. Then we can turn on the MMU. */
282 lwz r4,SL_SDR1(r1)
283 mtsdr1 r4
284 lwz r4,SL_SPRG0(r1)
285 mtsprg 0,r4
286 lwz r4,SL_SPRG0+4(r1)
287 mtsprg 1,r4
288 lwz r4,SL_SPRG0+8(r1)
289 mtsprg 2,r4
290 lwz r4,SL_SPRG0+12(r1)
291 mtsprg 3,r4
292
293 lwz r4,SL_DBAT0(r1)
294 mtdbatu 0,r4
295 lwz r4,SL_DBAT0+4(r1)
296 mtdbatl 0,r4
297 lwz r4,SL_DBAT1(r1)
298 mtdbatu 1,r4
299 lwz r4,SL_DBAT1+4(r1)
300 mtdbatl 1,r4
301 lwz r4,SL_DBAT2(r1)
302 mtdbatu 2,r4
303 lwz r4,SL_DBAT2+4(r1)
304 mtdbatl 2,r4
305 lwz r4,SL_DBAT3(r1)
306 mtdbatu 3,r4
307 lwz r4,SL_DBAT3+4(r1)
308 mtdbatl 3,r4
309 lwz r4,SL_IBAT0(r1)
310 mtibatu 0,r4
311 lwz r4,SL_IBAT0+4(r1)
312 mtibatl 0,r4
313 lwz r4,SL_IBAT1(r1)
314 mtibatu 1,r4
315 lwz r4,SL_IBAT1+4(r1)
316 mtibatl 1,r4
317 lwz r4,SL_IBAT2(r1)
318 mtibatu 2,r4
319 lwz r4,SL_IBAT2+4(r1)
320 mtibatl 2,r4
321 lwz r4,SL_IBAT3(r1)
322 mtibatu 3,r4
323 lwz r4,SL_IBAT3+4(r1)
324 mtibatl 3,r4
325
326BEGIN_FTR_SECTION
327 li r4,0
328 mtspr SPRN_DBAT4U,r4
329 mtspr SPRN_DBAT4L,r4
330 mtspr SPRN_DBAT5U,r4
331 mtspr SPRN_DBAT5L,r4
332 mtspr SPRN_DBAT6U,r4
333 mtspr SPRN_DBAT6L,r4
334 mtspr SPRN_DBAT7U,r4
335 mtspr SPRN_DBAT7L,r4
336 mtspr SPRN_IBAT4U,r4
337 mtspr SPRN_IBAT4L,r4
338 mtspr SPRN_IBAT5U,r4
339 mtspr SPRN_IBAT5L,r4
340 mtspr SPRN_IBAT6U,r4
341 mtspr SPRN_IBAT6L,r4
342 mtspr SPRN_IBAT7U,r4
343 mtspr SPRN_IBAT7L,r4
344END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS)
345
346 /* Flush all TLBs */
347 lis r4,0x1000
3481: addic. r4,r4,-0x1000
349 tlbie r4
350 blt 1b
351 sync
352
353 /* restore the MSR and turn on the MMU */
354 lwz r3,SL_MSR(r1)
355 bl turn_on_mmu
356
357 /* get back the stack pointer */
358 tovirt(r1,r1)
359
360 /* Restore TB */
361 li r3,0
362 mttbl r3
363 lwz r3,SL_TB(r1)
364 lwz r4,SL_TB+4(r1)
365 mttbu r3
366 mttbl r4
367
368 /* Restore the callee-saved registers and return */
369 lwz r0,SL_CR(r1)
370 mtcr r0
371 lwz r2,SL_R2(r1)
372 lmw r12,SL_R12(r1)
373 addi r1,r1,SL_SIZE
374 lwz r0,4(r1)
375 mtlr r0
376 blr
377
378turn_on_mmu:
379 mflr r4
380 tovirt(r4,r4)
381 mtsrr0 r4
382 mtsrr1 r3
383 sync
384 isync
385 rfi
386
387#endif /* defined(CONFIG_PM) || defined(CONFIG_CPU_FREQ) */
388
389 .section .data
390 .balign L1_CACHE_BYTES
391sleep_storage:
392 .long 0
393 .balign L1_CACHE_BYTES, 0
394
395#endif /* CONFIG_6xx */
396 .section .text
diff --git a/arch/ppc/platforms/pmac_smp.c b/arch/ppc/platforms/pmac_smp.c
deleted file mode 100644
index 26ff26238f0..00000000000
--- a/arch/ppc/platforms/pmac_smp.c
+++ /dev/null
@@ -1,692 +0,0 @@
1/*
2 * SMP support for power macintosh.
3 *
4 * We support both the old "powersurge" SMP architecture
5 * and the current Core99 (G4 PowerMac) machines.
6 *
7 * Note that we don't support the very first rev. of
8 * Apple/DayStar 2 CPUs board, the one with the funky
9 * watchdog. Hopefully, none of these should be there except
10 * maybe internally to Apple. I should probably still add some
11 * code to detect this card though and disable SMP. --BenH.
12 *
13 * Support Macintosh G4 SMP by Troy Benjegerdes (hozer@drgw.net)
14 * and Ben Herrenschmidt <benh@kernel.crashing.org>.
15 *
16 * Support for DayStar quad CPU cards
17 * Copyright (C) XLR8, Inc. 1994-2000
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version
22 * 2 of the License, or (at your option) any later version.
23 */
24#include <linux/config.h>
25#include <linux/kernel.h>
26#include <linux/sched.h>
27#include <linux/smp.h>
28#include <linux/smp_lock.h>
29#include <linux/interrupt.h>
30#include <linux/kernel_stat.h>
31#include <linux/delay.h>
32#include <linux/init.h>
33#include <linux/spinlock.h>
34#include <linux/errno.h>
35#include <linux/hardirq.h>
36#include <linux/cpu.h>
37
38#include <asm/ptrace.h>
39#include <asm/atomic.h>
40#include <asm/irq.h>
41#include <asm/page.h>
42#include <asm/pgtable.h>
43#include <asm/sections.h>
44#include <asm/io.h>
45#include <asm/prom.h>
46#include <asm/smp.h>
47#include <asm/residual.h>
48#include <asm/machdep.h>
49#include <asm/pmac_feature.h>
50#include <asm/time.h>
51#include <asm/open_pic.h>
52#include <asm/cacheflush.h>
53#include <asm/keylargo.h>
54
55/*
56 * Powersurge (old powermac SMP) support.
57 */
58
59extern void __secondary_start_pmac_0(void);
60
61/* Addresses for powersurge registers */
62#define HAMMERHEAD_BASE 0xf8000000
63#define HHEAD_CONFIG 0x90
64#define HHEAD_SEC_INTR 0xc0
65
66/* register for interrupting the primary processor on the powersurge */
67/* N.B. this is actually the ethernet ROM! */
68#define PSURGE_PRI_INTR 0xf3019000
69
70/* register for storing the start address for the secondary processor */
71/* N.B. this is the PCI config space address register for the 1st bridge */
72#define PSURGE_START 0xf2800000
73
74/* Daystar/XLR8 4-CPU card */
75#define PSURGE_QUAD_REG_ADDR 0xf8800000
76
77#define PSURGE_QUAD_IRQ_SET 0
78#define PSURGE_QUAD_IRQ_CLR 1
79#define PSURGE_QUAD_IRQ_PRIMARY 2
80#define PSURGE_QUAD_CKSTOP_CTL 3
81#define PSURGE_QUAD_PRIMARY_ARB 4
82#define PSURGE_QUAD_BOARD_ID 6
83#define PSURGE_QUAD_WHICH_CPU 7
84#define PSURGE_QUAD_CKSTOP_RDBK 8
85#define PSURGE_QUAD_RESET_CTL 11
86
87#define PSURGE_QUAD_OUT(r, v) (out_8(quad_base + ((r) << 4) + 4, (v)))
88#define PSURGE_QUAD_IN(r) (in_8(quad_base + ((r) << 4) + 4) & 0x0f)
89#define PSURGE_QUAD_BIS(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) | (v)))
90#define PSURGE_QUAD_BIC(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) & ~(v)))
91
92/* virtual addresses for the above */
93static volatile u8 __iomem *hhead_base;
94static volatile u8 __iomem *quad_base;
95static volatile u32 __iomem *psurge_pri_intr;
96static volatile u8 __iomem *psurge_sec_intr;
97static volatile u32 __iomem *psurge_start;
98
99/* values for psurge_type */
100#define PSURGE_NONE -1
101#define PSURGE_DUAL 0
102#define PSURGE_QUAD_OKEE 1
103#define PSURGE_QUAD_COTTON 2
104#define PSURGE_QUAD_ICEGRASS 3
105
106/* what sort of powersurge board we have */
107static int psurge_type = PSURGE_NONE;
108
109/* L2 and L3 cache settings to pass from CPU0 to CPU1 */
110volatile static long int core99_l2_cache;
111volatile static long int core99_l3_cache;
112
113/* Timebase freeze GPIO */
114static unsigned int core99_tb_gpio;
115
116/* Sync flag for HW tb sync */
117static volatile int sec_tb_reset = 0;
118static unsigned int pri_tb_hi, pri_tb_lo;
119static unsigned int pri_tb_stamp;
120
121static void __devinit core99_init_caches(int cpu)
122{
123 if (!cpu_has_feature(CPU_FTR_L2CR))
124 return;
125
126 if (cpu == 0) {
127 core99_l2_cache = _get_L2CR();
128 printk("CPU0: L2CR is %lx\n", core99_l2_cache);
129 } else {
130 printk("CPU%d: L2CR was %lx\n", cpu, _get_L2CR());
131 _set_L2CR(0);
132 _set_L2CR(core99_l2_cache);
133 printk("CPU%d: L2CR set to %lx\n", cpu, core99_l2_cache);
134 }
135
136 if (!cpu_has_feature(CPU_FTR_L3CR))
137 return;
138
139 if (cpu == 0){
140 core99_l3_cache = _get_L3CR();
141 printk("CPU0: L3CR is %lx\n", core99_l3_cache);
142 } else {
143 printk("CPU%d: L3CR was %lx\n", cpu, _get_L3CR());
144 _set_L3CR(0);
145 _set_L3CR(core99_l3_cache);
146 printk("CPU%d: L3CR set to %lx\n", cpu, core99_l3_cache);
147 }
148}
149
150/*
151 * Set and clear IPIs for powersurge.
152 */
153static inline void psurge_set_ipi(int cpu)
154{
155 if (psurge_type == PSURGE_NONE)
156 return;
157 if (cpu == 0)
158 in_be32(psurge_pri_intr);
159 else if (psurge_type == PSURGE_DUAL)
160 out_8(psurge_sec_intr, 0);
161 else
162 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_SET, 1 << cpu);
163}
164
165static inline void psurge_clr_ipi(int cpu)
166{
167 if (cpu > 0) {
168 switch(psurge_type) {
169 case PSURGE_DUAL:
170 out_8(psurge_sec_intr, ~0);
171 case PSURGE_NONE:
172 break;
173 default:
174 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, 1 << cpu);
175 }
176 }
177}
178
179/*
180 * On powersurge (old SMP powermac architecture) we don't have
181 * separate IPIs for separate messages like openpic does. Instead
182 * we have a bitmap for each processor, where a 1 bit means that
183 * the corresponding message is pending for that processor.
184 * Ideally each cpu's entry would be in a different cache line.
185 * -- paulus.
186 */
187static unsigned long psurge_smp_message[NR_CPUS];
188
189void psurge_smp_message_recv(struct pt_regs *regs)
190{
191 int cpu = smp_processor_id();
192 int msg;
193
194 /* clear interrupt */
195 psurge_clr_ipi(cpu);
196
197 if (num_online_cpus() < 2)
198 return;
199
200 /* make sure there is a message there */
201 for (msg = 0; msg < 4; msg++)
202 if (test_and_clear_bit(msg, &psurge_smp_message[cpu]))
203 smp_message_recv(msg, regs);
204}
205
206irqreturn_t psurge_primary_intr(int irq, void *d, struct pt_regs *regs)
207{
208 psurge_smp_message_recv(regs);
209 return IRQ_HANDLED;
210}
211
212static void smp_psurge_message_pass(int target, int msg)
213{
214 int i;
215
216 if (num_online_cpus() < 2)
217 return;
218
219 for (i = 0; i < NR_CPUS; i++) {
220 if (!cpu_online(i))
221 continue;
222 if (target == MSG_ALL
223 || (target == MSG_ALL_BUT_SELF && i != smp_processor_id())
224 || target == i) {
225 set_bit(msg, &psurge_smp_message[i]);
226 psurge_set_ipi(i);
227 }
228 }
229}
230
231/*
232 * Determine a quad card presence. We read the board ID register, we
233 * force the data bus to change to something else, and we read it again.
234 * It it's stable, then the register probably exist (ugh !)
235 */
236static int __init psurge_quad_probe(void)
237{
238 int type;
239 unsigned int i;
240
241 type = PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID);
242 if (type < PSURGE_QUAD_OKEE || type > PSURGE_QUAD_ICEGRASS
243 || type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID))
244 return PSURGE_DUAL;
245
246 /* looks OK, try a slightly more rigorous test */
247 /* bogus is not necessarily cacheline-aligned,
248 though I don't suppose that really matters. -- paulus */
249 for (i = 0; i < 100; i++) {
250 volatile u32 bogus[8];
251 bogus[(0+i)%8] = 0x00000000;
252 bogus[(1+i)%8] = 0x55555555;
253 bogus[(2+i)%8] = 0xFFFFFFFF;
254 bogus[(3+i)%8] = 0xAAAAAAAA;
255 bogus[(4+i)%8] = 0x33333333;
256 bogus[(5+i)%8] = 0xCCCCCCCC;
257 bogus[(6+i)%8] = 0xCCCCCCCC;
258 bogus[(7+i)%8] = 0x33333333;
259 wmb();
260 asm volatile("dcbf 0,%0" : : "r" (bogus) : "memory");
261 mb();
262 if (type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID))
263 return PSURGE_DUAL;
264 }
265 return type;
266}
267
268static void __init psurge_quad_init(void)
269{
270 int procbits;
271
272 if (ppc_md.progress) ppc_md.progress("psurge_quad_init", 0x351);
273 procbits = ~PSURGE_QUAD_IN(PSURGE_QUAD_WHICH_CPU);
274 if (psurge_type == PSURGE_QUAD_ICEGRASS)
275 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits);
276 else
277 PSURGE_QUAD_BIC(PSURGE_QUAD_CKSTOP_CTL, procbits);
278 mdelay(33);
279 out_8(psurge_sec_intr, ~0);
280 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, procbits);
281 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits);
282 if (psurge_type != PSURGE_QUAD_ICEGRASS)
283 PSURGE_QUAD_BIS(PSURGE_QUAD_CKSTOP_CTL, procbits);
284 PSURGE_QUAD_BIC(PSURGE_QUAD_PRIMARY_ARB, procbits);
285 mdelay(33);
286 PSURGE_QUAD_BIC(PSURGE_QUAD_RESET_CTL, procbits);
287 mdelay(33);
288 PSURGE_QUAD_BIS(PSURGE_QUAD_PRIMARY_ARB, procbits);
289 mdelay(33);
290}
291
292static int __init smp_psurge_probe(void)
293{
294 int i, ncpus;
295
296 /* We don't do SMP on the PPC601 -- paulus */
297 if (PVR_VER(mfspr(SPRN_PVR)) == 1)
298 return 1;
299
300 /*
301 * The powersurge cpu board can be used in the generation
302 * of powermacs that have a socket for an upgradeable cpu card,
303 * including the 7500, 8500, 9500, 9600.
304 * The device tree doesn't tell you if you have 2 cpus because
305 * OF doesn't know anything about the 2nd processor.
306 * Instead we look for magic bits in magic registers,
307 * in the hammerhead memory controller in the case of the
308 * dual-cpu powersurge board. -- paulus.
309 */
310 if (find_devices("hammerhead") == NULL)
311 return 1;
312
313 hhead_base = ioremap(HAMMERHEAD_BASE, 0x800);
314 quad_base = ioremap(PSURGE_QUAD_REG_ADDR, 1024);
315 psurge_sec_intr = hhead_base + HHEAD_SEC_INTR;
316
317 psurge_type = psurge_quad_probe();
318 if (psurge_type != PSURGE_DUAL) {
319 psurge_quad_init();
320 /* All released cards using this HW design have 4 CPUs */
321 ncpus = 4;
322 } else {
323 iounmap(quad_base);
324 if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) {
325 /* not a dual-cpu card */
326 iounmap(hhead_base);
327 psurge_type = PSURGE_NONE;
328 return 1;
329 }
330 ncpus = 2;
331 }
332
333 psurge_start = ioremap(PSURGE_START, 4);
334 psurge_pri_intr = ioremap(PSURGE_PRI_INTR, 4);
335
336 /* this is not actually strictly necessary -- paulus. */
337 for (i = 1; i < ncpus; ++i)
338 smp_hw_index[i] = i;
339
340 if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352);
341
342 return ncpus;
343}
344
345static void __init smp_psurge_kick_cpu(int nr)
346{
347 unsigned long start = __pa(__secondary_start_pmac_0) + nr * 8;
348 unsigned long a;
349
350 /* may need to flush here if secondary bats aren't setup */
351 for (a = KERNELBASE; a < KERNELBASE + 0x800000; a += 32)
352 asm volatile("dcbf 0,%0" : : "r" (a) : "memory");
353 asm volatile("sync");
354
355 if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu", 0x353);
356
357 out_be32(psurge_start, start);
358 mb();
359
360 psurge_set_ipi(nr);
361 udelay(10);
362 psurge_clr_ipi(nr);
363
364 if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354);
365}
366
367/*
368 * With the dual-cpu powersurge board, the decrementers and timebases
369 * of both cpus are frozen after the secondary cpu is started up,
370 * until we give the secondary cpu another interrupt. This routine
371 * uses this to get the timebases synchronized.
372 * -- paulus.
373 */
374static void __init psurge_dual_sync_tb(int cpu_nr)
375{
376 int t;
377
378 set_dec(tb_ticks_per_jiffy);
379 set_tb(0, 0);
380 last_jiffy_stamp(cpu_nr) = 0;
381
382 if (cpu_nr > 0) {
383 mb();
384 sec_tb_reset = 1;
385 return;
386 }
387
388 /* wait for the secondary to have reset its TB before proceeding */
389 for (t = 10000000; t > 0 && !sec_tb_reset; --t)
390 ;
391
392 /* now interrupt the secondary, starting both TBs */
393 psurge_set_ipi(1);
394
395 smp_tb_synchronized = 1;
396}
397
398static struct irqaction psurge_irqaction = {
399 .handler = psurge_primary_intr,
400 .flags = SA_INTERRUPT,
401 .mask = CPU_MASK_NONE,
402 .name = "primary IPI",
403};
404
405static void __init smp_psurge_setup_cpu(int cpu_nr)
406{
407
408 if (cpu_nr == 0) {
409 /* If we failed to start the second CPU, we should still
410 * send it an IPI to start the timebase & DEC or we might
411 * have them stuck.
412 */
413 if (num_online_cpus() < 2) {
414 if (psurge_type == PSURGE_DUAL)
415 psurge_set_ipi(1);
416 return;
417 }
418 /* reset the entry point so if we get another intr we won't
419 * try to startup again */
420 out_be32(psurge_start, 0x100);
421 if (setup_irq(30, &psurge_irqaction))
422 printk(KERN_ERR "Couldn't get primary IPI interrupt");
423 }
424
425 if (psurge_type == PSURGE_DUAL)
426 psurge_dual_sync_tb(cpu_nr);
427}
428
429void __init smp_psurge_take_timebase(void)
430{
431 /* Dummy implementation */
432}
433
434void __init smp_psurge_give_timebase(void)
435{
436 /* Dummy implementation */
437}
438
439static int __init smp_core99_probe(void)
440{
441#ifdef CONFIG_6xx
442 extern int powersave_nap;
443#endif
444 struct device_node *cpus, *firstcpu;
445 int i, ncpus = 0, boot_cpu = -1;
446 u32 *tbprop = NULL;
447
448 if (ppc_md.progress) ppc_md.progress("smp_core99_probe", 0x345);
449 cpus = firstcpu = find_type_devices("cpu");
450 while(cpus != NULL) {
451 u32 *regprop = (u32 *)get_property(cpus, "reg", NULL);
452 char *stateprop = (char *)get_property(cpus, "state", NULL);
453 if (regprop != NULL && stateprop != NULL &&
454 !strncmp(stateprop, "running", 7))
455 boot_cpu = *regprop;
456 ++ncpus;
457 cpus = cpus->next;
458 }
459 if (boot_cpu == -1)
460 printk(KERN_WARNING "Couldn't detect boot CPU !\n");
461 if (boot_cpu != 0)
462 printk(KERN_WARNING "Boot CPU is %d, unsupported setup !\n", boot_cpu);
463
464 if (machine_is_compatible("MacRISC4")) {
465 extern struct smp_ops_t core99_smp_ops;
466
467 core99_smp_ops.take_timebase = smp_generic_take_timebase;
468 core99_smp_ops.give_timebase = smp_generic_give_timebase;
469 } else {
470 if (firstcpu != NULL)
471 tbprop = (u32 *)get_property(firstcpu, "timebase-enable", NULL);
472 if (tbprop)
473 core99_tb_gpio = *tbprop;
474 else
475 core99_tb_gpio = KL_GPIO_TB_ENABLE;
476 }
477
478 if (ncpus > 1) {
479 openpic_request_IPIs();
480 for (i = 1; i < ncpus; ++i)
481 smp_hw_index[i] = i;
482#ifdef CONFIG_6xx
483 powersave_nap = 0;
484#endif
485 core99_init_caches(0);
486 }
487
488 return ncpus;
489}
490
491static void __devinit smp_core99_kick_cpu(int nr)
492{
493 unsigned long save_vector, new_vector;
494 unsigned long flags;
495
496 volatile unsigned long *vector
497 = ((volatile unsigned long *)(KERNELBASE+0x100));
498 if (nr < 0 || nr > 3)
499 return;
500 if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu", 0x346);
501
502 local_irq_save(flags);
503 local_irq_disable();
504
505 /* Save reset vector */
506 save_vector = *vector;
507
508 /* Setup fake reset vector that does
509 * b __secondary_start_pmac_0 + nr*8 - KERNELBASE
510 */
511 new_vector = (unsigned long) __secondary_start_pmac_0 + nr * 8;
512 *vector = 0x48000002 + new_vector - KERNELBASE;
513
514 /* flush data cache and inval instruction cache */
515 flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);
516
517 /* Put some life in our friend */
518 pmac_call_feature(PMAC_FTR_RESET_CPU, NULL, nr, 0);
519
520 /* FIXME: We wait a bit for the CPU to take the exception, I should
521 * instead wait for the entry code to set something for me. Well,
522 * ideally, all that crap will be done in prom.c and the CPU left
523 * in a RAM-based wait loop like CHRP.
524 */
525 mdelay(1);
526
527 /* Restore our exception vector */
528 *vector = save_vector;
529 flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);
530
531 local_irq_restore(flags);
532 if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu done", 0x347);
533}
534
535static void __devinit smp_core99_setup_cpu(int cpu_nr)
536{
537 /* Setup L2/L3 */
538 if (cpu_nr != 0)
539 core99_init_caches(cpu_nr);
540
541 /* Setup openpic */
542 do_openpic_setup_cpu();
543
544 if (cpu_nr == 0) {
545#ifdef CONFIG_POWER4
546 extern void g5_phy_disable_cpu1(void);
547
548 /* If we didn't start the second CPU, we must take
549 * it off the bus
550 */
551 if (machine_is_compatible("MacRISC4") &&
552 num_online_cpus() < 2)
553 g5_phy_disable_cpu1();
554#endif /* CONFIG_POWER4 */
555 if (ppc_md.progress) ppc_md.progress("core99_setup_cpu 0 done", 0x349);
556 }
557}
558
559/* not __init, called in sleep/wakeup code */
560void smp_core99_take_timebase(void)
561{
562 unsigned long flags;
563
564 /* tell the primary we're here */
565 sec_tb_reset = 1;
566 mb();
567
568 /* wait for the primary to set pri_tb_hi/lo */
569 while (sec_tb_reset < 2)
570 mb();
571
572 /* set our stuff the same as the primary */
573 local_irq_save(flags);
574 set_dec(1);
575 set_tb(pri_tb_hi, pri_tb_lo);
576 last_jiffy_stamp(smp_processor_id()) = pri_tb_stamp;
577 mb();
578
579 /* tell the primary we're done */
580 sec_tb_reset = 0;
581 mb();
582 local_irq_restore(flags);
583}
584
585/* not __init, called in sleep/wakeup code */
586void smp_core99_give_timebase(void)
587{
588 unsigned long flags;
589 unsigned int t;
590
591 /* wait for the secondary to be in take_timebase */
592 for (t = 100000; t > 0 && !sec_tb_reset; --t)
593 udelay(10);
594 if (!sec_tb_reset) {
595 printk(KERN_WARNING "Timeout waiting sync on second CPU\n");
596 return;
597 }
598
599 /* freeze the timebase and read it */
600 /* disable interrupts so the timebase is disabled for the
601 shortest possible time */
602 local_irq_save(flags);
603 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 4);
604 pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, core99_tb_gpio, 0);
605 mb();
606 pri_tb_hi = get_tbu();
607 pri_tb_lo = get_tbl();
608 pri_tb_stamp = last_jiffy_stamp(smp_processor_id());
609 mb();
610
611 /* tell the secondary we're ready */
612 sec_tb_reset = 2;
613 mb();
614
615 /* wait for the secondary to have taken it */
616 for (t = 100000; t > 0 && sec_tb_reset; --t)
617 udelay(10);
618 if (sec_tb_reset)
619 printk(KERN_WARNING "Timeout waiting sync(2) on second CPU\n");
620 else
621 smp_tb_synchronized = 1;
622
623 /* Now, restart the timebase by leaving the GPIO to an open collector */
624 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 0);
625 pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, core99_tb_gpio, 0);
626 local_irq_restore(flags);
627}
628
629
630/* PowerSurge-style Macs */
631struct smp_ops_t psurge_smp_ops = {
632 .message_pass = smp_psurge_message_pass,
633 .probe = smp_psurge_probe,
634 .kick_cpu = smp_psurge_kick_cpu,
635 .setup_cpu = smp_psurge_setup_cpu,
636 .give_timebase = smp_psurge_give_timebase,
637 .take_timebase = smp_psurge_take_timebase,
638};
639
640/* Core99 Macs (dual G4s) */
641struct smp_ops_t core99_smp_ops = {
642 .message_pass = smp_openpic_message_pass,
643 .probe = smp_core99_probe,
644 .kick_cpu = smp_core99_kick_cpu,
645 .setup_cpu = smp_core99_setup_cpu,
646 .give_timebase = smp_core99_give_timebase,
647 .take_timebase = smp_core99_take_timebase,
648};
649
650#ifdef CONFIG_HOTPLUG_CPU
651
652int __cpu_disable(void)
653{
654 cpu_clear(smp_processor_id(), cpu_online_map);
655
656 /* XXX reset cpu affinity here */
657 openpic_set_priority(0xf);
658 asm volatile("mtdec %0" : : "r" (0x7fffffff));
659 mb();
660 udelay(20);
661 asm volatile("mtdec %0" : : "r" (0x7fffffff));
662 return 0;
663}
664
665extern void low_cpu_die(void) __attribute__((noreturn)); /* in pmac_sleep.S */
666static int cpu_dead[NR_CPUS];
667
668void cpu_die(void)
669{
670 local_irq_disable();
671 cpu_dead[smp_processor_id()] = 1;
672 mb();
673 low_cpu_die();
674}
675
676void __cpu_die(unsigned int cpu)
677{
678 int timeout;
679
680 timeout = 1000;
681 while (!cpu_dead[cpu]) {
682 if (--timeout == 0) {
683 printk("CPU %u refused to die!\n", cpu);
684 break;
685 }
686 msleep(1);
687 }
688 cpu_callin_map[cpu] = 0;
689 cpu_dead[cpu] = 0;
690}
691
692#endif
diff --git a/arch/ppc/platforms/pmac_time.c b/arch/ppc/platforms/pmac_time.c
deleted file mode 100644
index edb9fcc6479..00000000000
--- a/arch/ppc/platforms/pmac_time.c
+++ /dev/null
@@ -1,291 +0,0 @@
1/*
2 * Support for periodic interrupts (100 per second) and for getting
3 * the current time from the RTC on Power Macintoshes.
4 *
5 * We use the decrementer register for our periodic interrupts.
6 *
7 * Paul Mackerras August 1996.
8 * Copyright (C) 1996 Paul Mackerras.
9 */
10#include <linux/config.h>
11#include <linux/errno.h>
12#include <linux/sched.h>
13#include <linux/kernel.h>
14#include <linux/param.h>
15#include <linux/string.h>
16#include <linux/mm.h>
17#include <linux/init.h>
18#include <linux/time.h>
19#include <linux/adb.h>
20#include <linux/cuda.h>
21#include <linux/pmu.h>
22#include <linux/hardirq.h>
23
24#include <asm/sections.h>
25#include <asm/prom.h>
26#include <asm/system.h>
27#include <asm/io.h>
28#include <asm/pgtable.h>
29#include <asm/machdep.h>
30#include <asm/time.h>
31#include <asm/nvram.h>
32
33/* Apparently the RTC stores seconds since 1 Jan 1904 */
34#define RTC_OFFSET 2082844800
35
36/*
37 * Calibrate the decrementer frequency with the VIA timer 1.
38 */
39#define VIA_TIMER_FREQ_6 4700000 /* time 1 frequency * 6 */
40
41/* VIA registers */
42#define RS 0x200 /* skip between registers */
43#define T1CL (4*RS) /* Timer 1 ctr/latch (low 8 bits) */
44#define T1CH (5*RS) /* Timer 1 counter (high 8 bits) */
45#define T1LL (6*RS) /* Timer 1 latch (low 8 bits) */
46#define T1LH (7*RS) /* Timer 1 latch (high 8 bits) */
47#define ACR (11*RS) /* Auxiliary control register */
48#define IFR (13*RS) /* Interrupt flag register */
49
50/* Bits in ACR */
51#define T1MODE 0xc0 /* Timer 1 mode */
52#define T1MODE_CONT 0x40 /* continuous interrupts */
53
54/* Bits in IFR and IER */
55#define T1_INT 0x40 /* Timer 1 interrupt */
56
57extern struct timezone sys_tz;
58
59long __init
60pmac_time_init(void)
61{
62#ifdef CONFIG_NVRAM
63 s32 delta = 0;
64 int dst;
65
66 delta = ((s32)pmac_xpram_read(PMAC_XPRAM_MACHINE_LOC + 0x9)) << 16;
67 delta |= ((s32)pmac_xpram_read(PMAC_XPRAM_MACHINE_LOC + 0xa)) << 8;
68 delta |= pmac_xpram_read(PMAC_XPRAM_MACHINE_LOC + 0xb);
69 if (delta & 0x00800000UL)
70 delta |= 0xFF000000UL;
71 dst = ((pmac_xpram_read(PMAC_XPRAM_MACHINE_LOC + 0x8) & 0x80) != 0);
72 printk("GMT Delta read from XPRAM: %d minutes, DST: %s\n", delta/60,
73 dst ? "on" : "off");
74 return delta;
75#else
76 return 0;
77#endif
78}
79
80unsigned long
81pmac_get_rtc_time(void)
82{
83#if defined(CONFIG_ADB_CUDA) || defined(CONFIG_ADB_PMU)
84 struct adb_request req;
85 unsigned long now;
86#endif
87
88 /* Get the time from the RTC */
89 switch (sys_ctrler) {
90#ifdef CONFIG_ADB_CUDA
91 case SYS_CTRLER_CUDA:
92 if (cuda_request(&req, NULL, 2, CUDA_PACKET, CUDA_GET_TIME) < 0)
93 return 0;
94 while (!req.complete)
95 cuda_poll();
96 if (req.reply_len != 7)
97 printk(KERN_ERR "pmac_get_rtc_time: got %d byte reply\n",
98 req.reply_len);
99 now = (req.reply[3] << 24) + (req.reply[4] << 16)
100 + (req.reply[5] << 8) + req.reply[6];
101 return now - RTC_OFFSET;
102#endif /* CONFIG_ADB_CUDA */
103#ifdef CONFIG_ADB_PMU
104 case SYS_CTRLER_PMU:
105 if (pmu_request(&req, NULL, 1, PMU_READ_RTC) < 0)
106 return 0;
107 while (!req.complete)
108 pmu_poll();
109 if (req.reply_len != 4)
110 printk(KERN_ERR "pmac_get_rtc_time: got %d byte reply\n",
111 req.reply_len);
112 now = (req.reply[0] << 24) + (req.reply[1] << 16)
113 + (req.reply[2] << 8) + req.reply[3];
114 return now - RTC_OFFSET;
115#endif /* CONFIG_ADB_PMU */
116 default: ;
117 }
118 return 0;
119}
120
121int
122pmac_set_rtc_time(unsigned long nowtime)
123{
124#if defined(CONFIG_ADB_CUDA) || defined(CONFIG_ADB_PMU)
125 struct adb_request req;
126#endif
127
128 nowtime += RTC_OFFSET;
129
130 switch (sys_ctrler) {
131#ifdef CONFIG_ADB_CUDA
132 case SYS_CTRLER_CUDA:
133 if (cuda_request(&req, NULL, 6, CUDA_PACKET, CUDA_SET_TIME,
134 nowtime >> 24, nowtime >> 16, nowtime >> 8, nowtime) < 0)
135 return 0;
136 while (!req.complete)
137 cuda_poll();
138 if ((req.reply_len != 3) && (req.reply_len != 7))
139 printk(KERN_ERR "pmac_set_rtc_time: got %d byte reply\n",
140 req.reply_len);
141 return 1;
142#endif /* CONFIG_ADB_CUDA */
143#ifdef CONFIG_ADB_PMU
144 case SYS_CTRLER_PMU:
145 if (pmu_request(&req, NULL, 5, PMU_SET_RTC,
146 nowtime >> 24, nowtime >> 16, nowtime >> 8, nowtime) < 0)
147 return 0;
148 while (!req.complete)
149 pmu_poll();
150 if (req.reply_len != 0)
151 printk(KERN_ERR "pmac_set_rtc_time: got %d byte reply\n",
152 req.reply_len);
153 return 1;
154#endif /* CONFIG_ADB_PMU */
155 default:
156 return 0;
157 }
158}
159
160/*
161 * Calibrate the decrementer register using VIA timer 1.
162 * This is used both on powermacs and CHRP machines.
163 */
164int __init
165via_calibrate_decr(void)
166{
167 struct device_node *vias;
168 volatile unsigned char __iomem *via;
169 int count = VIA_TIMER_FREQ_6 / 100;
170 unsigned int dstart, dend;
171
172 vias = find_devices("via-cuda");
173 if (vias == 0)
174 vias = find_devices("via-pmu");
175 if (vias == 0)
176 vias = find_devices("via");
177 if (vias == 0 || vias->n_addrs == 0)
178 return 0;
179 via = ioremap(vias->addrs[0].address, vias->addrs[0].size);
180
181 /* set timer 1 for continuous interrupts */
182 out_8(&via[ACR], (via[ACR] & ~T1MODE) | T1MODE_CONT);
183 /* set the counter to a small value */
184 out_8(&via[T1CH], 2);
185 /* set the latch to `count' */
186 out_8(&via[T1LL], count);
187 out_8(&via[T1LH], count >> 8);
188 /* wait until it hits 0 */
189 while ((in_8(&via[IFR]) & T1_INT) == 0)
190 ;
191 dstart = get_dec();
192 /* clear the interrupt & wait until it hits 0 again */
193 in_8(&via[T1CL]);
194 while ((in_8(&via[IFR]) & T1_INT) == 0)
195 ;
196 dend = get_dec();
197
198 tb_ticks_per_jiffy = (dstart - dend) / ((6 * HZ)/100);
199 tb_to_us = mulhwu_scale_factor(dstart - dend, 60000);
200
201 printk(KERN_INFO "via_calibrate_decr: ticks per jiffy = %u (%u ticks)\n",
202 tb_ticks_per_jiffy, dstart - dend);
203
204 iounmap(via);
205
206 return 1;
207}
208
209#ifdef CONFIG_PM
210/*
211 * Reset the time after a sleep.
212 */
213static int
214time_sleep_notify(struct pmu_sleep_notifier *self, int when)
215{
216 static unsigned long time_diff;
217 unsigned long flags;
218 unsigned long seq;
219
220 switch (when) {
221 case PBOOK_SLEEP_NOW:
222 do {
223 seq = read_seqbegin_irqsave(&xtime_lock, flags);
224 time_diff = xtime.tv_sec - pmac_get_rtc_time();
225 } while (read_seqretry_irqrestore(&xtime_lock, seq, flags));
226 break;
227 case PBOOK_WAKE:
228 write_seqlock_irqsave(&xtime_lock, flags);
229 xtime.tv_sec = pmac_get_rtc_time() + time_diff;
230 xtime.tv_nsec = 0;
231 last_rtc_update = xtime.tv_sec;
232 write_sequnlock_irqrestore(&xtime_lock, flags);
233 break;
234 }
235 return PBOOK_SLEEP_OK;
236}
237
238static struct pmu_sleep_notifier time_sleep_notifier = {
239 time_sleep_notify, SLEEP_LEVEL_MISC,
240};
241#endif /* CONFIG_PM */
242
243/*
244 * Query the OF and get the decr frequency.
245 * This was taken from the pmac time_init() when merging the prep/pmac
246 * time functions.
247 */
248void __init
249pmac_calibrate_decr(void)
250{
251 struct device_node *cpu;
252 unsigned int freq, *fp;
253
254#ifdef CONFIG_PM
255 pmu_register_sleep_notifier(&time_sleep_notifier);
256#endif /* CONFIG_PM */
257
258 /* We assume MacRISC2 machines have correct device-tree
259 * calibration. That's better since the VIA itself seems
260 * to be slightly off. --BenH
261 */
262 if (!machine_is_compatible("MacRISC2") &&
263 !machine_is_compatible("MacRISC3") &&
264 !machine_is_compatible("MacRISC4"))
265 if (via_calibrate_decr())
266 return;
267
268 /* Special case: QuickSilver G4s seem to have a badly calibrated
269 * timebase-frequency in OF, VIA is much better on these. We should
270 * probably implement calibration based on the KL timer on these
271 * machines anyway... -BenH
272 */
273 if (machine_is_compatible("PowerMac3,5"))
274 if (via_calibrate_decr())
275 return;
276 /*
277 * The cpu node should have a timebase-frequency property
278 * to tell us the rate at which the decrementer counts.
279 */
280 cpu = find_type_devices("cpu");
281 if (cpu == 0)
282 panic("can't find cpu node in time_init");
283 fp = (unsigned int *) get_property(cpu, "timebase-frequency", NULL);
284 if (fp == 0)
285 panic("can't get cpu timebase frequency");
286 freq = *fp;
287 printk("time_init: decrementer frequency = %u.%.6u MHz\n",
288 freq/1000000, freq%1000000);
289 tb_ticks_per_jiffy = freq / HZ;
290 tb_to_us = mulhwu_scale_factor(freq, 1000000);
291}
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