Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc

* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (53 commits)
  serial: Add driver for the Cell Network Processor serial port NWP device
  powerpc: enable dynamic ftrace
  powerpc/cell: Fix the prototype of create_vma_map()
  powerpc/mm: Make clear_fixmap() actually work
  powerpc/kdump: Use ppc_save_regs() in crash_setup_regs()
  powerpc: Export cacheable_memzero as its now used in a driver
  powerpc: Fix missing semicolons in mmu_decl.h
  powerpc/pasemi: local_irq_save uses an unsigned long
  powerpc/cell: Fix some u64 vs. long types
  powerpc/cell: Use correct types in beat files
  powerpc: Use correct type in prom_init.c
  powerpc: Remove unnecessary casts
  mtd/ps3vram: Use _PAGE_NO_CACHE in memory ioremap
  mtd/ps3vram: Use msleep in waits
  mtd/ps3vram: Use proper kernel types
  mtd/ps3vram: Cleanup ps3vram driver messages
  mtd/ps3vram: Remove ps3vram debug routines
  mtd/ps3vram: Add modalias support to the ps3vram driver
  mtd/ps3vram: Add ps3vram driver for accessing video RAM as MTD
  powerpc: Fix iseries drivers build failure without CONFIG_VIOPATH
  ...

7 files changed, 374 insertions, 4 deletions

diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 5afce115ab1..b33b28a6fe1 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_FSL_PCI)		+= fsl_pci.o $(fsl-msi-obj-y)
 obj-$(CONFIG_FSL_LBC)           += fsl_lbc.o
 obj-$(CONFIG_FSL_GTM)           += fsl_gtm.o
 obj-$(CONFIG_MPC8xxx_GPIO)      += mpc8xxx_gpio.o
+obj-$(CONFIG_SIMPLE_GPIO)       += simple_gpio.o
 obj-$(CONFIG_RAPIDIO)           += fsl_rio.o
 obj-$(CONFIG_TSI108_BRIDGE)     += tsi108_pci.o tsi108_dev.o
 obj-$(CONFIG_QUICC_ENGINE)      += qe_lib/
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index d5f9ae0f1b7..f611d0369cc 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -29,7 +29,8 @@
 
 #if defined(CONFIG_PPC_85xx) || defined(CONFIG_PPC_86xx)
 /* atmu setup for fsl pci/pcie controller */
-void __init setup_pci_atmu(struct pci_controller *hose, struct resource *rsrc)
+static void __init setup_pci_atmu(struct pci_controller *hose,
+                                  struct resource *rsrc)
 {
         struct ccsr_pci __iomem *pci;
         int i;
@@ -86,7 +87,7 @@ void __init setup_pci_atmu(struct pci_controller *hose, struct resource *rsrc)
         out_be32(&pci->piw[2].piwar, PIWAR_2G);
 }
 
-void __init setup_pci_cmd(struct pci_controller *hose)
+static void __init setup_pci_cmd(struct pci_controller *hose)
 {
         u16 cmd;
         int cap_x;
@@ -130,7 +131,7 @@ static void __init quirk_fsl_pcie_header(struct pci_dev *dev)
         return ;
 }
 
-int __init fsl_pcie_check_link(struct pci_controller *hose)
+static int __init fsl_pcie_check_link(struct pci_controller *hose)
 {
         u32 val;
         early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
diff --git a/arch/powerpc/sysdev/fsl_soc.h b/arch/powerpc/sysdev/fsl_soc.h
index 60f7f227327..9c744e4285a 100644
--- a/arch/powerpc/sysdev/fsl_soc.h
+++ b/arch/powerpc/sysdev/fsl_soc.h
@@ -5,8 +5,13 @@
 #include <asm/mmu.h>
 
 extern phys_addr_t get_immrbase(void);
+#if defined(CONFIG_CPM2) || defined(CONFIG_QUICC_ENGINE) || defined(CONFIG_8xx)
 extern u32 get_brgfreq(void);
 extern u32 get_baudrate(void);
+#else
+static inline u32 get_brgfreq(void) { return -1; }
+static inline u32 get_baudrate(void) { return -1; }
+#endif
 extern u32 fsl_get_sys_freq(void);
 
 struct spi_board_info;
diff --git a/arch/powerpc/sysdev/qe_lib/Kconfig b/arch/powerpc/sysdev/qe_lib/Kconfig
index 76ffbc48d4b..41ac3dfac98 100644
--- a/arch/powerpc/sysdev/qe_lib/Kconfig
+++ b/arch/powerpc/sysdev/qe_lib/Kconfig
@@ -22,5 +22,6 @@ config UCC
 
 config QE_USB
         bool
+        default y if USB_GADGET_FSL_QE
         help
-          QE USB Host Controller support
+          QE USB Controller support
diff --git a/arch/powerpc/sysdev/qe_lib/gpio.c b/arch/powerpc/sysdev/qe_lib/gpio.c
index 8e5a0bc36d0..3485288dce3 100644
--- a/arch/powerpc/sysdev/qe_lib/gpio.c
+++ b/arch/powerpc/sysdev/qe_lib/gpio.c
@@ -14,6 +14,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/spinlock.h>
+#include <linux/err.h>
 #include <linux/io.h>
 #include <linux/of.h>
 #include <linux/of_gpio.h>
@@ -24,8 +25,14 @@ struct qe_gpio_chip {
         struct of_mm_gpio_chip mm_gc;
         spinlock_t lock;
 
+        unsigned long pin_flags[QE_PIO_PINS];
+#define QE_PIN_REQUESTED 0
+
         /* shadowed data register to clear/set bits safely */
         u32 cpdata;
+
+        /* saved_regs used to restore dedicated functions */
+        struct qe_pio_regs saved_regs;
 };
 
 static inline struct qe_gpio_chip *
@@ -40,6 +47,12 @@ static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
         struct qe_pio_regs __iomem *regs = mm_gc->regs;
 
         qe_gc->cpdata = in_be32(&regs->cpdata);
+        qe_gc->saved_regs.cpdata = qe_gc->cpdata;
+        qe_gc->saved_regs.cpdir1 = in_be32(&regs->cpdir1);
+        qe_gc->saved_regs.cpdir2 = in_be32(&regs->cpdir2);
+        qe_gc->saved_regs.cppar1 = in_be32(&regs->cppar1);
+        qe_gc->saved_regs.cppar2 = in_be32(&regs->cppar2);
+        qe_gc->saved_regs.cpodr = in_be32(&regs->cpodr);
 }
 
 static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
@@ -103,6 +116,188 @@ static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
         return 0;
 }
 
+struct qe_pin {
+        /*
+         * The qe_gpio_chip name is unfortunate, we should change that to
+         * something like qe_pio_controller. Someday.
+         */
+        struct qe_gpio_chip *controller;
+        int num;
+};
+
+/**
+ * qe_pin_request - Request a QE pin
+ * @np:         device node to get a pin from
+ * @index:      index of a pin in the device tree
+ * Context:     non-atomic
+ *
+ * This function return qe_pin so that you could use it with the rest of
+ * the QE Pin Multiplexing API.
+ */
+struct qe_pin *qe_pin_request(struct device_node *np, int index)
+{
+        struct qe_pin *qe_pin;
+        struct device_node *gc;
+        struct of_gpio_chip *of_gc = NULL;
+        struct of_mm_gpio_chip *mm_gc;
+        struct qe_gpio_chip *qe_gc;
+        int err;
+        int size;
+        const void *gpio_spec;
+        const u32 *gpio_cells;
+        unsigned long flags;
+
+        qe_pin = kzalloc(sizeof(*qe_pin), GFP_KERNEL);
+        if (!qe_pin) {
+                pr_debug("%s: can't allocate memory\n", __func__);
+                return ERR_PTR(-ENOMEM);
+        }
+
+        err = of_parse_phandles_with_args(np, "gpios", "#gpio-cells", index,
+                                          &gc, &gpio_spec);
+        if (err) {
+                pr_debug("%s: can't parse gpios property\n", __func__);
+                goto err0;
+        }
+
+        if (!of_device_is_compatible(gc, "fsl,mpc8323-qe-pario-bank")) {
+                pr_debug("%s: tried to get a non-qe pin\n", __func__);
+                err = -EINVAL;
+                goto err1;
+        }
+
+        of_gc = gc->data;
+        if (!of_gc) {
+                pr_debug("%s: gpio controller %s isn't registered\n",
+                         np->full_name, gc->full_name);
+                err = -ENODEV;
+                goto err1;
+        }
+
+        gpio_cells = of_get_property(gc, "#gpio-cells", &size);
+        if (!gpio_cells || size != sizeof(*gpio_cells) ||
+                        *gpio_cells != of_gc->gpio_cells) {
+                pr_debug("%s: wrong #gpio-cells for %s\n",
+                         np->full_name, gc->full_name);
+                err = -EINVAL;
+                goto err1;
+        }
+
+        err = of_gc->xlate(of_gc, np, gpio_spec, NULL);
+        if (err < 0)
+                goto err1;
+
+        mm_gc = to_of_mm_gpio_chip(&of_gc->gc);
+        qe_gc = to_qe_gpio_chip(mm_gc);
+
+        spin_lock_irqsave(&qe_gc->lock, flags);
+
+        if (test_and_set_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[err]) == 0) {
+                qe_pin->controller = qe_gc;
+                qe_pin->num = err;
+                err = 0;
+        } else {
+                err = -EBUSY;
+        }
+
+        spin_unlock_irqrestore(&qe_gc->lock, flags);
+
+        if (!err)
+                return qe_pin;
+err1:
+        of_node_put(gc);
+err0:
+        kfree(qe_pin);
+        pr_debug("%s failed with status %d\n", __func__, err);
+        return ERR_PTR(err);
+}
+EXPORT_SYMBOL(qe_pin_request);
+
+/**
+ * qe_pin_free - Free a pin
+ * @qe_pin:     pointer to the qe_pin structure
+ * Context:     any
+ *
+ * This function frees the qe_pin structure and makes a pin available
+ * for further qe_pin_request() calls.
+ */
+void qe_pin_free(struct qe_pin *qe_pin)
+{
+        struct qe_gpio_chip *qe_gc = qe_pin->controller;
+        unsigned long flags;
+        const int pin = qe_pin->num;
+
+        spin_lock_irqsave(&qe_gc->lock, flags);
+        test_and_clear_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[pin]);
+        spin_unlock_irqrestore(&qe_gc->lock, flags);
+
+        kfree(qe_pin);
+}
+EXPORT_SYMBOL(qe_pin_free);
+
+/**
+ * qe_pin_set_dedicated - Revert a pin to a dedicated peripheral function mode
+ * @qe_pin:     pointer to the qe_pin structure
+ * Context:     any
+ *
+ * This function resets a pin to a dedicated peripheral function that
+ * has been set up by the firmware.
+ */
+void qe_pin_set_dedicated(struct qe_pin *qe_pin)
+{
+        struct qe_gpio_chip *qe_gc = qe_pin->controller;
+        struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
+        struct qe_pio_regs *sregs = &qe_gc->saved_regs;
+        int pin = qe_pin->num;
+        u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1));
+        u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2);
+        bool second_reg = pin > (QE_PIO_PINS / 2) - 1;
+        unsigned long flags;
+
+        spin_lock_irqsave(&qe_gc->lock, flags);
+
+        if (second_reg) {
+                clrsetbits_be32(&regs->cpdir2, mask2, sregs->cpdir2 & mask2);
+                clrsetbits_be32(&regs->cppar2, mask2, sregs->cppar2 & mask2);
+        } else {
+                clrsetbits_be32(&regs->cpdir1, mask2, sregs->cpdir1 & mask2);
+                clrsetbits_be32(&regs->cppar1, mask2, sregs->cppar1 & mask2);
+        }
+
+        if (sregs->cpdata & mask1)
+                qe_gc->cpdata |= mask1;
+        else
+                qe_gc->cpdata &= ~mask1;
+
+        out_be32(&regs->cpdata, qe_gc->cpdata);
+        clrsetbits_be32(&regs->cpodr, mask1, sregs->cpodr & mask1);
+
+        spin_unlock_irqrestore(&qe_gc->lock, flags);
+}
+EXPORT_SYMBOL(qe_pin_set_dedicated);
+
+/**
+ * qe_pin_set_gpio - Set a pin to the GPIO mode
+ * @qe_pin:     pointer to the qe_pin structure
+ * Context:     any
+ *
+ * This function sets a pin to the GPIO mode.
+ */
+void qe_pin_set_gpio(struct qe_pin *qe_pin)
+{
+        struct qe_gpio_chip *qe_gc = qe_pin->controller;
+        struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
+        unsigned long flags;
+
+        spin_lock_irqsave(&qe_gc->lock, flags);
+
+        /* Let's make it input by default, GPIO API is able to change that. */
+        __par_io_config_pin(regs, qe_pin->num, QE_PIO_DIR_IN, 0, 0, 0);
+
+        spin_unlock_irqrestore(&qe_gc->lock, flags);
+}
+EXPORT_SYMBOL(qe_pin_set_gpio);
+
 static int __init qe_add_gpiochips(void)
 {
         struct device_node *np;
diff --git a/arch/powerpc/sysdev/simple_gpio.c b/arch/powerpc/sysdev/simple_gpio.c
new file mode 100644
index 00000000000..43c4569e24b
--- /dev/null
+++ b/arch/powerpc/sysdev/simple_gpio.c
@@ -0,0 +1,155 @@
+/*
+ * Simple Memory-Mapped GPIOs
+ *
+ * Copyright (c) MontaVista Software, Inc. 2008.
+ *
+ * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+#include <linux/ioport.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_gpio.h>
+#include <linux/gpio.h>
+#include <asm/prom.h>
+#include "simple_gpio.h"
+
+struct u8_gpio_chip {
+        struct of_mm_gpio_chip mm_gc;
+        spinlock_t lock;
+
+        /* shadowed data register to clear/set bits safely */
+        u8 data;
+};
+
+static struct u8_gpio_chip *to_u8_gpio_chip(struct of_mm_gpio_chip *mm_gc)
+{
+        return container_of(mm_gc, struct u8_gpio_chip, mm_gc);
+}
+
+static u8 u8_pin2mask(unsigned int pin)
+{
+        return 1 << (8 - 1 - pin);
+}
+
+static int u8_gpio_get(struct gpio_chip *gc, unsigned int gpio)
+{
+        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+
+        return in_8(mm_gc->regs) & u8_pin2mask(gpio);
+}
+
+static void u8_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
+{
+        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+        struct u8_gpio_chip *u8_gc = to_u8_gpio_chip(mm_gc);
+        unsigned long flags;
+
+        spin_lock_irqsave(&u8_gc->lock, flags);
+
+        if (val)
+                u8_gc->data |= u8_pin2mask(gpio);
+        else
+                u8_gc->data &= ~u8_pin2mask(gpio);
+
+        out_8(mm_gc->regs, u8_gc->data);
+
+        spin_unlock_irqrestore(&u8_gc->lock, flags);
+}
+
+static int u8_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
+{
+        return 0;
+}
+
+static int u8_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
+{
+        u8_gpio_set(gc, gpio, val);
+        return 0;
+}
+
+static void u8_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
+{
+        struct u8_gpio_chip *u8_gc = to_u8_gpio_chip(mm_gc);
+
+        u8_gc->data = in_8(mm_gc->regs);
+}
+
+static int __init u8_simple_gpiochip_add(struct device_node *np)
+{
+        int ret;
+        struct u8_gpio_chip *u8_gc;
+        struct of_mm_gpio_chip *mm_gc;
+        struct of_gpio_chip *of_gc;
+        struct gpio_chip *gc;
+
+        u8_gc = kzalloc(sizeof(*u8_gc), GFP_KERNEL);
+        if (!u8_gc)
+                return -ENOMEM;
+
+        spin_lock_init(&u8_gc->lock);
+
+        mm_gc = &u8_gc->mm_gc;
+        of_gc = &mm_gc->of_gc;
+        gc = &of_gc->gc;
+
+        mm_gc->save_regs = u8_gpio_save_regs;
+        of_gc->gpio_cells = 2;
+        gc->ngpio = 8;
+        gc->direction_input = u8_gpio_dir_in;
+        gc->direction_output = u8_gpio_dir_out;
+        gc->get = u8_gpio_get;
+        gc->set = u8_gpio_set;
+
+        ret = of_mm_gpiochip_add(np, mm_gc);
+        if (ret)
+                goto err;
+        return 0;
+err:
+        kfree(u8_gc);
+        return ret;
+}
+
+void __init simple_gpiochip_init(const char *compatible)
+{
+        struct device_node *np;
+
+        for_each_compatible_node(np, NULL, compatible) {
+                int ret;
+                struct resource r;
+
+                ret = of_address_to_resource(np, 0, &r);
+                if (ret)
+                        goto err;
+
+                switch (resource_size(&r)) {
+                case 1:
+                        ret = u8_simple_gpiochip_add(np);
+                        if (ret)
+                                goto err;
+                        break;
+                default:
+                        /*
+                         * Whenever you need support for GPIO bank width > 1,
+                         * please just turn u8_ code into huge macros, and
+                         * construct needed uX_ code with it.
+                         */
+                        ret = -ENOSYS;
+                        goto err;
+                }
+                continue;
+err:
+                pr_err("%s: registration failed, status %d\n",
+                       np->full_name, ret);
+        }
+}
diff --git a/arch/powerpc/sysdev/simple_gpio.h b/arch/powerpc/sysdev/simple_gpio.h
new file mode 100644
index 00000000000..3a7b0c513c7
--- /dev/null
+++ b/arch/powerpc/sysdev/simple_gpio.h
@@ -0,0 +1,12 @@
+#ifndef __SYSDEV_SIMPLE_GPIO_H
+#define __SYSDEV_SIMPLE_GPIO_H
+
+#include <linux/errno.h>
+
+#ifdef CONFIG_SIMPLE_GPIO
+extern void simple_gpiochip_init(const char *compatible);
+#else
+static inline void simple_gpiochip_init(const char *compatible) {}
+#endif /* CONFIG_SIMPLE_GPIO */
+
+#endif /* __SYSDEV_SIMPLE_GPIO_H */