diff options
author | Stephen Rothwell <sfr@canb.auug.org.au> | 2007-12-06 09:49:27 -0500 |
---|---|---|
committer | Paul Mackerras <paulus@samba.org> | 2007-12-10 21:42:19 -0500 |
commit | 7a73bd7f06dad5c466c5f3a4712696a3932a428b (patch) | |
tree | d61bd46a9c044ef4a1a24798f18768d8db1acad7 /arch/powerpc/platforms/iseries/pci.c | |
parent | b9b1812cad14bf921409a76a444a015d22774639 (diff) |
[POWERPC] iSeries: DeCamelCase pci.c
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc/platforms/iseries/pci.c')
-rw-r--r-- | arch/powerpc/platforms/iseries/pci.c | 216 |
1 files changed, 108 insertions, 108 deletions
diff --git a/arch/powerpc/platforms/iseries/pci.c b/arch/powerpc/platforms/iseries/pci.c index 8ef322601f2..705f52c7ce5 100644 --- a/arch/powerpc/platforms/iseries/pci.c +++ b/arch/powerpc/platforms/iseries/pci.c | |||
@@ -138,19 +138,19 @@ static void __init allocate_device_bars(struct pci_dev *dev) | |||
138 | * PCI: Read Vendor Failed 0x18.58.10 Rc: 0x00xx | 138 | * PCI: Read Vendor Failed 0x18.58.10 Rc: 0x00xx |
139 | * PCI: Connect Bus Unit Failed 0x18.58.10 Rc: 0x00xx | 139 | * PCI: Connect Bus Unit Failed 0x18.58.10 Rc: 0x00xx |
140 | */ | 140 | */ |
141 | static void pci_Log_Error(char *Error_Text, int Bus, int SubBus, | 141 | static void pci_log_error(char *error, int bus, int subbus, |
142 | int AgentId, int HvRc) | 142 | int agent, int hv_res) |
143 | { | 143 | { |
144 | if (HvRc == 0x0302) | 144 | if (hv_res == 0x0302) |
145 | return; | 145 | return; |
146 | printk(KERN_ERR "PCI: %s Failed: 0x%02X.%02X.%02X Rc: 0x%04X", | 146 | printk(KERN_ERR "PCI: %s Failed: 0x%02X.%02X.%02X Rc: 0x%04X", |
147 | Error_Text, Bus, SubBus, AgentId, HvRc); | 147 | error, bus, subbus, agent, hv_res); |
148 | } | 148 | } |
149 | 149 | ||
150 | /* | 150 | /* |
151 | * Look down the chain to find the matching Device Device | 151 | * Look down the chain to find the matching Device Device |
152 | */ | 152 | */ |
153 | static struct device_node *find_Device_Node(int bus, int devfn) | 153 | static struct device_node *find_device_node(int bus, int devfn) |
154 | { | 154 | { |
155 | struct device_node *node; | 155 | struct device_node *node; |
156 | 156 | ||
@@ -170,14 +170,14 @@ void __init iSeries_pci_final_fixup(void) | |||
170 | { | 170 | { |
171 | struct pci_dev *pdev = NULL; | 171 | struct pci_dev *pdev = NULL; |
172 | struct device_node *node; | 172 | struct device_node *node; |
173 | int DeviceCount = 0; | 173 | int num_dev = 0; |
174 | 174 | ||
175 | /* Fix up at the device node and pci_dev relationship */ | 175 | /* Fix up at the device node and pci_dev relationship */ |
176 | mf_display_src(0xC9000100); | 176 | mf_display_src(0xC9000100); |
177 | 177 | ||
178 | printk("pcibios_final_fixup\n"); | 178 | printk("pcibios_final_fixup\n"); |
179 | for_each_pci_dev(pdev) { | 179 | for_each_pci_dev(pdev) { |
180 | node = find_Device_Node(pdev->bus->number, pdev->devfn); | 180 | node = find_device_node(pdev->bus->number, pdev->devfn); |
181 | printk("pci dev %p (%x.%x), node %p\n", pdev, | 181 | printk("pci dev %p (%x.%x), node %p\n", pdev, |
182 | pdev->bus->number, pdev->devfn, node); | 182 | pdev->bus->number, pdev->devfn, node); |
183 | 183 | ||
@@ -194,7 +194,7 @@ void __init iSeries_pci_final_fixup(void) | |||
194 | err = HvCallXm_connectBusUnit(pdn->busno, pdn->bussubno, | 194 | err = HvCallXm_connectBusUnit(pdn->busno, pdn->bussubno, |
195 | *agent, irq); | 195 | *agent, irq); |
196 | if (err) | 196 | if (err) |
197 | pci_Log_Error("Connect Bus Unit", | 197 | pci_log_error("Connect Bus Unit", |
198 | pdn->busno, pdn->bussubno, *agent, err); | 198 | pdn->busno, pdn->bussubno, *agent, err); |
199 | else { | 199 | else { |
200 | err = HvCallPci_configStore8(pdn->busno, pdn->bussubno, | 200 | err = HvCallPci_configStore8(pdn->busno, pdn->bussubno, |
@@ -202,18 +202,18 @@ void __init iSeries_pci_final_fixup(void) | |||
202 | PCI_INTERRUPT_LINE, | 202 | PCI_INTERRUPT_LINE, |
203 | irq); | 203 | irq); |
204 | if (err) | 204 | if (err) |
205 | pci_Log_Error("PciCfgStore Irq Failed!", | 205 | pci_log_error("PciCfgStore Irq Failed!", |
206 | pdn->busno, pdn->bussubno, *agent, err); | 206 | pdn->busno, pdn->bussubno, *agent, err); |
207 | } | 207 | } |
208 | if (!err) | 208 | if (!err) |
209 | pdev->irq = irq; | 209 | pdev->irq = irq; |
210 | } | 210 | } |
211 | 211 | ||
212 | ++DeviceCount; | 212 | ++num_dev; |
213 | pdev->sysdata = (void *)node; | 213 | pdev->sysdata = (void *)node; |
214 | PCI_DN(node)->pcidev = pdev; | 214 | PCI_DN(node)->pcidev = pdev; |
215 | allocate_device_bars(pdev); | 215 | allocate_device_bars(pdev); |
216 | iSeries_Device_Information(pdev, DeviceCount); | 216 | iSeries_Device_Information(pdev, num_dev); |
217 | iommu_devnode_init_iSeries(pdev, node); | 217 | iommu_devnode_init_iSeries(pdev, node); |
218 | } else | 218 | } else |
219 | printk("PCI: Device Tree not found for 0x%016lX\n", | 219 | printk("PCI: Device Tree not found for 0x%016lX\n", |
@@ -229,13 +229,13 @@ void __init iSeries_pci_final_fixup(void) | |||
229 | * Sanity Check Node PciDev to passed pci_dev | 229 | * Sanity Check Node PciDev to passed pci_dev |
230 | * If none is found, returns a NULL which the client must handle. | 230 | * If none is found, returns a NULL which the client must handle. |
231 | */ | 231 | */ |
232 | static struct device_node *get_Device_Node(struct pci_dev *pdev) | 232 | static struct device_node *get_device_node(struct pci_dev *pdev) |
233 | { | 233 | { |
234 | struct device_node *node; | 234 | struct device_node *node; |
235 | 235 | ||
236 | node = pdev->sysdata; | 236 | node = pdev->sysdata; |
237 | if (node == NULL || PCI_DN(node)->pcidev != pdev) | 237 | if (node == NULL || PCI_DN(node)->pcidev != pdev) |
238 | node = find_Device_Node(pdev->bus->number, pdev->devfn); | 238 | node = find_device_node(pdev->bus->number, pdev->devfn); |
239 | return node; | 239 | return node; |
240 | } | 240 | } |
241 | #endif | 241 | #endif |
@@ -262,7 +262,7 @@ static u64 hv_cfg_write_func[4] = { | |||
262 | static int iSeries_pci_read_config(struct pci_bus *bus, unsigned int devfn, | 262 | static int iSeries_pci_read_config(struct pci_bus *bus, unsigned int devfn, |
263 | int offset, int size, u32 *val) | 263 | int offset, int size, u32 *val) |
264 | { | 264 | { |
265 | struct device_node *node = find_Device_Node(bus->number, devfn); | 265 | struct device_node *node = find_device_node(bus->number, devfn); |
266 | u64 fn; | 266 | u64 fn; |
267 | struct HvCallPci_LoadReturn ret; | 267 | struct HvCallPci_LoadReturn ret; |
268 | 268 | ||
@@ -292,7 +292,7 @@ static int iSeries_pci_read_config(struct pci_bus *bus, unsigned int devfn, | |||
292 | static int iSeries_pci_write_config(struct pci_bus *bus, unsigned int devfn, | 292 | static int iSeries_pci_write_config(struct pci_bus *bus, unsigned int devfn, |
293 | int offset, int size, u32 val) | 293 | int offset, int size, u32 val) |
294 | { | 294 | { |
295 | struct device_node *node = find_Device_Node(bus->number, devfn); | 295 | struct device_node *node = find_device_node(bus->number, devfn); |
296 | u64 fn; | 296 | u64 fn; |
297 | u64 ret; | 297 | u64 ret; |
298 | 298 | ||
@@ -324,15 +324,15 @@ static struct pci_ops iSeries_pci_ops = { | |||
324 | * PCI: Device 23.90 ReadL Retry( 1) | 324 | * PCI: Device 23.90 ReadL Retry( 1) |
325 | * PCI: Device 23.90 ReadL Retry Successful(1) | 325 | * PCI: Device 23.90 ReadL Retry Successful(1) |
326 | */ | 326 | */ |
327 | static int CheckReturnCode(char *TextHdr, struct device_node *DevNode, | 327 | static int check_return_code(char *type, struct device_node *dn, |
328 | int *retry, u64 ret) | 328 | int *retry, u64 ret) |
329 | { | 329 | { |
330 | if (ret != 0) { | 330 | if (ret != 0) { |
331 | struct pci_dn *pdn = PCI_DN(DevNode); | 331 | struct pci_dn *pdn = PCI_DN(dn); |
332 | 332 | ||
333 | (*retry)++; | 333 | (*retry)++; |
334 | printk("PCI: %s: Device 0x%04X:%02X I/O Error(%2d): 0x%04X\n", | 334 | printk("PCI: %s: Device 0x%04X:%02X I/O Error(%2d): 0x%04X\n", |
335 | TextHdr, pdn->busno, pdn->devfn, | 335 | type, pdn->busno, pdn->devfn, |
336 | *retry, (int)ret); | 336 | *retry, (int)ret); |
337 | /* | 337 | /* |
338 | * Bump the retry and check for retry count exceeded. | 338 | * Bump the retry and check for retry count exceeded. |
@@ -356,28 +356,28 @@ static int CheckReturnCode(char *TextHdr, struct device_node *DevNode, | |||
356 | * the exposure of being device global. | 356 | * the exposure of being device global. |
357 | */ | 357 | */ |
358 | static inline struct device_node *xlate_iomm_address( | 358 | static inline struct device_node *xlate_iomm_address( |
359 | const volatile void __iomem *IoAddress, | 359 | const volatile void __iomem *addr, |
360 | u64 *dsaptr, u64 *BarOffsetPtr) | 360 | u64 *dsaptr, u64 *bar_offset) |
361 | { | 361 | { |
362 | unsigned long OrigIoAddr; | 362 | unsigned long orig_addr; |
363 | unsigned long BaseIoAddr; | 363 | unsigned long base_addr; |
364 | unsigned long TableIndex; | 364 | unsigned long ind; |
365 | struct device_node *DevNode; | 365 | struct device_node *dn; |
366 | 366 | ||
367 | OrigIoAddr = (unsigned long __force)IoAddress; | 367 | orig_addr = (unsigned long __force)addr; |
368 | if ((OrigIoAddr < BASE_IO_MEMORY) || (OrigIoAddr >= max_io_memory)) | 368 | if ((orig_addr < BASE_IO_MEMORY) || (orig_addr >= max_io_memory)) |
369 | return NULL; | 369 | return NULL; |
370 | BaseIoAddr = OrigIoAddr - BASE_IO_MEMORY; | 370 | base_addr = orig_addr - BASE_IO_MEMORY; |
371 | TableIndex = BaseIoAddr / IOMM_TABLE_ENTRY_SIZE; | 371 | ind = base_addr / IOMM_TABLE_ENTRY_SIZE; |
372 | DevNode = iomm_table[TableIndex]; | 372 | dn = iomm_table[ind]; |
373 | 373 | ||
374 | if (DevNode != NULL) { | 374 | if (dn != NULL) { |
375 | int barnum = iobar_table[TableIndex]; | 375 | int barnum = iobar_table[ind]; |
376 | *dsaptr = iseries_ds_addr(DevNode) | (barnum << 24); | 376 | *dsaptr = iseries_ds_addr(dn) | (barnum << 24); |
377 | *BarOffsetPtr = BaseIoAddr % IOMM_TABLE_ENTRY_SIZE; | 377 | *bar_offset = base_addr % IOMM_TABLE_ENTRY_SIZE; |
378 | } else | 378 | } else |
379 | panic("PCI: Invalid PCI IoAddress detected!\n"); | 379 | panic("PCI: Invalid PCI IO address detected!\n"); |
380 | return DevNode; | 380 | return dn; |
381 | } | 381 | } |
382 | 382 | ||
383 | /* | 383 | /* |
@@ -385,16 +385,16 @@ static inline struct device_node *xlate_iomm_address( | |||
385 | * On MM I/O error, all ones are returned and iSeries_pci_IoError is cal | 385 | * On MM I/O error, all ones are returned and iSeries_pci_IoError is cal |
386 | * else, data is returned in Big Endian format. | 386 | * else, data is returned in Big Endian format. |
387 | */ | 387 | */ |
388 | static u8 iSeries_Read_Byte(const volatile void __iomem *IoAddress) | 388 | static u8 iSeries_read_byte(const volatile void __iomem *addr) |
389 | { | 389 | { |
390 | u64 BarOffset; | 390 | u64 bar_offset; |
391 | u64 dsa; | 391 | u64 dsa; |
392 | int retry = 0; | 392 | int retry = 0; |
393 | struct HvCallPci_LoadReturn ret; | 393 | struct HvCallPci_LoadReturn ret; |
394 | struct device_node *DevNode = | 394 | struct device_node *dn = |
395 | xlate_iomm_address(IoAddress, &dsa, &BarOffset); | 395 | xlate_iomm_address(addr, &dsa, &bar_offset); |
396 | 396 | ||
397 | if (DevNode == NULL) { | 397 | if (dn == NULL) { |
398 | static unsigned long last_jiffies; | 398 | static unsigned long last_jiffies; |
399 | static int num_printed; | 399 | static int num_printed; |
400 | 400 | ||
@@ -403,27 +403,27 @@ static u8 iSeries_Read_Byte(const volatile void __iomem *IoAddress) | |||
403 | num_printed = 0; | 403 | num_printed = 0; |
404 | } | 404 | } |
405 | if (num_printed++ < 10) | 405 | if (num_printed++ < 10) |
406 | printk(KERN_ERR "iSeries_Read_Byte: invalid access at IO address %p\n", | 406 | printk(KERN_ERR "iSeries_read_byte: invalid access at IO address %p\n", |
407 | IoAddress); | 407 | addr); |
408 | return 0xff; | 408 | return 0xff; |
409 | } | 409 | } |
410 | do { | 410 | do { |
411 | HvCall3Ret16(HvCallPciBarLoad8, &ret, dsa, BarOffset, 0); | 411 | HvCall3Ret16(HvCallPciBarLoad8, &ret, dsa, bar_offset, 0); |
412 | } while (CheckReturnCode("RDB", DevNode, &retry, ret.rc) != 0); | 412 | } while (check_return_code("RDB", dn, &retry, ret.rc) != 0); |
413 | 413 | ||
414 | return ret.value; | 414 | return ret.value; |
415 | } | 415 | } |
416 | 416 | ||
417 | static u16 iSeries_Read_Word(const volatile void __iomem *IoAddress) | 417 | static u16 iSeries_read_word(const volatile void __iomem *addr) |
418 | { | 418 | { |
419 | u64 BarOffset; | 419 | u64 bar_offset; |
420 | u64 dsa; | 420 | u64 dsa; |
421 | int retry = 0; | 421 | int retry = 0; |
422 | struct HvCallPci_LoadReturn ret; | 422 | struct HvCallPci_LoadReturn ret; |
423 | struct device_node *DevNode = | 423 | struct device_node *dn = |
424 | xlate_iomm_address(IoAddress, &dsa, &BarOffset); | 424 | xlate_iomm_address(addr, &dsa, &bar_offset); |
425 | 425 | ||
426 | if (DevNode == NULL) { | 426 | if (dn == NULL) { |
427 | static unsigned long last_jiffies; | 427 | static unsigned long last_jiffies; |
428 | static int num_printed; | 428 | static int num_printed; |
429 | 429 | ||
@@ -432,28 +432,28 @@ static u16 iSeries_Read_Word(const volatile void __iomem *IoAddress) | |||
432 | num_printed = 0; | 432 | num_printed = 0; |
433 | } | 433 | } |
434 | if (num_printed++ < 10) | 434 | if (num_printed++ < 10) |
435 | printk(KERN_ERR "iSeries_Read_Word: invalid access at IO address %p\n", | 435 | printk(KERN_ERR "iSeries_read_word: invalid access at IO address %p\n", |
436 | IoAddress); | 436 | addr); |
437 | return 0xffff; | 437 | return 0xffff; |
438 | } | 438 | } |
439 | do { | 439 | do { |
440 | HvCall3Ret16(HvCallPciBarLoad16, &ret, dsa, | 440 | HvCall3Ret16(HvCallPciBarLoad16, &ret, dsa, |
441 | BarOffset, 0); | 441 | bar_offset, 0); |
442 | } while (CheckReturnCode("RDW", DevNode, &retry, ret.rc) != 0); | 442 | } while (check_return_code("RDW", dn, &retry, ret.rc) != 0); |
443 | 443 | ||
444 | return ret.value; | 444 | return ret.value; |
445 | } | 445 | } |
446 | 446 | ||
447 | static u32 iSeries_Read_Long(const volatile void __iomem *IoAddress) | 447 | static u32 iSeries_read_long(const volatile void __iomem *addr) |
448 | { | 448 | { |
449 | u64 BarOffset; | 449 | u64 bar_offset; |
450 | u64 dsa; | 450 | u64 dsa; |
451 | int retry = 0; | 451 | int retry = 0; |
452 | struct HvCallPci_LoadReturn ret; | 452 | struct HvCallPci_LoadReturn ret; |
453 | struct device_node *DevNode = | 453 | struct device_node *dn = |
454 | xlate_iomm_address(IoAddress, &dsa, &BarOffset); | 454 | xlate_iomm_address(addr, &dsa, &bar_offset); |
455 | 455 | ||
456 | if (DevNode == NULL) { | 456 | if (dn == NULL) { |
457 | static unsigned long last_jiffies; | 457 | static unsigned long last_jiffies; |
458 | static int num_printed; | 458 | static int num_printed; |
459 | 459 | ||
@@ -462,14 +462,14 @@ static u32 iSeries_Read_Long(const volatile void __iomem *IoAddress) | |||
462 | num_printed = 0; | 462 | num_printed = 0; |
463 | } | 463 | } |
464 | if (num_printed++ < 10) | 464 | if (num_printed++ < 10) |
465 | printk(KERN_ERR "iSeries_Read_Long: invalid access at IO address %p\n", | 465 | printk(KERN_ERR "iSeries_read_long: invalid access at IO address %p\n", |
466 | IoAddress); | 466 | addr); |
467 | return 0xffffffff; | 467 | return 0xffffffff; |
468 | } | 468 | } |
469 | do { | 469 | do { |
470 | HvCall3Ret16(HvCallPciBarLoad32, &ret, dsa, | 470 | HvCall3Ret16(HvCallPciBarLoad32, &ret, dsa, |
471 | BarOffset, 0); | 471 | bar_offset, 0); |
472 | } while (CheckReturnCode("RDL", DevNode, &retry, ret.rc) != 0); | 472 | } while (check_return_code("RDL", dn, &retry, ret.rc) != 0); |
473 | 473 | ||
474 | return ret.value; | 474 | return ret.value; |
475 | } | 475 | } |
@@ -478,16 +478,16 @@ static u32 iSeries_Read_Long(const volatile void __iomem *IoAddress) | |||
478 | * Write MM I/O Instructions for the iSeries | 478 | * Write MM I/O Instructions for the iSeries |
479 | * | 479 | * |
480 | */ | 480 | */ |
481 | static void iSeries_Write_Byte(u8 data, volatile void __iomem *IoAddress) | 481 | static void iSeries_write_byte(u8 data, volatile void __iomem *addr) |
482 | { | 482 | { |
483 | u64 BarOffset; | 483 | u64 bar_offset; |
484 | u64 dsa; | 484 | u64 dsa; |
485 | int retry = 0; | 485 | int retry = 0; |
486 | u64 rc; | 486 | u64 rc; |
487 | struct device_node *DevNode = | 487 | struct device_node *dn = |
488 | xlate_iomm_address(IoAddress, &dsa, &BarOffset); | 488 | xlate_iomm_address(addr, &dsa, &bar_offset); |
489 | 489 | ||
490 | if (DevNode == NULL) { | 490 | if (dn == NULL) { |
491 | static unsigned long last_jiffies; | 491 | static unsigned long last_jiffies; |
492 | static int num_printed; | 492 | static int num_printed; |
493 | 493 | ||
@@ -496,24 +496,24 @@ static void iSeries_Write_Byte(u8 data, volatile void __iomem *IoAddress) | |||
496 | num_printed = 0; | 496 | num_printed = 0; |
497 | } | 497 | } |
498 | if (num_printed++ < 10) | 498 | if (num_printed++ < 10) |
499 | printk(KERN_ERR "iSeries_Write_Byte: invalid access at IO address %p\n", IoAddress); | 499 | printk(KERN_ERR "iSeries_write_byte: invalid access at IO address %p\n", addr); |
500 | return; | 500 | return; |
501 | } | 501 | } |
502 | do { | 502 | do { |
503 | rc = HvCall4(HvCallPciBarStore8, dsa, BarOffset, data, 0); | 503 | rc = HvCall4(HvCallPciBarStore8, dsa, bar_offset, data, 0); |
504 | } while (CheckReturnCode("WWB", DevNode, &retry, rc) != 0); | 504 | } while (check_return_code("WWB", dn, &retry, rc) != 0); |
505 | } | 505 | } |
506 | 506 | ||
507 | static void iSeries_Write_Word(u16 data, volatile void __iomem *IoAddress) | 507 | static void iSeries_write_word(u16 data, volatile void __iomem *addr) |
508 | { | 508 | { |
509 | u64 BarOffset; | 509 | u64 bar_offset; |
510 | u64 dsa; | 510 | u64 dsa; |
511 | int retry = 0; | 511 | int retry = 0; |
512 | u64 rc; | 512 | u64 rc; |
513 | struct device_node *DevNode = | 513 | struct device_node *dn = |
514 | xlate_iomm_address(IoAddress, &dsa, &BarOffset); | 514 | xlate_iomm_address(addr, &dsa, &bar_offset); |
515 | 515 | ||
516 | if (DevNode == NULL) { | 516 | if (dn == NULL) { |
517 | static unsigned long last_jiffies; | 517 | static unsigned long last_jiffies; |
518 | static int num_printed; | 518 | static int num_printed; |
519 | 519 | ||
@@ -522,25 +522,25 @@ static void iSeries_Write_Word(u16 data, volatile void __iomem *IoAddress) | |||
522 | num_printed = 0; | 522 | num_printed = 0; |
523 | } | 523 | } |
524 | if (num_printed++ < 10) | 524 | if (num_printed++ < 10) |
525 | printk(KERN_ERR "iSeries_Write_Word: invalid access at IO address %p\n", | 525 | printk(KERN_ERR "iSeries_write_word: invalid access at IO address %p\n", |
526 | IoAddress); | 526 | addr); |
527 | return; | 527 | return; |
528 | } | 528 | } |
529 | do { | 529 | do { |
530 | rc = HvCall4(HvCallPciBarStore16, dsa, BarOffset, data, 0); | 530 | rc = HvCall4(HvCallPciBarStore16, dsa, bar_offset, data, 0); |
531 | } while (CheckReturnCode("WWW", DevNode, &retry, rc) != 0); | 531 | } while (check_return_code("WWW", dn, &retry, rc) != 0); |
532 | } | 532 | } |
533 | 533 | ||
534 | static void iSeries_Write_Long(u32 data, volatile void __iomem *IoAddress) | 534 | static void iSeries_write_long(u32 data, volatile void __iomem *addr) |
535 | { | 535 | { |
536 | u64 BarOffset; | 536 | u64 bar_offset; |
537 | u64 dsa; | 537 | u64 dsa; |
538 | int retry = 0; | 538 | int retry = 0; |
539 | u64 rc; | 539 | u64 rc; |
540 | struct device_node *DevNode = | 540 | struct device_node *dn = |
541 | xlate_iomm_address(IoAddress, &dsa, &BarOffset); | 541 | xlate_iomm_address(addr, &dsa, &bar_offset); |
542 | 542 | ||
543 | if (DevNode == NULL) { | 543 | if (dn == NULL) { |
544 | static unsigned long last_jiffies; | 544 | static unsigned long last_jiffies; |
545 | static int num_printed; | 545 | static int num_printed; |
546 | 546 | ||
@@ -549,63 +549,63 @@ static void iSeries_Write_Long(u32 data, volatile void __iomem *IoAddress) | |||
549 | num_printed = 0; | 549 | num_printed = 0; |
550 | } | 550 | } |
551 | if (num_printed++ < 10) | 551 | if (num_printed++ < 10) |
552 | printk(KERN_ERR "iSeries_Write_Long: invalid access at IO address %p\n", | 552 | printk(KERN_ERR "iSeries_write_long: invalid access at IO address %p\n", |
553 | IoAddress); | 553 | addr); |
554 | return; | 554 | return; |
555 | } | 555 | } |
556 | do { | 556 | do { |
557 | rc = HvCall4(HvCallPciBarStore32, dsa, BarOffset, data, 0); | 557 | rc = HvCall4(HvCallPciBarStore32, dsa, bar_offset, data, 0); |
558 | } while (CheckReturnCode("WWL", DevNode, &retry, rc) != 0); | 558 | } while (check_return_code("WWL", dn, &retry, rc) != 0); |
559 | } | 559 | } |
560 | 560 | ||
561 | static u8 iseries_readb(const volatile void __iomem *addr) | 561 | static u8 iseries_readb(const volatile void __iomem *addr) |
562 | { | 562 | { |
563 | return iSeries_Read_Byte(addr); | 563 | return iSeries_read_byte(addr); |
564 | } | 564 | } |
565 | 565 | ||
566 | static u16 iseries_readw(const volatile void __iomem *addr) | 566 | static u16 iseries_readw(const volatile void __iomem *addr) |
567 | { | 567 | { |
568 | return le16_to_cpu(iSeries_Read_Word(addr)); | 568 | return le16_to_cpu(iSeries_read_word(addr)); |
569 | } | 569 | } |
570 | 570 | ||
571 | static u32 iseries_readl(const volatile void __iomem *addr) | 571 | static u32 iseries_readl(const volatile void __iomem *addr) |
572 | { | 572 | { |
573 | return le32_to_cpu(iSeries_Read_Long(addr)); | 573 | return le32_to_cpu(iSeries_read_long(addr)); |
574 | } | 574 | } |
575 | 575 | ||
576 | static u16 iseries_readw_be(const volatile void __iomem *addr) | 576 | static u16 iseries_readw_be(const volatile void __iomem *addr) |
577 | { | 577 | { |
578 | return iSeries_Read_Word(addr); | 578 | return iSeries_read_word(addr); |
579 | } | 579 | } |
580 | 580 | ||
581 | static u32 iseries_readl_be(const volatile void __iomem *addr) | 581 | static u32 iseries_readl_be(const volatile void __iomem *addr) |
582 | { | 582 | { |
583 | return iSeries_Read_Long(addr); | 583 | return iSeries_read_long(addr); |
584 | } | 584 | } |
585 | 585 | ||
586 | static void iseries_writeb(u8 data, volatile void __iomem *addr) | 586 | static void iseries_writeb(u8 data, volatile void __iomem *addr) |
587 | { | 587 | { |
588 | iSeries_Write_Byte(data, addr); | 588 | iSeries_write_byte(data, addr); |
589 | } | 589 | } |
590 | 590 | ||
591 | static void iseries_writew(u16 data, volatile void __iomem *addr) | 591 | static void iseries_writew(u16 data, volatile void __iomem *addr) |
592 | { | 592 | { |
593 | iSeries_Write_Word(cpu_to_le16(data), addr); | 593 | iSeries_write_word(cpu_to_le16(data), addr); |
594 | } | 594 | } |
595 | 595 | ||
596 | static void iseries_writel(u32 data, volatile void __iomem *addr) | 596 | static void iseries_writel(u32 data, volatile void __iomem *addr) |
597 | { | 597 | { |
598 | iSeries_Write_Long(cpu_to_le32(data), addr); | 598 | iSeries_write_long(cpu_to_le32(data), addr); |
599 | } | 599 | } |
600 | 600 | ||
601 | static void iseries_writew_be(u16 data, volatile void __iomem *addr) | 601 | static void iseries_writew_be(u16 data, volatile void __iomem *addr) |
602 | { | 602 | { |
603 | iSeries_Write_Word(data, addr); | 603 | iSeries_write_word(data, addr); |
604 | } | 604 | } |
605 | 605 | ||
606 | static void iseries_writel_be(u32 data, volatile void __iomem *addr) | 606 | static void iseries_writel_be(u32 data, volatile void __iomem *addr) |
607 | { | 607 | { |
608 | iSeries_Write_Long(data, addr); | 608 | iSeries_write_long(data, addr); |
609 | } | 609 | } |
610 | 610 | ||
611 | static void iseries_readsb(const volatile void __iomem *addr, void *buf, | 611 | static void iseries_readsb(const volatile void __iomem *addr, void *buf, |
@@ -613,7 +613,7 @@ static void iseries_readsb(const volatile void __iomem *addr, void *buf, | |||
613 | { | 613 | { |
614 | u8 *dst = buf; | 614 | u8 *dst = buf; |
615 | while(count-- > 0) | 615 | while(count-- > 0) |
616 | *(dst++) = iSeries_Read_Byte(addr); | 616 | *(dst++) = iSeries_read_byte(addr); |
617 | } | 617 | } |
618 | 618 | ||
619 | static void iseries_readsw(const volatile void __iomem *addr, void *buf, | 619 | static void iseries_readsw(const volatile void __iomem *addr, void *buf, |
@@ -621,7 +621,7 @@ static void iseries_readsw(const volatile void __iomem *addr, void *buf, | |||
621 | { | 621 | { |
622 | u16 *dst = buf; | 622 | u16 *dst = buf; |
623 | while(count-- > 0) | 623 | while(count-- > 0) |
624 | *(dst++) = iSeries_Read_Word(addr); | 624 | *(dst++) = iSeries_read_word(addr); |
625 | } | 625 | } |
626 | 626 | ||
627 | static void iseries_readsl(const volatile void __iomem *addr, void *buf, | 627 | static void iseries_readsl(const volatile void __iomem *addr, void *buf, |
@@ -629,7 +629,7 @@ static void iseries_readsl(const volatile void __iomem *addr, void *buf, | |||
629 | { | 629 | { |
630 | u32 *dst = buf; | 630 | u32 *dst = buf; |
631 | while(count-- > 0) | 631 | while(count-- > 0) |
632 | *(dst++) = iSeries_Read_Long(addr); | 632 | *(dst++) = iSeries_read_long(addr); |
633 | } | 633 | } |
634 | 634 | ||
635 | static void iseries_writesb(volatile void __iomem *addr, const void *buf, | 635 | static void iseries_writesb(volatile void __iomem *addr, const void *buf, |
@@ -637,7 +637,7 @@ static void iseries_writesb(volatile void __iomem *addr, const void *buf, | |||
637 | { | 637 | { |
638 | const u8 *src = buf; | 638 | const u8 *src = buf; |
639 | while(count-- > 0) | 639 | while(count-- > 0) |
640 | iSeries_Write_Byte(*(src++), addr); | 640 | iSeries_write_byte(*(src++), addr); |
641 | } | 641 | } |
642 | 642 | ||
643 | static void iseries_writesw(volatile void __iomem *addr, const void *buf, | 643 | static void iseries_writesw(volatile void __iomem *addr, const void *buf, |
@@ -645,7 +645,7 @@ static void iseries_writesw(volatile void __iomem *addr, const void *buf, | |||
645 | { | 645 | { |
646 | const u16 *src = buf; | 646 | const u16 *src = buf; |
647 | while(count-- > 0) | 647 | while(count-- > 0) |
648 | iSeries_Write_Word(*(src++), addr); | 648 | iSeries_write_word(*(src++), addr); |
649 | } | 649 | } |
650 | 650 | ||
651 | static void iseries_writesl(volatile void __iomem *addr, const void *buf, | 651 | static void iseries_writesl(volatile void __iomem *addr, const void *buf, |
@@ -653,7 +653,7 @@ static void iseries_writesl(volatile void __iomem *addr, const void *buf, | |||
653 | { | 653 | { |
654 | const u32 *src = buf; | 654 | const u32 *src = buf; |
655 | while(count-- > 0) | 655 | while(count-- > 0) |
656 | iSeries_Write_Long(*(src++), addr); | 656 | iSeries_write_long(*(src++), addr); |
657 | } | 657 | } |
658 | 658 | ||
659 | static void iseries_memset_io(volatile void __iomem *addr, int c, | 659 | static void iseries_memset_io(volatile void __iomem *addr, int c, |
@@ -662,7 +662,7 @@ static void iseries_memset_io(volatile void __iomem *addr, int c, | |||
662 | volatile char __iomem *d = addr; | 662 | volatile char __iomem *d = addr; |
663 | 663 | ||
664 | while (n-- > 0) | 664 | while (n-- > 0) |
665 | iSeries_Write_Byte(c, d++); | 665 | iSeries_write_byte(c, d++); |
666 | } | 666 | } |
667 | 667 | ||
668 | static void iseries_memcpy_fromio(void *dest, const volatile void __iomem *src, | 668 | static void iseries_memcpy_fromio(void *dest, const volatile void __iomem *src, |
@@ -672,7 +672,7 @@ static void iseries_memcpy_fromio(void *dest, const volatile void __iomem *src, | |||
672 | const volatile char __iomem *s = src; | 672 | const volatile char __iomem *s = src; |
673 | 673 | ||
674 | while (n-- > 0) | 674 | while (n-- > 0) |
675 | *d++ = iSeries_Read_Byte(s++); | 675 | *d++ = iSeries_read_byte(s++); |
676 | } | 676 | } |
677 | 677 | ||
678 | static void iseries_memcpy_toio(volatile void __iomem *dest, const void *src, | 678 | static void iseries_memcpy_toio(volatile void __iomem *dest, const void *src, |
@@ -682,7 +682,7 @@ static void iseries_memcpy_toio(volatile void __iomem *dest, const void *src, | |||
682 | volatile char __iomem *d = dest; | 682 | volatile char __iomem *d = dest; |
683 | 683 | ||
684 | while (n-- > 0) | 684 | while (n-- > 0) |
685 | iSeries_Write_Byte(*s++, d++); | 685 | iSeries_write_byte(*s++, d++); |
686 | } | 686 | } |
687 | 687 | ||
688 | /* We only set MMIO ops. The default PIO ops will be default | 688 | /* We only set MMIO ops. The default PIO ops will be default |