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authorJon Loeliger <jdl@jdl.com>2006-06-17 18:52:45 -0400
committerPaul Mackerras <paulus@samba.org>2006-06-21 01:01:28 -0400
commit4ca4b6274c30d53d22014fb6974efe2b3e52cfdc (patch)
treef02451f8c52a056829e4bbe681f2cf3c3f4f2bf4 /arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
parentee0339f205d60375c5ce1653c0dc318c6ec72668 (diff)
[POWERPC] Add the MPC8641 HPCN platform files.
Signed-off-by: Xianghua Xiao <x.xiao@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Wei Zhang <Wei.Zhang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc/platforms/86xx/mpc86xx_hpcn.c')
-rw-r--r--arch/powerpc/platforms/86xx/mpc86xx_hpcn.c326
1 files changed, 326 insertions, 0 deletions
diff --git a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
new file mode 100644
index 00000000000..483c21df181
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
@@ -0,0 +1,326 @@
1/*
2 * MPC86xx HPCN board specific routines
3 *
4 * Recode: ZHANG WEI <wei.zhang@freescale.com>
5 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
6 *
7 * Copyright 2006 Freescale Semiconductor Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#include <linux/config.h>
16#include <linux/stddef.h>
17#include <linux/kernel.h>
18#include <linux/pci.h>
19#include <linux/kdev_t.h>
20#include <linux/delay.h>
21#include <linux/seq_file.h>
22#include <linux/root_dev.h>
23
24#include <asm/system.h>
25#include <asm/time.h>
26#include <asm/machdep.h>
27#include <asm/pci-bridge.h>
28#include <asm/mpc86xx.h>
29#include <asm/prom.h>
30#include <mm/mmu_decl.h>
31#include <asm/udbg.h>
32#include <asm/i8259.h>
33
34#include <asm/mpic.h>
35
36#include <sysdev/fsl_soc.h>
37
38#include "mpc86xx.h"
39
40#ifndef CONFIG_PCI
41unsigned long isa_io_base = 0;
42unsigned long isa_mem_base = 0;
43unsigned long pci_dram_offset = 0;
44#endif
45
46
47/*
48 * Internal interrupts are all Level Sensitive, and Positive Polarity
49 */
50
51static u_char mpc86xx_hpcn_openpic_initsenses[] __initdata = {
52 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0: Reserved */
53 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1: MCM */
54 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2: DDR DRAM */
55 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3: LBIU */
56 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4: DMA 0 */
57 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5: DMA 1 */
58 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6: DMA 2 */
59 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7: DMA 3 */
60 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8: PCIE1 */
61 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9: PCIE2 */
62 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10: Reserved */
63 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11: Reserved */
64 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12: DUART2 */
65 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13: TSEC 1 Transmit */
66 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14: TSEC 1 Receive */
67 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15: TSEC 3 transmit */
68 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16: TSEC 3 receive */
69 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17: TSEC 3 error */
70 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18: TSEC 1 Receive/Transmit Error */
71 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19: TSEC 2 Transmit */
72 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20: TSEC 2 Receive */
73 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21: TSEC 4 transmit */
74 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22: TSEC 4 receive */
75 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23: TSEC 4 error */
76 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24: TSEC 2 Receive/Transmit Error */
77 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25: Unused */
78 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26: DUART1 */
79 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27: I2C */
80 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28: Performance Monitor */
81 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29: Unused */
82 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30: Unused */
83 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31: Unused */
84 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 32: SRIO error/write-port unit */
85 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 33: SRIO outbound doorbell */
86 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 34: SRIO inbound doorbell */
87 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 35: Unused */
88 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 36: Unused */
89 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 37: SRIO outbound message unit 1 */
90 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 38: SRIO inbound message unit 1 */
91 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 39: SRIO outbound message unit 2 */
92 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 40: SRIO inbound message unit 2 */
93 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 41: Unused */
94 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 42: Unused */
95 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 43: Unused */
96 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 44: Unused */
97 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 45: Unused */
98 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 46: Unused */
99 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 47: Unused */
100 0x0, /* External 0: */
101 0x0, /* External 1: */
102 0x0, /* External 2: */
103 0x0, /* External 3: */
104 0x0, /* External 4: */
105 0x0, /* External 5: */
106 0x0, /* External 6: */
107 0x0, /* External 7: */
108 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 8: Pixis FPGA */
109 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* External 9: ULI 8259 INTR Cascade */
110 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 10: Quad ETH PHY */
111 0x0, /* External 11: */
112 0x0,
113 0x0,
114 0x0,
115 0x0,
116};
117
118
119void __init
120mpc86xx_hpcn_init_irq(void)
121{
122 struct mpic *mpic1;
123 phys_addr_t openpic_paddr;
124
125 /* Determine the Physical Address of the OpenPIC regs */
126 openpic_paddr = get_immrbase() + MPC86xx_OPENPIC_OFFSET;
127
128 /* Alloc mpic structure and per isu has 16 INT entries. */
129 mpic1 = mpic_alloc(openpic_paddr,
130 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
131 16, MPC86xx_OPENPIC_IRQ_OFFSET, 0, 250,
132 mpc86xx_hpcn_openpic_initsenses,
133 sizeof(mpc86xx_hpcn_openpic_initsenses),
134 " MPIC ");
135 BUG_ON(mpic1 == NULL);
136
137 /* 48 Internal Interrupts */
138 mpic_assign_isu(mpic1, 0, openpic_paddr + 0x10200);
139 mpic_assign_isu(mpic1, 1, openpic_paddr + 0x10400);
140 mpic_assign_isu(mpic1, 2, openpic_paddr + 0x10600);
141
142 /* 16 External interrupts */
143 mpic_assign_isu(mpic1, 3, openpic_paddr + 0x10000);
144
145 mpic_init(mpic1);
146
147#ifdef CONFIG_PCI
148 mpic_setup_cascade(MPC86xx_IRQ_EXT9, i8259_irq_cascade, NULL);
149 i8259_init(0, I8259_OFFSET);
150#endif
151}
152
153
154
155#ifdef CONFIG_PCI
156/*
157 * interrupt routing
158 */
159
160int
161mpc86xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
162{
163 static char pci_irq_table[][4] = {
164 /*
165 * PCI IDSEL/INTPIN->INTLINE
166 * A B C D
167 */
168 {PIRQA, PIRQB, PIRQC, PIRQD}, /* IDSEL 17 -- PCI Slot 1 */
169 {PIRQB, PIRQC, PIRQD, PIRQA}, /* IDSEL 18 -- PCI Slot 2 */
170 {0, 0, 0, 0}, /* IDSEL 19 */
171 {0, 0, 0, 0}, /* IDSEL 20 */
172 {0, 0, 0, 0}, /* IDSEL 21 */
173 {0, 0, 0, 0}, /* IDSEL 22 */
174 {0, 0, 0, 0}, /* IDSEL 23 */
175 {0, 0, 0, 0}, /* IDSEL 24 */
176 {0, 0, 0, 0}, /* IDSEL 25 */
177 {PIRQD, PIRQA, PIRQB, PIRQC}, /* IDSEL 26 -- PCI Bridge*/
178 {PIRQC, 0, 0, 0}, /* IDSEL 27 -- LAN */
179 {PIRQE, PIRQF, PIRQH, PIRQ7}, /* IDSEL 28 -- USB 1.1 */
180 {PIRQE, PIRQF, PIRQG, 0}, /* IDSEL 29 -- Audio & Modem */
181 {PIRQH, 0, 0, 0}, /* IDSEL 30 -- LPC & PMU*/
182 {PIRQD, 0, 0, 0}, /* IDSEL 31 -- ATA */
183 };
184
185 const long min_idsel = 17, max_idsel = 31, irqs_per_slot = 4;
186 return PCI_IRQ_TABLE_LOOKUP + I8259_OFFSET;
187}
188
189
190int
191mpc86xx_exclude_device(u_char bus, u_char devfn)
192{
193#if !defined(CONFIG_PCI)
194 if (bus == 0 && PCI_SLOT(devfn) == 0)
195 return PCIBIOS_DEVICE_NOT_FOUND;
196#endif
197
198 return PCIBIOS_SUCCESSFUL;
199}
200#endif /* CONFIG_PCI */
201
202
203static void __init
204mpc86xx_hpcn_setup_arch(void)
205{
206 struct device_node *np;
207
208 if (ppc_md.progress)
209 ppc_md.progress("mpc86xx_hpcn_setup_arch()", 0);
210
211 np = of_find_node_by_type(NULL, "cpu");
212 if (np != 0) {
213 unsigned int *fp;
214
215 fp = (int *)get_property(np, "clock-frequency", NULL);
216 if (fp != 0)
217 loops_per_jiffy = *fp / HZ;
218 else
219 loops_per_jiffy = 50000000 / HZ;
220 of_node_put(np);
221 }
222
223#ifdef CONFIG_PCI
224 for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
225 add_bridge(np);
226
227 ppc_md.pci_swizzle = common_swizzle;
228 ppc_md.pci_map_irq = mpc86xx_map_irq;
229 ppc_md.pci_exclude_device = mpc86xx_exclude_device;
230#endif
231
232 printk("MPC86xx HPCN board from Freescale Semiconductor\n");
233
234#ifdef CONFIG_ROOT_NFS
235 ROOT_DEV = Root_NFS;
236#else
237 ROOT_DEV = Root_HDA1;
238#endif
239
240#ifdef CONFIG_SMP
241 mpc86xx_smp_init();
242#endif
243}
244
245
246void
247mpc86xx_hpcn_show_cpuinfo(struct seq_file *m)
248{
249 struct device_node *root;
250 uint memsize = total_memory;
251 const char *model = "";
252 uint svid = mfspr(SPRN_SVR);
253
254 seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
255
256 root = of_find_node_by_path("/");
257 if (root)
258 model = get_property(root, "model", NULL);
259 seq_printf(m, "Machine\t\t: %s\n", model);
260 of_node_put(root);
261
262 seq_printf(m, "SVR\t\t: 0x%x\n", svid);
263 seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
264}
265
266
267/*
268 * Called very early, device-tree isn't unflattened
269 */
270static int __init mpc86xx_hpcn_probe(void)
271{
272 unsigned long root = of_get_flat_dt_root();
273
274 if (of_flat_dt_is_compatible(root, "mpc86xx"))
275 return 1; /* Looks good */
276
277 return 0;
278}
279
280
281void
282mpc86xx_restart(char *cmd)
283{
284 void __iomem *rstcr;
285
286 rstcr = ioremap(get_immrbase() + MPC86XX_RSTCR_OFFSET, 0x100);
287
288 local_irq_disable();
289
290 /* Assert reset request to Reset Control Register */
291 out_be32(rstcr, 0x2);
292
293 /* not reached */
294}
295
296
297long __init
298mpc86xx_time_init(void)
299{
300 unsigned int temp;
301
302 /* Set the time base to zero */
303 mtspr(SPRN_TBWL, 0);
304 mtspr(SPRN_TBWU, 0);
305
306 temp = mfspr(SPRN_HID0);
307 temp |= HID0_TBEN;
308 mtspr(SPRN_HID0, temp);
309 asm volatile("isync");
310
311 return 0;
312}
313
314
315define_machine(mpc86xx_hpcn) {
316 .name = "MPC86xx HPCN",
317 .probe = mpc86xx_hpcn_probe,
318 .setup_arch = mpc86xx_hpcn_setup_arch,
319 .init_IRQ = mpc86xx_hpcn_init_irq,
320 .show_cpuinfo = mpc86xx_hpcn_show_cpuinfo,
321 .get_irq = mpic_get_irq,
322 .restart = mpc86xx_restart,
323 .time_init = mpc86xx_time_init,
324 .calibrate_decr = generic_calibrate_decr,
325 .progress = udbg_progress,
326};
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