[POWERPC] Early serial debug support for PPC44x

This adds support for early serial debugging via the built in
port on IBM/AMCC PowerPC 44x CPUs.  It uses a bolted TLB entry in
address space 1 for the UART's mapping, allowing robust debugging both
before and after the initialization of the MMU.

Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>

2 files changed, 33 insertions, 0 deletions

diff --git a/arch/powerpc/platforms/44x/44x.h b/arch/powerpc/platforms/44x/44x.h
index 45f24b166f4..42eabf87fea 100644
--- a/arch/powerpc/platforms/44x/44x.h
+++ b/arch/powerpc/platforms/44x/44x.h
@@ -1,6 +1,8 @@
 #ifndef __POWERPC_PLATFORMS_44X_44X_H
 #define __POWERPC_PLATFORMS_44X_44X_H
 
+extern u8 as1_readb(volatile u8 __iomem  *addr);
+extern void as1_writeb(u8 data, volatile u8 __iomem *addr);
 extern void ppc44x_reset_system(char *cmd);
 
 #endif /* __POWERPC_PLATFORMS_44X_44X_H */
diff --git a/arch/powerpc/platforms/44x/misc_44x.S b/arch/powerpc/platforms/44x/misc_44x.S
index 52bde71485b..3bce71d5d75 100644
--- a/arch/powerpc/platforms/44x/misc_44x.S
+++ b/arch/powerpc/platforms/44x/misc_44x.S
@@ -15,6 +15,37 @@
         .text
 
 /*
+ * Do an IO access in AS1
+ */
+_GLOBAL(as1_readb)
+        mfmsr   r7
+        ori     r0,r7,MSR_DS
+        sync
+        mtmsr   r0
+        sync
+        isync
+        lbz     r3,0(r3)
+        sync
+        mtmsr   r7
+        sync
+        isync
+        blr
+
+_GLOBAL(as1_writeb)
+        mfmsr   r7
+        ori     r0,r7,MSR_DS
+        sync
+        mtmsr   r0
+        sync
+        isync
+        stb     r3,0(r4)
+        sync
+        mtmsr   r7
+        sync
+        isync
+        blr
+
+/*
  * void ppc44x_reset_system(char *cmd)
  *
  * At present, this routine just applies a system reset.