diff options
author | Milton Miller <miltonm@bga.com> | 2009-04-29 16:58:01 -0400 |
---|---|---|
committer | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2009-05-21 01:44:21 -0400 |
commit | 60dbf4385130136847ea73657da329f8e7dbe16e (patch) | |
tree | 66bb7e72105f416bcbe4be725fb5b97d9a965380 /arch/powerpc/mm/hash_native_64.c | |
parent | af20aeb1a3292ae7ecfc492a4dc059e35465e016 (diff) |
powerpc: Add 2.06 tlbie mnemonics
This adds the PowerPC 2.06 tlbie mnemonics and keeps backwards
compatibilty for CPUs before 2.06.
Only useful for bare metal systems.
Signed-off-by: Milton Miller <miltonm@bga.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/mm/hash_native_64.c')
-rw-r--r-- | arch/powerpc/mm/hash_native_64.c | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c index 34e5c0b219b..056d23a1b10 100644 --- a/arch/powerpc/mm/hash_native_64.c +++ b/arch/powerpc/mm/hash_native_64.c | |||
@@ -27,6 +27,7 @@ | |||
27 | #include <asm/cputable.h> | 27 | #include <asm/cputable.h> |
28 | #include <asm/udbg.h> | 28 | #include <asm/udbg.h> |
29 | #include <asm/kexec.h> | 29 | #include <asm/kexec.h> |
30 | #include <asm/ppc-opcode.h> | ||
30 | 31 | ||
31 | #ifdef DEBUG_LOW | 32 | #ifdef DEBUG_LOW |
32 | #define DBG_LOW(fmt...) udbg_printf(fmt) | 33 | #define DBG_LOW(fmt...) udbg_printf(fmt) |
@@ -49,14 +50,21 @@ static inline void __tlbie(unsigned long va, int psize, int ssize) | |||
49 | case MMU_PAGE_4K: | 50 | case MMU_PAGE_4K: |
50 | va &= ~0xffful; | 51 | va &= ~0xffful; |
51 | va |= ssize << 8; | 52 | va |= ssize << 8; |
52 | asm volatile("tlbie %0,0" : : "r" (va) : "memory"); | 53 | asm volatile(ASM_MMU_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0), |
54 | %2) | ||
55 | : : "r" (va), "r"(0), "i" (MMU_FTR_TLBIE_206) | ||
56 | : "memory"); | ||
53 | break; | 57 | break; |
54 | default: | 58 | default: |
55 | penc = mmu_psize_defs[psize].penc; | 59 | penc = mmu_psize_defs[psize].penc; |
56 | va &= ~((1ul << mmu_psize_defs[psize].shift) - 1); | 60 | va &= ~((1ul << mmu_psize_defs[psize].shift) - 1); |
57 | va |= penc << 12; | 61 | va |= penc << 12; |
58 | va |= ssize << 8; | 62 | va |= ssize << 8; |
59 | asm volatile("tlbie %0,1" : : "r" (va) : "memory"); | 63 | va |= 1; /* L */ |
64 | asm volatile(ASM_MMU_FTR_IFCLR("tlbie %0,1", PPC_TLBIE(%1,%0), | ||
65 | %2) | ||
66 | : : "r" (va), "r"(0), "i" (MMU_FTR_TLBIE_206) | ||
67 | : "memory"); | ||
60 | break; | 68 | break; |
61 | } | 69 | } |
62 | } | 70 | } |
@@ -80,6 +88,7 @@ static inline void __tlbiel(unsigned long va, int psize, int ssize) | |||
80 | va &= ~((1ul << mmu_psize_defs[psize].shift) - 1); | 88 | va &= ~((1ul << mmu_psize_defs[psize].shift) - 1); |
81 | va |= penc << 12; | 89 | va |= penc << 12; |
82 | va |= ssize << 8; | 90 | va |= ssize << 8; |
91 | va |= 1; /* L */ | ||
83 | asm volatile(".long 0x7c000224 | (%0 << 11) | (1 << 21)" | 92 | asm volatile(".long 0x7c000224 | (%0 << 11) | (1 << 21)" |
84 | : : "r"(va) : "memory"); | 93 | : : "r"(va) : "memory"); |
85 | break; | 94 | break; |