diff options
author | Wolfram Sang <w.sang@pengutronix.de> | 2008-12-21 04:54:32 -0500 |
---|---|---|
committer | Grant Likely <grant.likely@secretlab.ca> | 2008-12-21 04:54:32 -0500 |
commit | aec739e010f8163eac225f4e331ac7fbd59ac5c8 (patch) | |
tree | 85b01751d95c1635d0825c02d43654444543fb21 /arch/powerpc/include/asm/mpc52xx_psc.h | |
parent | b65149880d0467287fa4c7b4f19953392323f4ac (diff) |
powerpc/mpc5200: add rts/cts handling in PSC UART driver
Add RTS/CTS-support for the PSC of the MPC5200B. Tested with a Phytec
MPC5200B-IO.
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Diffstat (limited to 'arch/powerpc/include/asm/mpc52xx_psc.h')
-rw-r--r-- | arch/powerpc/include/asm/mpc52xx_psc.h | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/arch/powerpc/include/asm/mpc52xx_psc.h b/arch/powerpc/include/asm/mpc52xx_psc.h index 8917ed63056..a218da6bec7 100644 --- a/arch/powerpc/include/asm/mpc52xx_psc.h +++ b/arch/powerpc/include/asm/mpc52xx_psc.h | |||
@@ -68,12 +68,20 @@ | |||
68 | #define MPC52xx_PSC_IMR_ORERR 0x1000 | 68 | #define MPC52xx_PSC_IMR_ORERR 0x1000 |
69 | #define MPC52xx_PSC_IMR_IPC 0x8000 | 69 | #define MPC52xx_PSC_IMR_IPC 0x8000 |
70 | 70 | ||
71 | /* PSC input port change bit */ | 71 | /* PSC input port change bits */ |
72 | #define MPC52xx_PSC_CTS 0x01 | 72 | #define MPC52xx_PSC_CTS 0x01 |
73 | #define MPC52xx_PSC_DCD 0x02 | 73 | #define MPC52xx_PSC_DCD 0x02 |
74 | #define MPC52xx_PSC_D_CTS 0x10 | 74 | #define MPC52xx_PSC_D_CTS 0x10 |
75 | #define MPC52xx_PSC_D_DCD 0x20 | 75 | #define MPC52xx_PSC_D_DCD 0x20 |
76 | 76 | ||
77 | /* PSC acr bits */ | ||
78 | #define MPC52xx_PSC_IEC_CTS 0x01 | ||
79 | #define MPC52xx_PSC_IEC_DCD 0x02 | ||
80 | |||
81 | /* PSC output port bits */ | ||
82 | #define MPC52xx_PSC_OP_RTS 0x01 | ||
83 | #define MPC52xx_PSC_OP_RES 0x02 | ||
84 | |||
77 | /* PSC mode fields */ | 85 | /* PSC mode fields */ |
78 | #define MPC52xx_PSC_MODE_5_BITS 0x00 | 86 | #define MPC52xx_PSC_MODE_5_BITS 0x00 |
79 | #define MPC52xx_PSC_MODE_6_BITS 0x01 | 87 | #define MPC52xx_PSC_MODE_6_BITS 0x01 |
@@ -91,6 +99,7 @@ | |||
91 | #define MPC52xx_PSC_MODE_ONE_STOP_5_BITS 0x00 | 99 | #define MPC52xx_PSC_MODE_ONE_STOP_5_BITS 0x00 |
92 | #define MPC52xx_PSC_MODE_ONE_STOP 0x07 | 100 | #define MPC52xx_PSC_MODE_ONE_STOP 0x07 |
93 | #define MPC52xx_PSC_MODE_TWO_STOP 0x0f | 101 | #define MPC52xx_PSC_MODE_TWO_STOP 0x0f |
102 | #define MPC52xx_PSC_MODE_TXCTS 0x10 | ||
94 | 103 | ||
95 | #define MPC52xx_PSC_RFNUM_MASK 0x01ff | 104 | #define MPC52xx_PSC_RFNUM_MASK 0x01ff |
96 | 105 | ||