Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx

* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx:
  ppc440spe-adma: adds updated ppc440spe adma driver
  iop-adma.c: use resource_size()
  dmaengine: clarify the meaning of the DMA_CTRL_ACK flag
  sh: stylistic improvements for the DMA driver
  dmaengine: fix dmatest to verify minimum transfer length and test buffer size
  sh: DMA driver has to specify its alignment requirements
  Add COH 901 318 DMA block driver v5

1 files changed, 23 insertions, 0 deletions

diff --git a/arch/powerpc/include/asm/dcr-regs.h b/arch/powerpc/include/asm/dcr-regs.h
index 828e3aa1f2f..380274de429 100644
--- a/arch/powerpc/include/asm/dcr-regs.h
+++ b/arch/powerpc/include/asm/dcr-regs.h
@@ -157,4 +157,27 @@
 #define  L2C_SNP_SSR_32G        0x0000f000
 #define  L2C_SNP_ESR            0x00000800
 
+/*
+ * DCR register offsets for 440SP/440SPe I2O/DMA controller.
+ * The base address is configured in the device tree.
+ */
+#define DCRN_I2O0_IBAL          0x006
+#define DCRN_I2O0_IBAH          0x007
+#define I2O_REG_ENABLE          0x00000001      /* Enable I2O/DMA access */
+
+/* 440SP/440SPe Software Reset DCR */
+#define DCRN_SDR0_SRST          0x0200
+#define DCRN_SDR0_SRST_I2ODMA   (0x80000000 >> 15)      /* Reset I2O/DMA */
+
+/* 440SP/440SPe Memory Queue DCR offsets */
+#define DCRN_MQ0_XORBA          0x04
+#define DCRN_MQ0_CF2H           0x06
+#define DCRN_MQ0_CFBHL          0x0f
+#define DCRN_MQ0_BAUH           0x10
+
+/* HB/LL Paths Configuration Register */
+#define MQ0_CFBHL_TPLM          28
+#define MQ0_CFBHL_HBCL          23
+#define MQ0_CFBHL_POLY          15
+
 #endif /* __DCR_REGS_H__ */