[POWERPC] 4xx: Rework clock probing in boot wrapper

This reworks the boot wrapper library function that probes
the chip clocks. Better separate the base function that is
used on 440GX,SPe,EP,... from the uart fixups as those need
different device-tree path on different processors.

Also, rework the function itself based on the arch/ppc code
from Eugene Surovegin which I find more readable, and which
handles one more bypass case. Also handle the subtle difference
between 440EP/EPx and 440SPe/GX, on the former, PerClk is derived
from the PLB clock while on the later, it's derived from the OPB.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>

1 files changed, 17 insertions, 0 deletions

diff --git a/arch/powerpc/boot/dcr.h b/arch/powerpc/boot/dcr.h
index f6b793573b9..55655f78505 100644
--- a/arch/powerpc/boot/dcr.h
+++ b/arch/powerpc/boot/dcr.h
@@ -160,6 +160,23 @@ static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR,
 #define DCRN_CPR0_PERD                                  0x0e0
 #define DCRN_CPR0_MALD                                  0x100
 
+#define DCRN_SDR0_CONFIG_ADDR   0xe
+#define DCRN_SDR0_CONFIG_DATA   0xf
+
+/* SDR read/write helper macros */
+#define SDR0_READ(offset) ({\
+        mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \
+        mfdcr(DCRN_SDR0_CONFIG_DATA); })
+#define SDR0_WRITE(offset, data) ({\
+        mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \
+        mtdcr(DCRN_SDR0_CONFIG_DATA, data); })
+
+#define DCRN_SDR0_UART0         0x0120
+#define DCRN_SDR0_UART1         0x0121
+#define DCRN_SDR0_UART2         0x0122
+#define DCRN_SDR0_UART3         0x0123
+
+
 /* CPRs read/write helper macros - based off include/asm-ppc/ibm44x.h */
 
 #define DCRN_CPR0_CFGADDR                               0xc