diff options
author | Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> | 2008-07-13 07:02:13 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2008-07-15 13:44:38 -0400 |
commit | b6c4053610f04011bc0ecbc5a0417afe169b2693 (patch) | |
tree | 3324cd6637d74643a88468f40f4d091f7244863d /arch/mips/txx9 | |
parent | a38c47519832f22659244fd8437722b7aaa67f9a (diff) |
[MIPS] separate rbtx4927_time_init() and rbtx4937_time_init()
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Acked-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/txx9')
-rw-r--r-- | arch/mips/txx9/rbtx4927/setup.c | 78 |
1 files changed, 45 insertions, 33 deletions
diff --git a/arch/mips/txx9/rbtx4927/setup.c b/arch/mips/txx9/rbtx4927/setup.c index b4c4178607c..adc91c0bbb9 100644 --- a/arch/mips/txx9/rbtx4927/setup.c +++ b/arch/mips/txx9/rbtx4927/setup.c | |||
@@ -301,6 +301,18 @@ static void __init rbtx4927_mem_setup(void) | |||
301 | #endif | 301 | #endif |
302 | } | 302 | } |
303 | 303 | ||
304 | static void __init rbtx49x7_common_time_init(void) | ||
305 | { | ||
306 | /* change default value to udelay/mdelay take reasonable time */ | ||
307 | loops_per_jiffy = txx9_cpu_clock / HZ / 2; | ||
308 | |||
309 | mips_hpt_frequency = txx9_cpu_clock / 2; | ||
310 | if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_TINTDIS) | ||
311 | txx9_clockevent_init(TX4927_TMR_REG(0) & 0xfffffffffULL, | ||
312 | TXX9_IRQ_BASE + 17, | ||
313 | 50000000); | ||
314 | } | ||
315 | |||
304 | static void __init rbtx4927_time_init(void) | 316 | static void __init rbtx4927_time_init(void) |
305 | { | 317 | { |
306 | /* | 318 | /* |
@@ -313,6 +325,24 @@ static void __init rbtx4927_time_init(void) | |||
313 | * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5) | 325 | * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5) |
314 | * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6) | 326 | * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6) |
315 | * i.e. S9[3]: ON (83MHz), OFF (100MHz) | 327 | * i.e. S9[3]: ON (83MHz), OFF (100MHz) |
328 | */ | ||
329 | switch ((unsigned long)__raw_readq(&tx4927_ccfgptr->ccfg) & | ||
330 | TX4927_CCFG_PCIDIVMODE_MASK) { | ||
331 | case TX4927_CCFG_PCIDIVMODE_2_5: | ||
332 | case TX4927_CCFG_PCIDIVMODE_5: | ||
333 | txx9_cpu_clock = 166666666; /* 166MHz */ | ||
334 | break; | ||
335 | default: | ||
336 | txx9_cpu_clock = 200000000; /* 200MHz */ | ||
337 | } | ||
338 | |||
339 | rbtx49x7_common_time_init(); | ||
340 | } | ||
341 | |||
342 | static void __init rbtx4937_time_init(void) | ||
343 | { | ||
344 | /* | ||
345 | * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. | ||
316 | * | 346 | * |
317 | * For TX4937: | 347 | * For TX4937: |
318 | * PCIDIVMODE[12:11]'s initial value is given by S1[5:4] (ON:0, OFF:1) | 348 | * PCIDIVMODE[12:11]'s initial value is given by S1[5:4] (ON:0, OFF:1) |
@@ -324,39 +354,21 @@ static void __init rbtx4927_time_init(void) | |||
324 | * CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10) | 354 | * CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10) |
325 | * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5) | 355 | * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5) |
326 | */ | 356 | */ |
327 | if (mips_machtype == MACH_TOSHIBA_RBTX4937) | 357 | switch ((unsigned long)__raw_readq(&tx4938_ccfgptr->ccfg) & |
328 | switch ((unsigned long)__raw_readq(&tx4938_ccfgptr->ccfg) & | 358 | TX4938_CCFG_PCIDIVMODE_MASK) { |
329 | TX4938_CCFG_PCIDIVMODE_MASK) { | 359 | case TX4938_CCFG_PCIDIVMODE_8: |
330 | case TX4938_CCFG_PCIDIVMODE_8: | 360 | case TX4938_CCFG_PCIDIVMODE_4: |
331 | case TX4938_CCFG_PCIDIVMODE_4: | 361 | txx9_cpu_clock = 266666666; /* 266MHz */ |
332 | txx9_cpu_clock = 266666666; /* 266MHz */ | 362 | break; |
333 | break; | 363 | case TX4938_CCFG_PCIDIVMODE_9: |
334 | case TX4938_CCFG_PCIDIVMODE_9: | 364 | case TX4938_CCFG_PCIDIVMODE_4_5: |
335 | case TX4938_CCFG_PCIDIVMODE_4_5: | 365 | txx9_cpu_clock = 300000000; /* 300MHz */ |
336 | txx9_cpu_clock = 300000000; /* 300MHz */ | 366 | break; |
337 | break; | 367 | default: |
338 | default: | 368 | txx9_cpu_clock = 333333333; /* 333MHz */ |
339 | txx9_cpu_clock = 333333333; /* 333MHz */ | 369 | } |
340 | } | ||
341 | else | ||
342 | switch ((unsigned long)__raw_readq(&tx4927_ccfgptr->ccfg) & | ||
343 | TX4927_CCFG_PCIDIVMODE_MASK) { | ||
344 | case TX4927_CCFG_PCIDIVMODE_2_5: | ||
345 | case TX4927_CCFG_PCIDIVMODE_5: | ||
346 | txx9_cpu_clock = 166666666; /* 166MHz */ | ||
347 | break; | ||
348 | default: | ||
349 | txx9_cpu_clock = 200000000; /* 200MHz */ | ||
350 | } | ||
351 | |||
352 | /* change default value to udelay/mdelay take reasonable time */ | ||
353 | loops_per_jiffy = txx9_cpu_clock / HZ / 2; | ||
354 | 370 | ||
355 | mips_hpt_frequency = txx9_cpu_clock / 2; | 371 | rbtx49x7_common_time_init(); |
356 | if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_TINTDIS) | ||
357 | txx9_clockevent_init(TX4927_TMR_REG(0) & 0xfffffffffULL, | ||
358 | TXX9_IRQ_BASE + 17, | ||
359 | 50000000); | ||
360 | } | 372 | } |
361 | 373 | ||
362 | static int __init toshiba_rbtx4927_rtc_init(void) | 374 | static int __init toshiba_rbtx4927_rtc_init(void) |
@@ -434,7 +446,7 @@ struct txx9_board_vec rbtx4937_vec __initdata = { | |||
434 | .prom_init = rbtx4927_prom_init, | 446 | .prom_init = rbtx4927_prom_init, |
435 | .mem_setup = rbtx4927_mem_setup, | 447 | .mem_setup = rbtx4927_mem_setup, |
436 | .irq_setup = rbtx4927_irq_setup, | 448 | .irq_setup = rbtx4927_irq_setup, |
437 | .time_init = rbtx4927_time_init, | 449 | .time_init = rbtx4937_time_init, |
438 | .device_init = rbtx4927_device_init, | 450 | .device_init = rbtx4927_device_init, |
439 | .arch_init = rbtx4937_arch_init, | 451 | .arch_init = rbtx4937_arch_init, |
440 | #ifdef CONFIG_PCI | 452 | #ifdef CONFIG_PCI |