diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2009-06-19 10:01:44 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2009-06-24 13:34:39 -0400 |
commit | 44eeab67416711db9b84610ef18c99a60415dff8 (patch) | |
tree | e9beb9000be5cd9c17bbb7bc05cd3db1c4cb3f09 /arch/mips/power | |
parent | 631330f5847b3f8a7ea67d689e9f7c56833ccaa6 (diff) |
MIPS: Hibernation: Remove SMP TLB and cacheflushing code.
We can't perform any flushes on SMP from swsusp_arch_resume because
interrupts are disabled. A cross-CPU flush is unnecessary anyway
because all but the local CPU have already been disabled. A local
flush is not needed either because we didn't change any mappings. So
just delete the code.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/power')
-rw-r--r-- | arch/mips/power/hibernate.S | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/arch/mips/power/hibernate.S b/arch/mips/power/hibernate.S index 486bd3fd01a..4b8174b382d 100644 --- a/arch/mips/power/hibernate.S +++ b/arch/mips/power/hibernate.S | |||
@@ -43,15 +43,6 @@ LEAF(swsusp_arch_resume) | |||
43 | bne t1, t3, 1b | 43 | bne t1, t3, 1b |
44 | PTR_L t0, PBE_NEXT(t0) | 44 | PTR_L t0, PBE_NEXT(t0) |
45 | bnez t0, 0b | 45 | bnez t0, 0b |
46 | /* flush caches to make sure context is in memory */ | ||
47 | PTR_L t0, __flush_cache_all | ||
48 | jalr t0 | ||
49 | /* flush tlb entries */ | ||
50 | #ifdef CONFIG_SMP | ||
51 | jal flush_tlb_all | ||
52 | #else | ||
53 | jal local_flush_tlb_all | ||
54 | #endif | ||
55 | PTR_LA t0, saved_regs | 46 | PTR_LA t0, saved_regs |
56 | PTR_L ra, PT_R31(t0) | 47 | PTR_L ra, PT_R31(t0) |
57 | PTR_L sp, PT_R29(t0) | 48 | PTR_L sp, PT_R29(t0) |