[MIPS] Delete Ocelot 3 support.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

3 files changed, 0 insertions, 136 deletions

diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index cfebf58c8dc..f26ede001a0 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -9,7 +9,6 @@ obj-y				+= pci.o pci-dac.o
 #
 obj-$(CONFIG_MIPS_BONITO64)     += ops-bonito64.o
 obj-$(CONFIG_PCI_GT64XXX_PCI0)  += ops-gt64xxx_pci0.o
-obj-$(CONFIG_PCI_MARVELL)       += ops-marvell.o
 obj-$(CONFIG_MIPS_MSC)          += ops-msc.o
 obj-$(CONFIG_MIPS_TX3927)       += ops-tx3927.o
 obj-$(CONFIG_PCI_VR41XX)        += ops-vr41xx.o pci-vr41xx.o
@@ -29,7 +28,6 @@ obj-$(CONFIG_SOC_PNX8550)	+= fixup-pnx8550.o ops-pnx8550.o
 obj-$(CONFIG_LEMOTE_FULONG)     += fixup-lm2e.o ops-bonito64.o
 obj-$(CONFIG_MIPS_MALTA)        += fixup-malta.o
 obj-$(CONFIG_MOMENCO_OCELOT)    += fixup-ocelot.o pci-ocelot.o
-obj-$(CONFIG_MOMENCO_OCELOT_3)  += fixup-ocelot3.o
 obj-$(CONFIG_PMC_MSP7120_GW)    += fixup-pmcmsp.o ops-pmcmsp.o
 obj-$(CONFIG_PMC_MSP7120_EVAL)  += fixup-pmcmsp.o ops-pmcmsp.o
 obj-$(CONFIG_PMC_MSP7120_FPGA)  += fixup-pmcmsp.o ops-pmcmsp.o
diff --git a/arch/mips/pci/fixup-ocelot3.c b/arch/mips/pci/fixup-ocelot3.c
deleted file mode 100644
index 702f997b867..00000000000
--- a/arch/mips/pci/fixup-ocelot3.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2004 Montavista Software Inc.
- * Author: Manish Lachwani (mlachwani@mvista.com)
- *
- * Looking at the schematics for the Ocelot-3 board, there are
- * two PCI busses and each bus has two PCI slots.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/pci.h>
-#include <asm/mipsregs.h>
-
-/*
- * Do platform specific device initialization at
- * pci_enable_device() time
- */
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
-        return 0;
-}
-
-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
-        int bus = dev->bus->number;
-
-        if (bus == 0 && slot == 1)
-                return 2;       /* PCI-X A */
-        if (bus == 0 && slot == 2)
-                return 3;       /* PCI-X B */
-        if (bus == 1 && slot == 1)
-                return 4;       /* PCI A */
-        if (bus == 1 && slot == 2)
-                return 5;       /* PCI B */
-
-return 0;
-        panic("Whooops in pcibios_map_irq");
-}
diff --git a/arch/mips/pci/ops-marvell.c b/arch/mips/pci/ops-marvell.c
deleted file mode 100644
index 1ac5c59199d..00000000000
--- a/arch/mips/pci/ops-marvell.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2003, 2004 Ralf Baechle (ralf@linux-mips.org)
- */
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/pci.h>
-
-#include <asm/marvell.h>
-
-static int mv_read_config(struct pci_bus *bus, unsigned int devfn,
-        int where, int size, u32 * val)
-{
-        struct mv_pci_controller *mvbc = bus->sysdata;
-        unsigned long address_reg, data_reg;
-        u32 address;
-
-        address_reg = mvbc->config_addr;
-        data_reg = mvbc->config_vreg;
-
-        /* Accessing device 31 crashes those Marvells.  Since years.
-           Will they ever make sane controllers ... */
-        if (PCI_SLOT(devfn) == 31)
-                return PCIBIOS_DEVICE_NOT_FOUND;
-
-        address = (bus->number << 16) | (devfn << 8) |
-                  (where & 0xfc) | 0x80000000;
-
-        /* start the configuration cycle */
-        MV_WRITE(address_reg, address);
-
-        switch (size) {
-        case 1:
-                *val = MV_READ_8(data_reg + (where & 0x3));
-                break;
-
-        case 2:
-                *val = MV_READ_16(data_reg + (where & 0x3));
-                break;
-
-        case 4:
-                *val = MV_READ(data_reg);
-                break;
-        }
-
-        return PCIBIOS_SUCCESSFUL;
-}
-
-static int mv_write_config(struct pci_bus *bus, unsigned int devfn,
-        int where, int size, u32 val)
-{
-        struct mv_pci_controller *mvbc = bus->sysdata;
-        unsigned long address_reg, data_reg;
-        u32 address;
-
-        address_reg = mvbc->config_addr;
-        data_reg = mvbc->config_vreg;
-
-        /* Accessing device 31 crashes those Marvells.  Since years.
-           Will they ever make sane controllers ... */
-        if (PCI_SLOT(devfn) == 31)
-                return PCIBIOS_DEVICE_NOT_FOUND;
-
-        address = (bus->number << 16) | (devfn << 8) |
-                  (where & 0xfc) | 0x80000000;
-
-        /* start the configuration cycle */
-        MV_WRITE(address_reg, address);
-
-        switch (size) {
-        case 1:
-                MV_WRITE_8(data_reg + (where & 0x3), val);
-                break;
-
-        case 2:
-                MV_WRITE_16(data_reg + (where & 0x3), val);
-                break;
-
-        case 4:
-                MV_WRITE(data_reg, val);
-                break;
-        }
-
-        return PCIBIOS_SUCCESSFUL;
-}
-
-struct pci_ops mv_pci_ops = {
-        .read   = mv_read_config,
-        .write  = mv_write_config
-};