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authorRalf Baechle <ralf@linux-mips.org>2007-07-28 09:20:16 -0400
committerRalf Baechle <ralf@linux-mips.org>2007-07-31 16:35:29 -0400
commit0b0ef2ea00c581d613e15eadc3215d52a6a55946 (patch)
treed5081883a39ceb9a29b1f7b1123a4873becb6682 /arch/mips/pci
parente7865765ef85473c1b97aad86d44b80dc260dbbf (diff)
[MIPS] Remove Momentum Ocelot support.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/pci')
-rw-r--r--arch/mips/pci/Makefile1
-rw-r--r--arch/mips/pci/fixup-ocelot.c75
-rw-r--r--arch/mips/pci/pci-ocelot.c107
3 files changed, 0 insertions, 183 deletions
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index c58bd3d036f..8be9f2b9db2 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -27,7 +27,6 @@ obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o
27obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o 27obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o
28obj-$(CONFIG_LEMOTE_FULONG) += fixup-lm2e.o ops-bonito64.o 28obj-$(CONFIG_LEMOTE_FULONG) += fixup-lm2e.o ops-bonito64.o
29obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o 29obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o
30obj-$(CONFIG_MOMENCO_OCELOT) += fixup-ocelot.o pci-ocelot.o
31obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o 30obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o
32obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o 31obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o
33obj-$(CONFIG_PMC_MSP7120_FPGA) += fixup-pmcmsp.o ops-pmcmsp.o 32obj-$(CONFIG_PMC_MSP7120_FPGA) += fixup-pmcmsp.o ops-pmcmsp.o
diff --git a/arch/mips/pci/fixup-ocelot.c b/arch/mips/pci/fixup-ocelot.c
deleted file mode 100644
index 99629bd047c..00000000000
--- a/arch/mips/pci/fixup-ocelot.c
+++ /dev/null
@@ -1,75 +0,0 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 *
5 * arch/mips/gt64120/momenco_ocelot/pci.c
6 * Board-specific PCI routines for gt64120 controller.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13#include <linux/types.h>
14#include <linux/pci.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <asm/pci.h>
18
19
20void __devinit pcibios_fixup_bus(struct pci_bus *bus)
21{
22 struct pci_bus *current_bus = bus;
23 struct pci_dev *devices;
24 struct list_head *devices_link;
25 u16 cmd;
26
27 list_for_each(devices_link, &(current_bus->devices)) {
28
29 devices = pci_dev_b(devices_link);
30 if (devices == NULL)
31 continue;
32
33 if (PCI_SLOT(devices->devfn) == 1) {
34 /*
35 * Slot 1 is primary ether port, i82559
36 * we double-check against that assumption
37 */
38 if ((devices->vendor != 0x8086) ||
39 (devices->device != 0x1209)) {
40 panic("pcibios_fixup_bus: found "
41 "unexpected PCI device in slot 1.");
42 }
43 devices->irq = 2; /* irq_nr is 2 for INT0 */
44 } else if (PCI_SLOT(devices->devfn) == 2) {
45 /*
46 * Slot 2 is secondary ether port, i21143
47 * we double-check against that assumption
48 */
49 if ((devices->vendor != 0x1011) ||
50 (devices->device != 0x19)) {
51 panic("galileo_pcibios_fixup_bus: "
52 "found unexpected PCI device in slot 2.");
53 }
54 devices->irq = 3; /* irq_nr is 3 for INT1 */
55 } else if (PCI_SLOT(devices->devfn) == 4) {
56 /* PMC Slot 1 */
57 devices->irq = 8; /* irq_nr is 8 for INT6 */
58 } else if (PCI_SLOT(devices->devfn) == 5) {
59 /* PMC Slot 1 */
60 devices->irq = 9; /* irq_nr is 9 for INT7 */
61 } else {
62 /* We don't have assign interrupts for other devices. */
63 devices->irq = 0xff;
64 }
65
66 /* Assign an interrupt number for the device */
67 bus->ops->write_byte(devices, PCI_INTERRUPT_LINE,
68 devices->irq);
69
70 /* enable master */
71 bus->ops->read_word(devices, PCI_COMMAND, &cmd);
72 cmd |= PCI_COMMAND_MASTER;
73 bus->ops->write_word(devices, PCI_COMMAND, cmd);
74 }
75}
diff --git a/arch/mips/pci/pci-ocelot.c b/arch/mips/pci/pci-ocelot.c
deleted file mode 100644
index 1421d34535e..00000000000
--- a/arch/mips/pci/pci-ocelot.c
+++ /dev/null
@@ -1,107 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Galileo Evaluation Boards PCI support.
4 *
5 * The general-purpose functions to read/write and configure the GT64120A's
6 * PCI registers (function names start with pci0 or pci1) are either direct
7 * copies of functions written by Galileo Technology, or are modifications
8 * of their functions to work with Linux 2.4 vs Linux 2.2. These functions
9 * are Copyright - Galileo Technology.
10 *
11 * Other functions are derived from other MIPS PCI implementations, or were
12 * written by RidgeRun, Inc, Copyright (C) 2000 RidgeRun, Inc.
13 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
14 *
15 * Copyright 2001 MontaVista Software Inc.
16 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
17 *
18 * This program is free software; you can redistribute it and/or modify it
19 * under the terms of the GNU General Public License as published by the
20 * Free Software Foundation; either version 2 of the License, or (at your
21 * option) any later version.
22 *
23 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 * You should have received a copy of the GNU General Public License along
35 * with this program; if not, write to the Free Software Foundation, Inc.,
36 * 675 Mass Ave, Cambridge, MA 02139, USA.
37 */
38#include <linux/init.h>
39#include <linux/types.h>
40#include <linux/pci.h>
41#include <linux/kernel.h>
42#include <linux/slab.h>
43#include <linux/cache.h>
44#include <asm/pci.h>
45#include <asm/io.h>
46#include <asm/gt64120.h>
47
48static inline unsigned int pci0ReadConfigReg(unsigned int offset)
49{
50 unsigned int DataForRegCf8;
51 unsigned int data;
52
53 DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) |
54 (PCI_FUNC(device->devfn) << 8) |
55 (offset & ~0x3)) | 0x80000000;
56 GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8);
57 GT_READ(GT_PCI0_CFGDATA_OFS, &data);
58
59 return data;
60}
61
62static inline void pci0WriteConfigReg(unsigned int offset, unsigned int data)
63{
64 unsigned int DataForRegCf8;
65
66 DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) |
67 (PCI_FUNC(device->devfn) << 8) |
68 (offset & ~0x3)) | 0x80000000;
69 GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8);
70 GT_WRITE(GT_PCI0_CFGDATA_OFS, data);
71}
72
73static struct resource ocelot_mem_resource = {
74 .start = GT_PCI_MEM_BASE,
75 .end = GT_PCI_MEM_BASE + GT_PCI_MEM_BASE - 1,
76};
77
78static struct resource ocelot_io_resource = {
79 .start = GT_PCI_IO_BASE,
80 .end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1,
81};
82
83static struct pci_controller ocelot_pci_controller = {
84 .pci_ops = gt64xxx_pci0_ops,
85 .mem_resource = &ocelot_mem_resource,
86 .io_resource = &ocelot_io_resource,
87};
88
89static int __init ocelot_pcibios_init(void)
90{
91 u32 tmp;
92
93 GT_READ(GT_PCI0_CMD_OFS, &tmp);
94 GT_READ(GT_PCI0_BARE_OFS, &tmp);
95
96 /*
97 * You have to enable bus mastering to configure any other
98 * card on the bus.
99 */
100 tmp = pci0ReadConfigReg(PCI_COMMAND);
101 tmp |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
102 pci0WriteConfigReg(PCI_COMMAND, tmp);
103
104 register_pci_controller(&ocelot_pci_controller);
105}
106
107arch_initcall(ocelot_pcibios_init);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 21:06:04 -0500