diff options
author | Jayachandran C <jayachandranc@netlogicmicro.com> | 2011-05-11 02:34:58 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2011-05-19 04:55:39 -0400 |
commit | a7117c6bddcbfff2fa237a14a853b32cb94bf59a (patch) | |
tree | 3a81d4194766dedf274985047022d3441074a3db /arch/mips/include/asm | |
parent | 61c4f2c81c61f73549928dfd9f3e8f26aa36a8cf (diff) |
MIPS: Netlogic XLR/XLS processor IDs.
Add Netlogic Microsystems company ID and processor IDs for XLR
and XLS processors for CPU probe. Add CPU_XLR to cpu_type_enum.
Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2367/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm')
-rw-r--r-- | arch/mips/include/asm/cpu.h | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 86877539c6e..34c0d3cb116 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h | |||
@@ -33,6 +33,7 @@ | |||
33 | #define PRID_COMP_TOSHIBA 0x070000 | 33 | #define PRID_COMP_TOSHIBA 0x070000 |
34 | #define PRID_COMP_LSI 0x080000 | 34 | #define PRID_COMP_LSI 0x080000 |
35 | #define PRID_COMP_LEXRA 0x0b0000 | 35 | #define PRID_COMP_LEXRA 0x0b0000 |
36 | #define PRID_COMP_NETLOGIC 0x0c0000 | ||
36 | #define PRID_COMP_CAVIUM 0x0d0000 | 37 | #define PRID_COMP_CAVIUM 0x0d0000 |
37 | #define PRID_COMP_INGENIC 0xd00000 | 38 | #define PRID_COMP_INGENIC 0xd00000 |
38 | 39 | ||
@@ -142,6 +143,31 @@ | |||
142 | #define PRID_IMP_JZRISC 0x0200 | 143 | #define PRID_IMP_JZRISC 0x0200 |
143 | 144 | ||
144 | /* | 145 | /* |
146 | * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC | ||
147 | */ | ||
148 | #define PRID_IMP_NETLOGIC_XLR732 0x0000 | ||
149 | #define PRID_IMP_NETLOGIC_XLR716 0x0200 | ||
150 | #define PRID_IMP_NETLOGIC_XLR532 0x0900 | ||
151 | #define PRID_IMP_NETLOGIC_XLR308 0x0600 | ||
152 | #define PRID_IMP_NETLOGIC_XLR532C 0x0800 | ||
153 | #define PRID_IMP_NETLOGIC_XLR516C 0x0a00 | ||
154 | #define PRID_IMP_NETLOGIC_XLR508C 0x0b00 | ||
155 | #define PRID_IMP_NETLOGIC_XLR308C 0x0f00 | ||
156 | #define PRID_IMP_NETLOGIC_XLS608 0x8000 | ||
157 | #define PRID_IMP_NETLOGIC_XLS408 0x8800 | ||
158 | #define PRID_IMP_NETLOGIC_XLS404 0x8c00 | ||
159 | #define PRID_IMP_NETLOGIC_XLS208 0x8e00 | ||
160 | #define PRID_IMP_NETLOGIC_XLS204 0x8f00 | ||
161 | #define PRID_IMP_NETLOGIC_XLS108 0xce00 | ||
162 | #define PRID_IMP_NETLOGIC_XLS104 0xcf00 | ||
163 | #define PRID_IMP_NETLOGIC_XLS616B 0x4000 | ||
164 | #define PRID_IMP_NETLOGIC_XLS608B 0x4a00 | ||
165 | #define PRID_IMP_NETLOGIC_XLS416B 0x4400 | ||
166 | #define PRID_IMP_NETLOGIC_XLS412B 0x4c00 | ||
167 | #define PRID_IMP_NETLOGIC_XLS408B 0x4e00 | ||
168 | #define PRID_IMP_NETLOGIC_XLS404B 0x4f00 | ||
169 | |||
170 | /* | ||
145 | * Definitions for 7:0 on legacy processors | 171 | * Definitions for 7:0 on legacy processors |
146 | */ | 172 | */ |
147 | 173 | ||
@@ -234,6 +260,7 @@ enum cpu_type_enum { | |||
234 | */ | 260 | */ |
235 | CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, | 261 | CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, |
236 | CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2, | 262 | CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2, |
263 | CPU_XLR, | ||
237 | 264 | ||
238 | CPU_LAST | 265 | CPU_LAST |
239 | }; | 266 | }; |