Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (38 commits)
  MIPS: O32: Fix ppoll
  MIPS: Oprofile: Rename cpu_type from godson2 to loongson2
  MIPS: Alchemy: Fix hang with high-frequency edge interrupts
  MIPS: TXx9: Fix spi-baseclk value
  MIPS: bcm63xx: Set the correct BCM3302 CPU name
  MIPS: Loongson 2: Set cpu_has_dc_aliases and cpu_icache_snoops_remote_store
  MIPS: Avoid potential hazard on Context register
  MIPS: Octeon: Use lockless interrupt controller operations when possible.
  MIPS: Octeon: Use write_{un,}lock_irq{restore,save} to set irq affinity
  MIPS: Set S-cache linesize to 64-bytes for MTI's S-cache
  MIPS: SMTC: Avoid queing multiple reschedule IPIs
  MIPS: GCMP: Avoid accessing registers when they are not present
  MIPS: GIC: Random fixes and enhancements.
  MIPS: CMP: Fix memory barriers for correct operation of amon_cpu_start
  MIPS: Fix abs.[sd] and neg.[sd] emulation for NaN operands
  MIPS: SPRAM: Clean up support code a little
  MIPS: 1004K: Enable SPRAM support.
  MIPS: Malta: Enable PCI 2.1 compatibility in PIIX4
  MIPS: Kconfig: Fix duplicate default value for MIPS_L1_CACHE_SHIFT.
  MIPS: MTI: Fix accesses to device registers on MIPS boards
  ...

13 files changed, 61 insertions, 202 deletions

diff --git a/arch/mips/include/asm/fixmap.h b/arch/mips/include/asm/fixmap.h
index efeddc8db8b..0b89b83e205 100644
--- a/arch/mips/include/asm/fixmap.h
+++ b/arch/mips/include/asm/fixmap.h
@@ -48,9 +48,9 @@ enum fixed_addresses {
 #define FIX_N_COLOURS 8
         FIX_CMAP_BEGIN,
 #ifdef CONFIG_MIPS_MT_SMTC
-        FIX_CMAP_END = FIX_CMAP_BEGIN + (FIX_N_COLOURS * NR_CPUS),
+        FIX_CMAP_END = FIX_CMAP_BEGIN + (FIX_N_COLOURS * NR_CPUS * 2),
 #else
-        FIX_CMAP_END = FIX_CMAP_BEGIN + FIX_N_COLOURS,
+        FIX_CMAP_END = FIX_CMAP_BEGIN + (FIX_N_COLOURS * 2),
 #endif
 #ifdef CONFIG_HIGHMEM
         /* reserved pte's for temporary kernel mappings */
diff --git a/arch/mips/include/asm/gcmpregs.h b/arch/mips/include/asm/gcmpregs.h
index 36fd969d64d..c0cf76a2ca8 100644
--- a/arch/mips/include/asm/gcmpregs.h
+++ b/arch/mips/include/asm/gcmpregs.h
@@ -19,15 +19,20 @@
 #define GCMP_GDB_OFS            0x8000 /* Global Debug Block */
 
 /* Offsets to individual GCMP registers from GCMP base */
-#define GCMPOFS(block, tag, reg)        (GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS)
+#define GCMPOFS(block, tag, reg)        \
+        (GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS)
+#define GCMPOFSn(block, tag, reg, n) \
+        (GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS(n))
 
 #define GCMPGCBOFS(reg)         GCMPOFS(GCB, GCB, reg)
+#define GCMPGCBOFSn(reg, n)     GCMPOFSn(GCB, GCB, reg, n)
 #define GCMPCLCBOFS(reg)        GCMPOFS(CLCB, CCB, reg)
 #define GCMPCOCBOFS(reg)        GCMPOFS(COCB, CCB, reg)
 #define GCMPGDBOFS(reg)         GCMPOFS(GDB, GDB, reg)
 
 /* GCMP register access */
 #define GCMPGCB(reg)                    REGP(_gcmp_base, GCMPGCBOFS(reg))
+#define GCMPGCBn(reg, n)               REGP(_gcmp_base, GCMPGCBOFSn(reg, n))
 #define GCMPCLCB(reg)                   REGP(_gcmp_base, GCMPCLCBOFS(reg))
 #define GCMPCOCB(reg)                   REGP(_gcmp_base, GCMPCOCBOFS(reg))
 #define GCMPGDB(reg)                    REGP(_gcmp_base, GCMPGDBOFS(reg))
@@ -49,10 +54,10 @@
 #define  GCMP_GCB_GCMPB_GCMPBASE_MSK    GCMPGCBMSK(GCMPB_GCMPBASE, 17)
 #define  GCMP_GCB_GCMPB_CMDEFTGT_SHF    0
 #define  GCMP_GCB_GCMPB_CMDEFTGT_MSK    GCMPGCBMSK(GCMPB_CMDEFTGT, 2)
-#define  GCMP_GCB_GCMPB_CMDEFTGT_MEM    0
-#define  GCMP_GCB_GCMPB_CMDEFTGT_MEM1   1
-#define  GCMP_GCB_GCMPB_CMDEFTGT_IOCU1 2
-#define  GCMP_GCB_GCMPB_CMDEFTGT_IOCU2 3
+#define  GCMP_GCB_GCMPB_CMDEFTGT_DISABLED       0
+#define  GCMP_GCB_GCMPB_CMDEFTGT_MEM            1
+#define  GCMP_GCB_GCMPB_CMDEFTGT_IOCU1          2
+#define  GCMP_GCB_GCMPB_CMDEFTGT_IOCU2          3
 #define GCMP_GCB_CCMC_OFS               0x0010  /* Global CM Control */
 #define GCMP_GCB_GCSRAP_OFS             0x0020  /* Global CSR Access Privilege */
 #define  GCMP_GCB_GCSRAP_CMACCESS_SHF   0
@@ -115,5 +120,6 @@
 #define GCMP_CCB_DBGGROUP_OFS           0x0100          /* DebugBreak Group */
 
 extern int __init gcmp_probe(unsigned long, unsigned long);
-
+extern int __init gcmp_niocu(void);
+extern void __init gcmp_setregion(int, unsigned long, unsigned long, int);
 #endif /* _ASM_GCMPREGS_H */
diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h
index a8f57341f12..9b9436a4d81 100644
--- a/arch/mips/include/asm/gic.h
+++ b/arch/mips/include/asm/gic.h
@@ -12,7 +12,6 @@
 #define _ASM_GICREGS_H
 
 #undef  GICISBYTELITTLEENDIAN
-#define GICISWORDLITTLEENDIAN
 
 /* Constants */
 #define GIC_POL_POS                     1
@@ -20,11 +19,7 @@
 #define GIC_TRIG_EDGE                   1
 #define GIC_TRIG_LEVEL                  0
 
-#ifdef CONFIG_SMP
 #define GIC_NUM_INTRS                   (24 + NR_CPUS * 2)
-#else
-#define GIC_NUM_INTRS                   32
-#endif
 
 #define MSK(n) ((1 << (n)) - 1)
 #define REG32(addr)             (*(volatile unsigned int *) (addr))
@@ -70,13 +65,13 @@
 #define USM_VISIBLE_SECTION_SIZE        0x10000
 
 /* Register Map for Shared Section */
-#if defined(CONFIG_CPU_LITTLE_ENDIAN) || defined(GICISWORDLITTLEENDIAN)
 
 #define GIC_SH_CONFIG_OFS               0x0000
 
 /* Shared Global Counter */
 #define GIC_SH_COUNTER_31_00_OFS        0x0010
 #define GIC_SH_COUNTER_63_32_OFS        0x0014
+#define GIC_SH_REVISIONID_OFS           0x0020
 
 /* Interrupt Polarity */
 #define GIC_SH_POL_31_0_OFS             0x0100
@@ -164,24 +159,31 @@
         (GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + (((vpe) / 32) * 4))
 #define GIC_SH_MAP_TO_VPE_REG_BIT(vpe)  (1 << ((vpe) % 32))
 
+/* Convert an interrupt number to a byte offset/bit for multi-word registers */
+#define GIC_INTR_OFS(intr) (((intr) / 32)*4)
+#define GIC_INTR_BIT(intr) ((intr) % 32)
+
 /* Polarity : Reset Value is always 0 */
 #define GIC_SH_SET_POLARITY_OFS         0x0100
 #define GIC_SET_POLARITY(intr, pol) \
-        GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + (((intr) / 32) * 4)), (pol) << ((intr) % 32))
+        GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + \
+                GIC_INTR_OFS(intr)), (pol) << GIC_INTR_BIT(intr))
 
 /* Triggering : Reset Value is always 0 */
 #define GIC_SH_SET_TRIGGER_OFS          0x0180
 #define GIC_SET_TRIGGER(intr, trig) \
-        GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + (((intr) / 32) * 4)), (trig) << ((intr) % 32))
+        GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + \
+                GIC_INTR_OFS(intr)), (trig) << GIC_INTR_BIT(intr))
 
 /* Mask manipulation */
 #define GIC_SH_SMASK_OFS                0x0380
-#define GIC_SET_INTR_MASK(intr, val) \
-        GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + (((intr) / 32) * 4)), ((val) << ((intr) % 32)))
-
+#define GIC_SET_INTR_MASK(intr) \
+        GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + \
+                GIC_INTR_OFS(intr)), 1 << GIC_INTR_BIT(intr))
 #define GIC_SH_RMASK_OFS                0x0300
-#define GIC_CLR_INTR_MASK(intr, val) \
-        GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + (((intr) / 32) * 4)), ((val) << ((intr) % 32)))
+#define GIC_CLR_INTR_MASK(intr) \
+        GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + \
+                GIC_INTR_OFS(intr)), 1 << GIC_INTR_BIT(intr))
 
 /* Register Map for Local Section */
 #define GIC_VPE_CTL_OFS                 0x0000
@@ -219,161 +221,6 @@
 #define GIC_UMV_SH_COUNTER_31_00_OFS    0x0000
 #define GIC_UMV_SH_COUNTER_63_32_OFS    0x0004
 
-#else /* CONFIG_CPU_BIG_ENDIAN */
-
-#define GIC_SH_CONFIG_OFS               0x0000
-
-/* Shared Global Counter */
-#define GIC_SH_COUNTER_31_00_OFS        0x0014
-#define GIC_SH_COUNTER_63_32_OFS        0x0010
-
-/* Interrupt Polarity */
-#define GIC_SH_POL_31_0_OFS             0x0104
-#define GIC_SH_POL_63_32_OFS            0x0100
-#define GIC_SH_POL_95_64_OFS            0x010c
-#define GIC_SH_POL_127_96_OFS           0x0108
-#define GIC_SH_POL_159_128_OFS          0x0114
-#define GIC_SH_POL_191_160_OFS          0x0110
-#define GIC_SH_POL_223_192_OFS          0x011c
-#define GIC_SH_POL_255_224_OFS          0x0118
-
-/* Edge/Level Triggering */
-#define GIC_SH_TRIG_31_0_OFS            0x0184
-#define GIC_SH_TRIG_63_32_OFS           0x0180
-#define GIC_SH_TRIG_95_64_OFS           0x018c
-#define GIC_SH_TRIG_127_96_OFS          0x0188
-#define GIC_SH_TRIG_159_128_OFS         0x0194
-#define GIC_SH_TRIG_191_160_OFS         0x0190
-#define GIC_SH_TRIG_223_192_OFS         0x019c
-#define GIC_SH_TRIG_255_224_OFS         0x0198
-
-/* Dual Edge Triggering */
-#define GIC_SH_DUAL_31_0_OFS            0x0204
-#define GIC_SH_DUAL_63_32_OFS           0x0200
-#define GIC_SH_DUAL_95_64_OFS           0x020c
-#define GIC_SH_DUAL_127_96_OFS          0x0208
-#define GIC_SH_DUAL_159_128_OFS         0x0214
-#define GIC_SH_DUAL_191_160_OFS         0x0210
-#define GIC_SH_DUAL_223_192_OFS         0x021c
-#define GIC_SH_DUAL_255_224_OFS         0x0218
-
-/* Set/Clear corresponding bit in Edge Detect Register */
-#define GIC_SH_WEDGE_OFS                0x0280
-
-/* Reset Mask - Disables Interrupt */
-#define GIC_SH_RMASK_31_0_OFS           0x0304
-#define GIC_SH_RMASK_63_32_OFS          0x0300
-#define GIC_SH_RMASK_95_64_OFS          0x030c
-#define GIC_SH_RMASK_127_96_OFS         0x0308
-#define GIC_SH_RMASK_159_128_OFS        0x0314
-#define GIC_SH_RMASK_191_160_OFS        0x0310
-#define GIC_SH_RMASK_223_192_OFS        0x031c
-#define GIC_SH_RMASK_255_224_OFS        0x0318
-
-/* Set Mask (WO) - Enables Interrupt */
-#define GIC_SH_SMASK_31_0_OFS           0x0384
-#define GIC_SH_SMASK_63_32_OFS          0x0380
-#define GIC_SH_SMASK_95_64_OFS          0x038c
-#define GIC_SH_SMASK_127_96_OFS         0x0388
-#define GIC_SH_SMASK_159_128_OFS        0x0394
-#define GIC_SH_SMASK_191_160_OFS        0x0390
-#define GIC_SH_SMASK_223_192_OFS        0x039c
-#define GIC_SH_SMASK_255_224_OFS        0x0398
-
-/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */
-#define GIC_SH_MASK_31_0_OFS            0x0404
-#define GIC_SH_MASK_63_32_OFS           0x0400
-#define GIC_SH_MASK_95_64_OFS           0x040c
-#define GIC_SH_MASK_127_96_OFS          0x0408
-#define GIC_SH_MASK_159_128_OFS         0x0414
-#define GIC_SH_MASK_191_160_OFS         0x0410
-#define GIC_SH_MASK_223_192_OFS         0x041c
-#define GIC_SH_MASK_255_224_OFS         0x0418
-
-/* Pending Global Interrupts (RO) */
-#define GIC_SH_PEND_31_0_OFS            0x0484
-#define GIC_SH_PEND_63_32_OFS           0x0480
-#define GIC_SH_PEND_95_64_OFS           0x048c
-#define GIC_SH_PEND_127_96_OFS          0x0488
-#define GIC_SH_PEND_159_128_OFS         0x0494
-#define GIC_SH_PEND_191_160_OFS         0x0490
-#define GIC_SH_PEND_223_192_OFS         0x049c
-#define GIC_SH_PEND_255_224_OFS         0x0498
-
-#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500
-
-/* Maps Interrupt X to a Pin */
-#define GIC_SH_MAP_TO_PIN(intr) \
-        (GIC_SH_INTR_MAP_TO_PIN_BASE_OFS + (4 * intr))
-
-#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2004
-
-/*
- * Maps Interrupt X to a VPE.  This is more complex than the LE case, as
- * odd and even registers need to be transposed.  It does work - trust me!
- */
-#define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \
-        (GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + \
-        (((((vpe) / 32) ^ 1) - 1) * 4))
-#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe)  (1 << ((vpe) % 32))
-
-/* Polarity */
-#define GIC_SH_SET_POLARITY_OFS         0x0100
-#define GIC_SET_POLARITY(intr, pol) \
-        GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), (pol) << ((intr) % 32))
-
-/* Triggering */
-#define GIC_SH_SET_TRIGGER_OFS          0x0180
-#define GIC_SET_TRIGGER(intr, trig) \
-        GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), (trig) << ((intr) % 32))
-
-/* Mask manipulation */
-#define GIC_SH_SMASK_OFS                0x0380
-#define GIC_SET_INTR_MASK(intr, val) \
-        GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), ((val) << ((intr) % 32)))
-
-#define GIC_SH_RMASK_OFS                0x0300
-#define GIC_CLR_INTR_MASK(intr, val) \
-        GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), ((val) << ((intr) % 32)))
-
-/* Register Map for Local Section */
-#define GIC_VPE_CTL_OFS                 0x0000
-#define GIC_VPE_PEND_OFS                0x0004
-#define GIC_VPE_MASK_OFS                0x0008
-#define GIC_VPE_RMASK_OFS               0x000c
-#define GIC_VPE_SMASK_OFS               0x0010
-#define GIC_VPE_WD_MAP_OFS              0x0040
-#define GIC_VPE_COMPARE_MAP_OFS         0x0044
-#define GIC_VPE_TIMER_MAP_OFS           0x0048
-#define GIC_VPE_PERFCTR_MAP_OFS         0x0050
-#define GIC_VPE_SWINT0_MAP_OFS          0x0054
-#define GIC_VPE_SWINT1_MAP_OFS          0x0058
-#define GIC_VPE_OTHER_ADDR_OFS          0x0080
-#define GIC_VPE_WD_CONFIG0_OFS          0x0090
-#define GIC_VPE_WD_COUNT0_OFS           0x0094
-#define GIC_VPE_WD_INITIAL0_OFS         0x0098
-#define GIC_VPE_COMPARE_LO_OFS          0x00a4
-#define GIC_VPE_COMPARE_HI_OFS          0x00a0
-
-#define GIC_VPE_EIC_SHADOW_SET_BASE     0x0100
-#define GIC_VPE_EIC_SS(intr) \
-        (GIC_EIC_SHADOW_SET_BASE + (4 * intr))
-
-#define GIC_VPE_EIC_VEC_BASE            0x0800
-#define GIC_VPE_EIC_VEC(intr) \
-        (GIC_VPE_EIC_VEC_BASE + (4 * intr))
-
-#define GIC_VPE_TENABLE_NMI_OFS         0x1000
-#define GIC_VPE_TENABLE_YQ_OFS          0x1004
-#define GIC_VPE_TENABLE_INT_31_0_OFS    0x1080
-#define GIC_VPE_TENABLE_INT_63_32_OFS   0x1084
-
-/* User Mode Visible Section Register Map */
-#define GIC_UMV_SH_COUNTER_31_00_OFS    0x0004
-#define GIC_UMV_SH_COUNTER_63_32_OFS    0x0000
-
-#endif /* !LE */
-
 /* Masks */
 #define GIC_SH_CONFIG_COUNTSTOP_SHF     28
 #define GIC_SH_CONFIG_COUNTSTOP_MSK     (MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF)
@@ -473,12 +320,13 @@ struct gic_intrmask_regs {
  * in building ipi_map.
  */
 struct gic_intr_map {
-        unsigned int intrnum;   /* Ext Intr Num         */
         unsigned int cpunum;    /* Directed to this CPU */
         unsigned int pin;       /* Directed to this Pin */
         unsigned int polarity;  /* Polarity : +/-       */
         unsigned int trigtype;  /* Trigger  : Edge/Levl */
-        unsigned int ipiflag;   /* Is used for IPI ?    */
+        unsigned int flags;     /* Misc flags   */
+#define GIC_FLAG_IPI           0x01
+#define GIC_FLAG_TRANSPARENT   0x02
 };
 
 extern void gic_init(unsigned long gic_base_addr,
diff --git a/arch/mips/include/asm/mach-ar7/ar7.h b/arch/mips/include/asm/mach-ar7/ar7.h
index de71694614d..21cbbc70644 100644
--- a/arch/mips/include/asm/mach-ar7/ar7.h
+++ b/arch/mips/include/asm/mach-ar7/ar7.h
@@ -78,6 +78,9 @@
 #define AR7_REF_CLOCK   25000000
 #define AR7_XTAL_CLOCK  24000000
 
+/* DCL */
+#define AR7_WDT_HW_ENA  0x10
+
 struct plat_cpmac_data {
         int reset_bit;
         int power_bit;
diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
index feea00148b5..91595fa8903 100644
--- a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
@@ -104,6 +104,8 @@ static inline int au1100_gpio2_to_irq(int gpio)
 
         if ((gpio >= 8) && (gpio <= 15))
                 return MAKE_IRQ(0, 29);         /* shared GPIO208_215 */
+
+        return -ENXIO;
 }
 
 #ifdef CONFIG_SOC_AU1100
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_uart.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_uart.h
deleted file mode 100644
index bf348f573bb..00000000000
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_uart.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef BCM63XX_DEV_UART_H_
-#define BCM63XX_DEV_UART_H_
-
-int bcm63xx_uart_register(void);
-
-#endif /* BCM63XX_DEV_UART_H_ */
diff --git a/arch/mips/include/asm/mach-ip27/topology.h b/arch/mips/include/asm/mach-ip27/topology.h
index f6837422fe6..09a59bcc1b0 100644
--- a/arch/mips/include/asm/mach-ip27/topology.h
+++ b/arch/mips/include/asm/mach-ip27/topology.h
@@ -44,8 +44,8 @@ extern unsigned char __node_distances[MAX_COMPACT_NODES][MAX_COMPACT_NODES];
         .busy_factor            = 32,                   \
         .imbalance_pct          = 125,                  \
         .cache_nice_tries       = 1,                    \
-        .flags                  = SD_LOAD_BALANCE       \
-                                | SD_BALANCE_EXEC       \
+        .flags                  = SD_LOAD_BALANCE |     \
+                                  SD_BALANCE_EXEC,      \
         .last_balance           = jiffies,              \
         .balance_interval       = 1,                    \
         .nr_balance_failed      = 0,                    \
diff --git a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
index ce5b6e270e3..9947e57c91d 100644
--- a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
@@ -29,7 +29,7 @@
 #define cpu_has_cache_cdex_p    0
 #define cpu_has_cache_cdex_s    0
 #define cpu_has_counter         1
-#define cpu_has_dc_aliases      1
+#define cpu_has_dc_aliases      (PAGE_SIZE < 0x4000)
 #define cpu_has_divec           0
 #define cpu_has_dsp             0
 #define cpu_has_ejtag           0
@@ -54,6 +54,5 @@
 #define cpu_has_vce             0
 #define cpu_has_vtag_icache     0
 #define cpu_has_watch           1
-#define cpu_icache_snoops_remote_store  1
 
 #endif /* __ASM_MACH_LOONGSON_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h
index d9743536a62..6083db58650 100644
--- a/arch/mips/include/asm/mmu_context.h
+++ b/arch/mips/include/asm/mmu_context.h
@@ -16,6 +16,7 @@
 #include <linux/smp.h>
 #include <linux/slab.h>
 #include <asm/cacheflush.h>
+#include <asm/hazards.h>
 #include <asm/tlbflush.h>
 #ifdef CONFIG_MIPS_MT_SMTC
 #include <asm/mipsmtregs.h>
@@ -36,11 +37,13 @@ extern unsigned long pgd_current[];
 #ifdef CONFIG_32BIT
 #define TLBMISS_HANDLER_SETUP()                                         \
         write_c0_context((unsigned long) smp_processor_id() << 25);     \
+        back_to_back_c0_hazard();                                       \
         TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
 #endif
 #ifdef CONFIG_64BIT
 #define TLBMISS_HANDLER_SETUP()                                         \
         write_c0_context((unsigned long) smp_processor_id() << 26);     \
+        back_to_back_c0_hazard();                                       \
         TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
 #endif
 
@@ -165,12 +168,12 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
          * having ASID_MASK smaller than the hardware maximum,
          * make sure no "soft" bits become "hard"...
          */
-        write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK)
-                        | (cpu_context(cpu, next) & ASID_MASK));
+        write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) |
+                         cpu_asid(cpu, next));
         ehb(); /* Make sure it propagates to TCStatus */
         evpe(mtflags);
 #else
-        write_c0_entryhi(cpu_context(cpu, next));
+        write_c0_entryhi(cpu_asid(cpu, next));
 #endif /* CONFIG_MIPS_MT_SMTC */
         TLBMISS_HANDLER_SETUP_PGD(next->pgd);
 
@@ -226,11 +229,11 @@ activate_mm(struct mm_struct *prev, struct mm_struct *next)
         }
         /* See comments for similar code above */
         write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) |
-                         (cpu_context(cpu, next) & ASID_MASK));
+                         cpu_asid(cpu, next));
         ehb(); /* Make sure it propagates to TCStatus */
         evpe(mtflags);
 #else
-        write_c0_entryhi(cpu_context(cpu, next));
+        write_c0_entryhi(cpu_asid(cpu, next));
 #endif /* CONFIG_MIPS_MT_SMTC */
         TLBMISS_HANDLER_SETUP_PGD(next->pgd);
 
diff --git a/arch/mips/include/asm/setup.h b/arch/mips/include/asm/setup.h
index e600cedda97..50511aac04e 100644
--- a/arch/mips/include/asm/setup.h
+++ b/arch/mips/include/asm/setup.h
@@ -1,7 +1,7 @@
 #ifndef _MIPS_SETUP_H
 #define _MIPS_SETUP_H
 
-#define COMMAND_LINE_SIZE       256
+#define COMMAND_LINE_SIZE       4096
 
 #ifdef  __KERNEL__
 extern void setup_early_printk(void);
diff --git a/arch/mips/include/asm/smtc_ipi.h b/arch/mips/include/asm/smtc_ipi.h
index 8ce51757434..15278dbd7e7 100644
--- a/arch/mips/include/asm/smtc_ipi.h
+++ b/arch/mips/include/asm/smtc_ipi.h
@@ -45,6 +45,7 @@ struct smtc_ipi_q {
         spinlock_t lock;
         struct smtc_ipi *tail;
         int depth;
+        int resched_flag;       /* reschedule already queued */
 };
 
 static inline void smtc_ipi_nq(struct smtc_ipi_q *q, struct smtc_ipi *p)
diff --git a/arch/mips/include/asm/spram.h b/arch/mips/include/asm/spram.h
new file mode 100644
index 00000000000..0b89006e490
--- /dev/null
+++ b/arch/mips/include/asm/spram.h
@@ -0,0 +1,10 @@
+#ifndef _MIPS_SPRAM_H
+#define _MIPS_SPRAM_H
+
+#ifdef CONFIG_CPU_MIPSR2
+extern __init void spram_config(void);
+#else
+static inline void spram_config(void) { };
+#endif /* CONFIG_CPU_MIPSR2 */
+
+#endif /* _MIPS_SPRAM_H */
diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h
index 01cc1630b66..845da2107ed 100644
--- a/arch/mips/include/asm/thread_info.h
+++ b/arch/mips/include/asm/thread_info.h
@@ -86,14 +86,7 @@ register struct thread_info *__current_thread_info __asm__("$28");
 #define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
 
 #ifdef CONFIG_DEBUG_STACK_USAGE
-#define alloc_thread_info(tsk)                                  \
-({                                                              \
-        struct thread_info *ret;                                \
-                                                                \
-        ret = kzalloc(THREAD_SIZE, GFP_KERNEL);                 \
-                                                                \
-        ret;                                                    \
-})
+#define alloc_thread_info(tsk) kzalloc(THREAD_SIZE, GFP_KERNEL)
 #else
 #define alloc_thread_info(tsk) kmalloc(THREAD_SIZE, GFP_KERNEL)
 #endif