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authorJiri Kosina <jkosina@suse.cz>2011-04-26 04:22:15 -0400
committerJiri Kosina <jkosina@suse.cz>2011-04-26 04:22:59 -0400
commit07f9479a40cc778bc1462ada11f95b01360ae4ff (patch)
tree0676cf38df3844004bb3ebfd99dfa67a4a8998f5 /arch/mips/include/asm
parent9d5e6bdb3013acfb311ab407eeca0b6a6a3dedbf (diff)
parentcd2e49e90f1cae7726c9a2c54488d881d7f1cd1c (diff)
Merge branch 'master' into for-next
Fast-forwarded to current state of Linus' tree as there are patches to be applied for files that didn't exist on the old branch.
Diffstat (limited to 'arch/mips/include/asm')
-rw-r--r--arch/mips/include/asm/bitops.h3
-rw-r--r--arch/mips/include/asm/dec/prom.h2
-rw-r--r--arch/mips/include/asm/floppy.h2
-rw-r--r--arch/mips/include/asm/hw_irq.h2
-rw-r--r--arch/mips/include/asm/io.h2
-rw-r--r--arch/mips/include/asm/irq.h64
-rw-r--r--arch/mips/include/asm/irqflags.h2
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h2
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/irq.h243
-rw-r--r--arch/mips/include/asm/mach-ip32/mc146818rtc.h2
-rw-r--r--arch/mips/include/asm/mach-loongson/cs5536/cs5536.h2
-rw-r--r--arch/mips/include/asm/mach-pb1x00/pb1000.h2
-rw-r--r--arch/mips/include/asm/mach-pb1x00/pb1200.h2
-rw-r--r--arch/mips/include/asm/mach-pb1x00/pb1550.h2
-rw-r--r--arch/mips/include/asm/mach-powertv/dma-coherence.h2
-rw-r--r--arch/mips/include/asm/mipsregs.h4
-rw-r--r--arch/mips/include/asm/octeon/cvmx-bootinfo.h2
-rw-r--r--arch/mips/include/asm/octeon/cvmx-bootmem.h2
-rw-r--r--arch/mips/include/asm/octeon/cvmx-l2c.h2
-rw-r--r--arch/mips/include/asm/octeon/cvmx.h2
-rw-r--r--arch/mips/include/asm/octeon/octeon.h2
-rw-r--r--arch/mips/include/asm/paccess.h2
-rw-r--r--arch/mips/include/asm/pci/bridge.h2
-rw-r--r--arch/mips/include/asm/pmc-sierra/msp71xx/cpu-feature-overrides.h21
-rw-r--r--arch/mips/include/asm/pmc-sierra/msp71xx/msp_gpio_macros.h343
-rw-r--r--arch/mips/include/asm/pmc-sierra/msp71xx/msp_regops.h2
-rw-r--r--arch/mips/include/asm/pmc-sierra/msp71xx/msp_regs.h17
-rw-r--r--arch/mips/include/asm/pmc-sierra/msp71xx/msp_usb.h144
-rw-r--r--arch/mips/include/asm/processor.h2
-rw-r--r--arch/mips/include/asm/sgi/ioc.h2
-rw-r--r--arch/mips/include/asm/sibyte/sb1250_mac.h4
-rw-r--r--arch/mips/include/asm/siginfo.h2
-rw-r--r--arch/mips/include/asm/sn/klconfig.h4
-rw-r--r--arch/mips/include/asm/sn/sn0/hubio.h2
-rw-r--r--arch/mips/include/asm/spinlock.h22
-rw-r--r--arch/mips/include/asm/stackframe.h2
-rw-r--r--arch/mips/include/asm/thread_info.h6
-rw-r--r--arch/mips/include/asm/types.h8
-rw-r--r--arch/mips/include/asm/unistd.h24
-rw-r--r--arch/mips/include/asm/war.h2
40 files changed, 698 insertions, 261 deletions
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index 50b4ef288c5..2e1ad4c652b 100644
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -676,9 +676,8 @@ static inline int ffs(int word)
676#include <asm/arch_hweight.h> 676#include <asm/arch_hweight.h>
677#include <asm-generic/bitops/const_hweight.h> 677#include <asm-generic/bitops/const_hweight.h>
678 678
679#include <asm-generic/bitops/ext2-non-atomic.h> 679#include <asm-generic/bitops/le.h>
680#include <asm-generic/bitops/ext2-atomic.h> 680#include <asm-generic/bitops/ext2-atomic.h>
681#include <asm-generic/bitops/minix.h>
682 681
683#endif /* __KERNEL__ */ 682#endif /* __KERNEL__ */
684 683
diff --git a/arch/mips/include/asm/dec/prom.h b/arch/mips/include/asm/dec/prom.h
index b9c8203688d..c0ead631384 100644
--- a/arch/mips/include/asm/dec/prom.h
+++ b/arch/mips/include/asm/dec/prom.h
@@ -108,7 +108,7 @@ extern int (*__pmax_close)(int);
108 108
109/* 109/*
110 * On MIPS64 we have to call PROM functions via a helper 110 * On MIPS64 we have to call PROM functions via a helper
111 * dispatcher to accomodate ABI incompatibilities. 111 * dispatcher to accommodate ABI incompatibilities.
112 */ 112 */
113#define __DEC_PROM_O32(fun, arg) fun arg __asm__(#fun); \ 113#define __DEC_PROM_O32(fun, arg) fun arg __asm__(#fun); \
114 __asm__(#fun " = call_o32") 114 __asm__(#fun " = call_o32")
diff --git a/arch/mips/include/asm/floppy.h b/arch/mips/include/asm/floppy.h
index 992d232adc8..c5c7c0e6064 100644
--- a/arch/mips/include/asm/floppy.h
+++ b/arch/mips/include/asm/floppy.h
@@ -24,7 +24,7 @@ static inline void fd_cacheflush(char * addr, long size)
24 * And on Mips's the CMOS info fails also ... 24 * And on Mips's the CMOS info fails also ...
25 * 25 *
26 * FIXME: This information should come from the ARC configuration tree 26 * FIXME: This information should come from the ARC configuration tree
27 * or whereever a particular machine has stored this ... 27 * or wherever a particular machine has stored this ...
28 */ 28 */
29#define FLOPPY0_TYPE fd_drive_type(0) 29#define FLOPPY0_TYPE fd_drive_type(0)
30#define FLOPPY1_TYPE fd_drive_type(1) 30#define FLOPPY1_TYPE fd_drive_type(1)
diff --git a/arch/mips/include/asm/hw_irq.h b/arch/mips/include/asm/hw_irq.h
index aca05a43a97..77adda297ad 100644
--- a/arch/mips/include/asm/hw_irq.h
+++ b/arch/mips/include/asm/hw_irq.h
@@ -13,7 +13,7 @@
13extern atomic_t irq_err_count; 13extern atomic_t irq_err_count;
14 14
15/* 15/*
16 * interrupt-retrigger: NOP for now. This may not be apropriate for all 16 * interrupt-retrigger: NOP for now. This may not be appropriate for all
17 * machines, we'll see ... 17 * machines, we'll see ...
18 */ 18 */
19 19
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 5b017f23e24..b04e4de5dd2 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -242,7 +242,7 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
242 * This version of ioremap ensures that the memory is marked uncachable 242 * This version of ioremap ensures that the memory is marked uncachable
243 * on the CPU as well as honouring existing caching rules from things like 243 * on the CPU as well as honouring existing caching rules from things like
244 * the PCI bus. Note that there are other caches and buffers on many 244 * the PCI bus. Note that there are other caches and buffers on many
245 * busses. In paticular driver authors should read up on PCI writes 245 * busses. In particular driver authors should read up on PCI writes
246 * 246 *
247 * It's useful if some control registers are in such an area and 247 * It's useful if some control registers are in such an area and
248 * write combining or read caching is not desirable: 248 * write combining or read caching is not desirable:
diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h
index b003ed52ed1..0ec01294b06 100644
--- a/arch/mips/include/asm/irq.h
+++ b/arch/mips/include/asm/irq.h
@@ -55,9 +55,9 @@ static inline void smtc_im_ack_irq(unsigned int irq)
55#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF 55#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
56#include <linux/cpumask.h> 56#include <linux/cpumask.h>
57 57
58extern int plat_set_irq_affinity(unsigned int irq, 58extern int plat_set_irq_affinity(struct irq_data *d,
59 const struct cpumask *affinity); 59 const struct cpumask *affinity, bool force);
60extern void smtc_forward_irq(unsigned int irq); 60extern void smtc_forward_irq(struct irq_data *d);
61 61
62/* 62/*
63 * IRQ affinity hook invoked at the beginning of interrupt dispatch 63 * IRQ affinity hook invoked at the beginning of interrupt dispatch
@@ -70,51 +70,53 @@ extern void smtc_forward_irq(unsigned int irq);
70 * cpumask implementations, this version is optimistically assuming 70 * cpumask implementations, this version is optimistically assuming
71 * that cpumask.h macro overhead is reasonable during interrupt dispatch. 71 * that cpumask.h macro overhead is reasonable during interrupt dispatch.
72 */ 72 */
73#define IRQ_AFFINITY_HOOK(irq) \ 73static inline int handle_on_other_cpu(unsigned int irq)
74do { \ 74{
75 if (!cpumask_test_cpu(smp_processor_id(), irq_desc[irq].affinity)) {\ 75 struct irq_data *d = irq_get_irq_data(irq);
76 smtc_forward_irq(irq); \ 76
77 irq_exit(); \ 77 if (cpumask_test_cpu(smp_processor_id(), d->affinity))
78 return; \ 78 return 0;
79 } \ 79 smtc_forward_irq(d);
80} while (0) 80 return 1;
81}
81 82
82#else /* Not doing SMTC affinity */ 83#else /* Not doing SMTC affinity */
83 84
84#define IRQ_AFFINITY_HOOK(irq) do { } while (0) 85static inline int handle_on_other_cpu(unsigned int irq) { return 0; }
85 86
86#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ 87#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
87 88
88#ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP 89#ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP
89 90
91static inline void smtc_im_backstop(unsigned int irq)
92{
93 if (irq_hwmask[irq] & 0x0000ff00)
94 write_c0_tccontext(read_c0_tccontext() &
95 ~(irq_hwmask[irq] & 0x0000ff00));
96}
97
90/* 98/*
91 * Clear interrupt mask handling "backstop" if irq_hwmask 99 * Clear interrupt mask handling "backstop" if irq_hwmask
92 * entry so indicates. This implies that the ack() or end() 100 * entry so indicates. This implies that the ack() or end()
93 * functions will take over re-enabling the low-level mask. 101 * functions will take over re-enabling the low-level mask.
94 * Otherwise it will be done on return from exception. 102 * Otherwise it will be done on return from exception.
95 */ 103 */
96#define __DO_IRQ_SMTC_HOOK(irq) \ 104static inline int smtc_handle_on_other_cpu(unsigned int irq)
97do { \ 105{
98 IRQ_AFFINITY_HOOK(irq); \ 106 int ret = handle_on_other_cpu(irq);
99 if (irq_hwmask[irq] & 0x0000ff00) \ 107
100 write_c0_tccontext(read_c0_tccontext() & \ 108 if (!ret)
101 ~(irq_hwmask[irq] & 0x0000ff00)); \ 109 smtc_im_backstop(irq);
102} while (0) 110 return ret;
103 111}
104#define __NO_AFFINITY_IRQ_SMTC_HOOK(irq) \
105do { \
106 if (irq_hwmask[irq] & 0x0000ff00) \
107 write_c0_tccontext(read_c0_tccontext() & \
108 ~(irq_hwmask[irq] & 0x0000ff00)); \
109} while (0)
110 112
111#else 113#else
112 114
113#define __DO_IRQ_SMTC_HOOK(irq) \ 115static inline void smtc_im_backstop(unsigned int irq) { }
114do { \ 116static inline int smtc_handle_on_other_cpu(unsigned int irq)
115 IRQ_AFFINITY_HOOK(irq); \ 117{
116} while (0) 118 return handle_on_other_cpu(irq);
117#define __NO_AFFINITY_IRQ_SMTC_HOOK(irq) do { } while (0) 119}
118 120
119#endif 121#endif
120 122
diff --git a/arch/mips/include/asm/irqflags.h b/arch/mips/include/asm/irqflags.h
index 9ef3b0d1789..309cbcd6909 100644
--- a/arch/mips/include/asm/irqflags.h
+++ b/arch/mips/include/asm/irqflags.h
@@ -174,7 +174,7 @@ __asm__(
174 "mtc0 \\flags, $2, 1 \n" 174 "mtc0 \\flags, $2, 1 \n"
175#elif defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU) 175#elif defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU)
176 /* 176 /*
177 * Slow, but doesn't suffer from a relativly unlikely race 177 * Slow, but doesn't suffer from a relatively unlikely race
178 * condition we're having since days 1. 178 * condition we're having since days 1.
179 */ 179 */
180 " beqz \\flags, 1f \n" 180 " beqz \\flags, 1f \n"
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h b/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h
index 5325084d5c4..32978d32561 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h
@@ -4,7 +4,7 @@
4#define TAGVER_LEN 4 /* Length of Tag Version */ 4#define TAGVER_LEN 4 /* Length of Tag Version */
5#define TAGLAYOUT_LEN 4 /* Length of FlashLayoutVer */ 5#define TAGLAYOUT_LEN 4 /* Length of FlashLayoutVer */
6#define SIG1_LEN 20 /* Company Signature 1 Length */ 6#define SIG1_LEN 20 /* Company Signature 1 Length */
7#define SIG2_LEN 14 /* Company Signature 2 Lenght */ 7#define SIG2_LEN 14 /* Company Signature 2 Length */
8#define BOARDID_LEN 16 /* Length of BoardId */ 8#define BOARDID_LEN 16 /* Length of BoardId */
9#define ENDIANFLAG_LEN 2 /* Endian Flag Length */ 9#define ENDIANFLAG_LEN 2 /* Endian Flag Length */
10#define CHIPID_LEN 6 /* Chip Id Length */ 10#define CHIPID_LEN 6 /* Chip Id Length */
diff --git a/arch/mips/include/asm/mach-cavium-octeon/irq.h b/arch/mips/include/asm/mach-cavium-octeon/irq.h
index 6ddab8aef64..5b05f186e39 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/irq.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/irq.h
@@ -11,172 +11,91 @@
11#define NR_IRQS OCTEON_IRQ_LAST 11#define NR_IRQS OCTEON_IRQ_LAST
12#define MIPS_CPU_IRQ_BASE OCTEON_IRQ_SW0 12#define MIPS_CPU_IRQ_BASE OCTEON_IRQ_SW0
13 13
14/* 0 - 7 represent the i8259 master */ 14enum octeon_irq {
15#define OCTEON_IRQ_I8259M0 0 15/* 1 - 8 represent the 8 MIPS standard interrupt sources */
16#define OCTEON_IRQ_I8259M1 1 16 OCTEON_IRQ_SW0 = 1,
17#define OCTEON_IRQ_I8259M2 2 17 OCTEON_IRQ_SW1,
18#define OCTEON_IRQ_I8259M3 3 18/* CIU0, CUI2, CIU4 are 3, 4, 5 */
19#define OCTEON_IRQ_I8259M4 4 19 OCTEON_IRQ_5 = 6,
20#define OCTEON_IRQ_I8259M5 5 20 OCTEON_IRQ_PERF,
21#define OCTEON_IRQ_I8259M6 6 21 OCTEON_IRQ_TIMER,
22#define OCTEON_IRQ_I8259M7 7 22/* sources in CIU_INTX_EN0 */
23/* 8 - 15 represent the i8259 slave */ 23 OCTEON_IRQ_WORKQ0,
24#define OCTEON_IRQ_I8259S0 8 24 OCTEON_IRQ_GPIO0 = OCTEON_IRQ_WORKQ0 + 16,
25#define OCTEON_IRQ_I8259S1 9 25 OCTEON_IRQ_WDOG0 = OCTEON_IRQ_GPIO0 + 16,
26#define OCTEON_IRQ_I8259S2 10 26 OCTEON_IRQ_WDOG15 = OCTEON_IRQ_WDOG0 + 15,
27#define OCTEON_IRQ_I8259S3 11 27 OCTEON_IRQ_MBOX0 = OCTEON_IRQ_WDOG0 + 16,
28#define OCTEON_IRQ_I8259S4 12 28 OCTEON_IRQ_MBOX1,
29#define OCTEON_IRQ_I8259S5 13 29 OCTEON_IRQ_UART0,
30#define OCTEON_IRQ_I8259S6 14 30 OCTEON_IRQ_UART1,
31#define OCTEON_IRQ_I8259S7 15 31 OCTEON_IRQ_UART2,
32/* 16 - 23 represent the 8 MIPS standard interrupt sources */ 32 OCTEON_IRQ_PCI_INT0,
33#define OCTEON_IRQ_SW0 16 33 OCTEON_IRQ_PCI_INT1,
34#define OCTEON_IRQ_SW1 17 34 OCTEON_IRQ_PCI_INT2,
35#define OCTEON_IRQ_CIU0 18 35 OCTEON_IRQ_PCI_INT3,
36#define OCTEON_IRQ_CIU1 19 36 OCTEON_IRQ_PCI_MSI0,
37#define OCTEON_IRQ_CIU4 20 37 OCTEON_IRQ_PCI_MSI1,
38#define OCTEON_IRQ_5 21 38 OCTEON_IRQ_PCI_MSI2,
39#define OCTEON_IRQ_PERF 22 39 OCTEON_IRQ_PCI_MSI3,
40#define OCTEON_IRQ_TIMER 23 40
41/* 24 - 87 represent the sources in CIU_INTX_EN0 */ 41 OCTEON_IRQ_TWSI,
42#define OCTEON_IRQ_WORKQ0 24 42 OCTEON_IRQ_TWSI2,
43#define OCTEON_IRQ_WORKQ1 25 43 OCTEON_IRQ_RML,
44#define OCTEON_IRQ_WORKQ2 26 44 OCTEON_IRQ_TRACE0,
45#define OCTEON_IRQ_WORKQ3 27 45 OCTEON_IRQ_GMX_DRP0 = OCTEON_IRQ_TRACE0 + 4,
46#define OCTEON_IRQ_WORKQ4 28 46 OCTEON_IRQ_IPD_DRP = OCTEON_IRQ_GMX_DRP0 + 5,
47#define OCTEON_IRQ_WORKQ5 29 47 OCTEON_IRQ_KEY_ZERO,
48#define OCTEON_IRQ_WORKQ6 30 48 OCTEON_IRQ_TIMER0,
49#define OCTEON_IRQ_WORKQ7 31 49 OCTEON_IRQ_TIMER1,
50#define OCTEON_IRQ_WORKQ8 32 50 OCTEON_IRQ_TIMER2,
51#define OCTEON_IRQ_WORKQ9 33 51 OCTEON_IRQ_TIMER3,
52#define OCTEON_IRQ_WORKQ10 34 52 OCTEON_IRQ_USB0,
53#define OCTEON_IRQ_WORKQ11 35 53 OCTEON_IRQ_USB1,
54#define OCTEON_IRQ_WORKQ12 36 54 OCTEON_IRQ_PCM,
55#define OCTEON_IRQ_WORKQ13 37 55 OCTEON_IRQ_MPI,
56#define OCTEON_IRQ_WORKQ14 38 56 OCTEON_IRQ_POWIQ,
57#define OCTEON_IRQ_WORKQ15 39 57 OCTEON_IRQ_IPDPPTHR,
58#define OCTEON_IRQ_GPIO0 40 58 OCTEON_IRQ_MII0,
59#define OCTEON_IRQ_GPIO1 41 59 OCTEON_IRQ_MII1,
60#define OCTEON_IRQ_GPIO2 42 60 OCTEON_IRQ_BOOTDMA,
61#define OCTEON_IRQ_GPIO3 43 61
62#define OCTEON_IRQ_GPIO4 44 62 OCTEON_IRQ_NAND,
63#define OCTEON_IRQ_GPIO5 45 63 OCTEON_IRQ_MIO, /* Summary of MIO_BOOT_ERR */
64#define OCTEON_IRQ_GPIO6 46 64 OCTEON_IRQ_IOB, /* Summary of IOB_INT_SUM */
65#define OCTEON_IRQ_GPIO7 47 65 OCTEON_IRQ_FPA, /* Summary of FPA_INT_SUM */
66#define OCTEON_IRQ_GPIO8 48 66 OCTEON_IRQ_POW, /* Summary of POW_ECC_ERR */
67#define OCTEON_IRQ_GPIO9 49 67 OCTEON_IRQ_L2C, /* Summary of L2C_INT_STAT */
68#define OCTEON_IRQ_GPIO10 50 68 OCTEON_IRQ_IPD, /* Summary of IPD_INT_SUM */
69#define OCTEON_IRQ_GPIO11 51 69 OCTEON_IRQ_PIP, /* Summary of PIP_INT_REG */
70#define OCTEON_IRQ_GPIO12 52 70 OCTEON_IRQ_PKO, /* Summary of PKO_REG_ERROR */
71#define OCTEON_IRQ_GPIO13 53 71 OCTEON_IRQ_ZIP, /* Summary of ZIP_ERROR */
72#define OCTEON_IRQ_GPIO14 54 72 OCTEON_IRQ_TIM, /* Summary of TIM_REG_ERROR */
73#define OCTEON_IRQ_GPIO15 55 73 OCTEON_IRQ_RAD, /* Summary of RAD_REG_ERROR */
74#define OCTEON_IRQ_MBOX0 56 74 OCTEON_IRQ_KEY, /* Summary of KEY_INT_SUM */
75#define OCTEON_IRQ_MBOX1 57 75 OCTEON_IRQ_DFA, /* Summary of DFA */
76#define OCTEON_IRQ_UART0 58 76 OCTEON_IRQ_USBCTL, /* Summary of USBN0_INT_SUM */
77#define OCTEON_IRQ_UART1 59 77 OCTEON_IRQ_SLI, /* Summary of SLI_INT_SUM */
78#define OCTEON_IRQ_PCI_INT0 60 78 OCTEON_IRQ_DPI, /* Summary of DPI_INT_SUM */
79#define OCTEON_IRQ_PCI_INT1 61 79 OCTEON_IRQ_AGX0, /* Summary of GMX0*+PCS0_INT*_REG */
80#define OCTEON_IRQ_PCI_INT2 62 80 OCTEON_IRQ_AGL = OCTEON_IRQ_AGX0 + 5,
81#define OCTEON_IRQ_PCI_INT3 63 81 OCTEON_IRQ_PTP,
82#define OCTEON_IRQ_PCI_MSI0 64 82 OCTEON_IRQ_PEM0,
83#define OCTEON_IRQ_PCI_MSI1 65 83 OCTEON_IRQ_PEM1,
84#define OCTEON_IRQ_PCI_MSI2 66 84 OCTEON_IRQ_SRIO0,
85#define OCTEON_IRQ_PCI_MSI3 67 85 OCTEON_IRQ_SRIO1,
86#define OCTEON_IRQ_RESERVED68 68 /* Summary of CIU_INT_SUM1 */ 86 OCTEON_IRQ_LMC0,
87#define OCTEON_IRQ_TWSI 69 87 OCTEON_IRQ_DFM = OCTEON_IRQ_LMC0 + 4, /* Summary of DFM */
88#define OCTEON_IRQ_RML 70 88 OCTEON_IRQ_RST,
89#define OCTEON_IRQ_TRACE 71 89};
90#define OCTEON_IRQ_GMX_DRP0 72
91#define OCTEON_IRQ_GMX_DRP1 73
92#define OCTEON_IRQ_IPD_DRP 74
93#define OCTEON_IRQ_KEY_ZERO 75
94#define OCTEON_IRQ_TIMER0 76
95#define OCTEON_IRQ_TIMER1 77
96#define OCTEON_IRQ_TIMER2 78
97#define OCTEON_IRQ_TIMER3 79
98#define OCTEON_IRQ_USB0 80
99#define OCTEON_IRQ_PCM 81
100#define OCTEON_IRQ_MPI 82
101#define OCTEON_IRQ_TWSI2 83
102#define OCTEON_IRQ_POWIQ 84
103#define OCTEON_IRQ_IPDPPTHR 85
104#define OCTEON_IRQ_MII0 86
105#define OCTEON_IRQ_BOOTDMA 87
106/* 88 - 151 represent the sources in CIU_INTX_EN1 */
107#define OCTEON_IRQ_WDOG0 88
108#define OCTEON_IRQ_WDOG1 89
109#define OCTEON_IRQ_WDOG2 90
110#define OCTEON_IRQ_WDOG3 91
111#define OCTEON_IRQ_WDOG4 92
112#define OCTEON_IRQ_WDOG5 93
113#define OCTEON_IRQ_WDOG6 94
114#define OCTEON_IRQ_WDOG7 95
115#define OCTEON_IRQ_WDOG8 96
116#define OCTEON_IRQ_WDOG9 97
117#define OCTEON_IRQ_WDOG10 98
118#define OCTEON_IRQ_WDOG11 99
119#define OCTEON_IRQ_WDOG12 100
120#define OCTEON_IRQ_WDOG13 101
121#define OCTEON_IRQ_WDOG14 102
122#define OCTEON_IRQ_WDOG15 103
123#define OCTEON_IRQ_UART2 104
124#define OCTEON_IRQ_USB1 105
125#define OCTEON_IRQ_MII1 106
126#define OCTEON_IRQ_RESERVED107 107
127#define OCTEON_IRQ_RESERVED108 108
128#define OCTEON_IRQ_RESERVED109 109
129#define OCTEON_IRQ_RESERVED110 110
130#define OCTEON_IRQ_RESERVED111 111
131#define OCTEON_IRQ_RESERVED112 112
132#define OCTEON_IRQ_RESERVED113 113
133#define OCTEON_IRQ_RESERVED114 114
134#define OCTEON_IRQ_RESERVED115 115
135#define OCTEON_IRQ_RESERVED116 116
136#define OCTEON_IRQ_RESERVED117 117
137#define OCTEON_IRQ_RESERVED118 118
138#define OCTEON_IRQ_RESERVED119 119
139#define OCTEON_IRQ_RESERVED120 120
140#define OCTEON_IRQ_RESERVED121 121
141#define OCTEON_IRQ_RESERVED122 122
142#define OCTEON_IRQ_RESERVED123 123
143#define OCTEON_IRQ_RESERVED124 124
144#define OCTEON_IRQ_RESERVED125 125
145#define OCTEON_IRQ_RESERVED126 126
146#define OCTEON_IRQ_RESERVED127 127
147#define OCTEON_IRQ_RESERVED128 128
148#define OCTEON_IRQ_RESERVED129 129
149#define OCTEON_IRQ_RESERVED130 130
150#define OCTEON_IRQ_RESERVED131 131
151#define OCTEON_IRQ_RESERVED132 132
152#define OCTEON_IRQ_RESERVED133 133
153#define OCTEON_IRQ_RESERVED134 134
154#define OCTEON_IRQ_RESERVED135 135
155#define OCTEON_IRQ_RESERVED136 136
156#define OCTEON_IRQ_RESERVED137 137
157#define OCTEON_IRQ_RESERVED138 138
158#define OCTEON_IRQ_RESERVED139 139
159#define OCTEON_IRQ_RESERVED140 140
160#define OCTEON_IRQ_RESERVED141 141
161#define OCTEON_IRQ_RESERVED142 142
162#define OCTEON_IRQ_RESERVED143 143
163#define OCTEON_IRQ_RESERVED144 144
164#define OCTEON_IRQ_RESERVED145 145
165#define OCTEON_IRQ_RESERVED146 146
166#define OCTEON_IRQ_RESERVED147 147
167#define OCTEON_IRQ_RESERVED148 148
168#define OCTEON_IRQ_RESERVED149 149
169#define OCTEON_IRQ_RESERVED150 150
170#define OCTEON_IRQ_RESERVED151 151
171 90
172#ifdef CONFIG_PCI_MSI 91#ifdef CONFIG_PCI_MSI
173/* 152 - 215 represent the MSI interrupts 0-63 */ 92/* 152 - 407 represent the MSI interrupts 0-255 */
174#define OCTEON_IRQ_MSI_BIT0 152 93#define OCTEON_IRQ_MSI_BIT0 (OCTEON_IRQ_RST + 1)
175#define OCTEON_IRQ_MSI_LAST (OCTEON_IRQ_MSI_BIT0 + 255)
176 94
177#define OCTEON_IRQ_LAST (OCTEON_IRQ_MSI_LAST + 1) 95#define OCTEON_IRQ_MSI_LAST (OCTEON_IRQ_MSI_BIT0 + 255)
96#define OCTEON_IRQ_LAST (OCTEON_IRQ_MSI_LAST + 1)
178#else 97#else
179#define OCTEON_IRQ_LAST 152 98#define OCTEON_IRQ_LAST (OCTEON_IRQ_RST + 1)
180#endif 99#endif
181 100
182#endif 101#endif
diff --git a/arch/mips/include/asm/mach-ip32/mc146818rtc.h b/arch/mips/include/asm/mach-ip32/mc146818rtc.h
index c28ba8d8407..6b6bab43d5c 100644
--- a/arch/mips/include/asm/mach-ip32/mc146818rtc.h
+++ b/arch/mips/include/asm/mach-ip32/mc146818rtc.h
@@ -26,7 +26,7 @@ static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
26} 26}
27 27
28/* 28/*
29 * FIXME: Do it right. For now just assume that noone lives in 20th century 29 * FIXME: Do it right. For now just assume that no one lives in 20th century
30 * and no O2 user in 22th century ;-) 30 * and no O2 user in 22th century ;-)
31 */ 31 */
32#define mc146818_decode_year(year) ((year) + 2000) 32#define mc146818_decode_year(year) ((year) + 2000)
diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h
index 021f77ca59e..2a8e2bb5d53 100644
--- a/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h
+++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * The header file of cs5536 sourth bridge. 2 * The header file of cs5536 south bridge.
3 * 3 *
4 * Copyright (C) 2007 Lemote, Inc. 4 * Copyright (C) 2007 Lemote, Inc.
5 * Author : jlliu <liujl@lemote.com> 5 * Author : jlliu <liujl@lemote.com>
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1000.h b/arch/mips/include/asm/mach-pb1x00/pb1000.h
index 6d1ff9060e4..65059255dc1 100644
--- a/arch/mips/include/asm/mach-pb1x00/pb1000.h
+++ b/arch/mips/include/asm/mach-pb1x00/pb1000.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Alchemy Semi Pb1000 Referrence Board 2 * Alchemy Semi Pb1000 Reference Board
3 * 3 *
4 * Copyright 2001, 2008 MontaVista Software Inc. 4 * Copyright 2001, 2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. <source@mvista.com> 5 * Author: MontaVista Software, Inc. <source@mvista.com>
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1200.h b/arch/mips/include/asm/mach-pb1x00/pb1200.h
index 962eb55dc88..fce4332ebb7 100644
--- a/arch/mips/include/asm/mach-pb1x00/pb1200.h
+++ b/arch/mips/include/asm/mach-pb1x00/pb1200.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * AMD Alchemy Pb1200 Referrence Board 2 * AMD Alchemy Pb1200 Reference Board
3 * Board Registers defines. 3 * Board Registers defines.
4 * 4 *
5 * ######################################################################## 5 * ########################################################################
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1550.h b/arch/mips/include/asm/mach-pb1x00/pb1550.h
index fc4d766641c..f835c88e959 100644
--- a/arch/mips/include/asm/mach-pb1x00/pb1550.h
+++ b/arch/mips/include/asm/mach-pb1x00/pb1550.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * AMD Alchemy Semi PB1550 Referrence Board 2 * AMD Alchemy Semi PB1550 Reference Board
3 * Board Registers defines. 3 * Board Registers defines.
4 * 4 *
5 * Copyright 2004 Embedded Edge LLC. 5 * Copyright 2004 Embedded Edge LLC.
diff --git a/arch/mips/include/asm/mach-powertv/dma-coherence.h b/arch/mips/include/asm/mach-powertv/dma-coherence.h
index f76029c2406..a8e72cf1214 100644
--- a/arch/mips/include/asm/mach-powertv/dma-coherence.h
+++ b/arch/mips/include/asm/mach-powertv/dma-coherence.h
@@ -48,7 +48,7 @@ static inline unsigned long virt_to_phys_from_pte(void *addr)
48 /* check for a valid page */ 48 /* check for a valid page */
49 if (pte_present(pte)) { 49 if (pte_present(pte)) {
50 /* get the physical address the page is 50 /* get the physical address the page is
51 * refering to */ 51 * referring to */
52 phys_addr = (unsigned long) 52 phys_addr = (unsigned long)
53 page_to_phys(pte_page(pte)); 53 page_to_phys(pte_page(pte));
54 /* add the offset within the page */ 54 /* add the offset within the page */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 4d987097538..6a6f8a8f542 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -922,7 +922,7 @@ do { \
922#define write_c0_config7(val) __write_32bit_c0_register($16, 7, val) 922#define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
923 923
924/* 924/*
925 * The WatchLo register. There may be upto 8 of them. 925 * The WatchLo register. There may be up to 8 of them.
926 */ 926 */
927#define read_c0_watchlo0() __read_ulong_c0_register($18, 0) 927#define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
928#define read_c0_watchlo1() __read_ulong_c0_register($18, 1) 928#define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
@@ -942,7 +942,7 @@ do { \
942#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) 942#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
943 943
944/* 944/*
945 * The WatchHi register. There may be upto 8 of them. 945 * The WatchHi register. There may be up to 8 of them.
946 */ 946 */
947#define read_c0_watchhi0() __read_32bit_c0_register($19, 0) 947#define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
948#define read_c0_watchhi1() __read_32bit_c0_register($19, 1) 948#define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
diff --git a/arch/mips/include/asm/octeon/cvmx-bootinfo.h b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
index f3c23a43f84..4e4c3a8282d 100644
--- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h
+++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
@@ -200,7 +200,7 @@ enum cvmx_chip_types_enum {
200 CVMX_CHIP_TYPE_MAX, 200 CVMX_CHIP_TYPE_MAX,
201}; 201};
202 202
203/* Compatability alias for NAC38 name change, planned to be removed 203/* Compatibility alias for NAC38 name change, planned to be removed
204 * from SDK 1.7 */ 204 * from SDK 1.7 */
205#define CVMX_BOARD_TYPE_NAO38 CVMX_BOARD_TYPE_NAC38 205#define CVMX_BOARD_TYPE_NAO38 CVMX_BOARD_TYPE_NAC38
206 206
diff --git a/arch/mips/include/asm/octeon/cvmx-bootmem.h b/arch/mips/include/asm/octeon/cvmx-bootmem.h
index 8e708bdb43f..877845b84b1 100644
--- a/arch/mips/include/asm/octeon/cvmx-bootmem.h
+++ b/arch/mips/include/asm/octeon/cvmx-bootmem.h
@@ -67,7 +67,7 @@ struct cvmx_bootmem_block_header {
67 67
68/* 68/*
69 * Structure for named memory blocks. Number of descriptors available 69 * Structure for named memory blocks. Number of descriptors available
70 * can be changed without affecting compatiblity, but name length 70 * can be changed without affecting compatibility, but name length
71 * changes require a bump in the bootmem descriptor version Note: This 71 * changes require a bump in the bootmem descriptor version Note: This
72 * structure must be naturally 64 bit aligned, as a single memory 72 * structure must be naturally 64 bit aligned, as a single memory
73 * image will be used by both 32 and 64 bit programs. 73 * image will be used by both 32 and 64 bit programs.
diff --git a/arch/mips/include/asm/octeon/cvmx-l2c.h b/arch/mips/include/asm/octeon/cvmx-l2c.h
index 0b32c5b118e..2c8ff9e33ec 100644
--- a/arch/mips/include/asm/octeon/cvmx-l2c.h
+++ b/arch/mips/include/asm/octeon/cvmx-l2c.h
@@ -157,7 +157,7 @@ enum cvmx_l2c_tad_event {
157 157
158/** 158/**
159 * Configure one of the four L2 Cache performance counters to capture event 159 * Configure one of the four L2 Cache performance counters to capture event
160 * occurences. 160 * occurrences.
161 * 161 *
162 * @counter: The counter to configure. Range 0..3. 162 * @counter: The counter to configure. Range 0..3.
163 * @event: The type of L2 Cache event occurrence to count. 163 * @event: The type of L2 Cache event occurrence to count.
diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h
index 9d9381e2e3d..7e1286706d4 100644
--- a/arch/mips/include/asm/octeon/cvmx.h
+++ b/arch/mips/include/asm/octeon/cvmx.h
@@ -151,7 +151,7 @@ enum cvmx_mips_space {
151#endif 151#endif
152 152
153/** 153/**
154 * Convert a memory pointer (void*) into a hardware compatable 154 * Convert a memory pointer (void*) into a hardware compatible
155 * memory address (uint64_t). Octeon hardware widgets don't 155 * memory address (uint64_t). Octeon hardware widgets don't
156 * understand logical addresses. 156 * understand logical addresses.
157 * 157 *
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
index 6b34afd0d4e..f72f768cd3a 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -257,4 +257,6 @@ extern struct cvmx_bootinfo *octeon_bootinfo;
257 257
258extern uint64_t octeon_bootloader_entry_addr; 258extern uint64_t octeon_bootloader_entry_addr;
259 259
260extern void (*octeon_irq_setup_secondary)(void);
261
260#endif /* __ASM_OCTEON_OCTEON_H */ 262#endif /* __ASM_OCTEON_OCTEON_H */
diff --git a/arch/mips/include/asm/paccess.h b/arch/mips/include/asm/paccess.h
index c2394f8b0fe..9ce5a1e7e14 100644
--- a/arch/mips/include/asm/paccess.h
+++ b/arch/mips/include/asm/paccess.h
@@ -7,7 +7,7 @@
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8 * 8 *
9 * Protected memory access. Used for everything that might take revenge 9 * Protected memory access. Used for everything that might take revenge
10 * by sending a DBE error like accessing possibly non-existant memory or 10 * by sending a DBE error like accessing possibly non-existent memory or
11 * devices. 11 * devices.
12 */ 12 */
13#ifndef _ASM_PACCESS_H 13#ifndef _ASM_PACCESS_H
diff --git a/arch/mips/include/asm/pci/bridge.h b/arch/mips/include/asm/pci/bridge.h
index f1f508e4f97..be44fb0266d 100644
--- a/arch/mips/include/asm/pci/bridge.h
+++ b/arch/mips/include/asm/pci/bridge.h
@@ -262,7 +262,7 @@ typedef volatile struct bridge_s {
262} bridge_t; 262} bridge_t;
263 263
264/* 264/*
265 * Field formats for Error Command Word and Auxillary Error Command Word 265 * Field formats for Error Command Word and Auxiliary Error Command Word
266 * of bridge. 266 * of bridge.
267 */ 267 */
268typedef struct bridge_err_cmdword_s { 268typedef struct bridge_err_cmdword_s {
diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/cpu-feature-overrides.h b/arch/mips/include/asm/pmc-sierra/msp71xx/cpu-feature-overrides.h
new file mode 100644
index 00000000000..a80801b094b
--- /dev/null
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/cpu-feature-overrides.h
@@ -0,0 +1,21 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003, 04, 07 Ralf Baechle (ralf@linux-mips.org)
7 */
8#ifndef __ASM_MACH_MSP71XX_CPU_FEATURE_OVERRIDES_H
9#define __ASM_MACH_MSP71XX_CPU_FEATURE_OVERRIDES_H
10
11#define cpu_has_mips16 1
12#define cpu_has_dsp 1
13#define cpu_has_mipsmt 1
14#define cpu_has_fpu 0
15
16#define cpu_has_mips32r1 0
17#define cpu_has_mips32r2 1
18#define cpu_has_mips64r1 0
19#define cpu_has_mips64r2 0
20
21#endif /* __ASM_MACH_MSP71XX_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_gpio_macros.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_gpio_macros.h
new file mode 100644
index 00000000000..156f320c69e
--- /dev/null
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_gpio_macros.h
@@ -0,0 +1,343 @@
1/*
2 *
3 * Macros for external SMP-safe access to the PMC MSP71xx reference
4 * board GPIO pins
5 *
6 * Copyright 2010 PMC-Sierra, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#ifndef __MSP_GPIO_MACROS_H__
30#define __MSP_GPIO_MACROS_H__
31
32#include <msp_regops.h>
33#include <msp_regs.h>
34
35#ifdef CONFIG_PMC_MSP7120_GW
36#define MSP_NUM_GPIOS 20
37#else
38#define MSP_NUM_GPIOS 28
39#endif
40
41/* -- GPIO Enumerations -- */
42enum msp_gpio_data {
43 MSP_GPIO_LO = 0,
44 MSP_GPIO_HI = 1,
45 MSP_GPIO_NONE, /* Special - Means pin is out of range */
46 MSP_GPIO_TOGGLE, /* Special - Sets pin to opposite */
47};
48
49enum msp_gpio_mode {
50 MSP_GPIO_INPUT = 0x0,
51 /* MSP_GPIO_ INTERRUPT = 0x1, Not supported yet */
52 MSP_GPIO_UART_INPUT = 0x2, /* Only GPIO 4 or 5 */
53 MSP_GPIO_OUTPUT = 0x8,
54 MSP_GPIO_UART_OUTPUT = 0x9, /* Only GPIO 2 or 3 */
55 MSP_GPIO_PERIF_TIMERA = 0x9, /* Only GPIO 0 or 1 */
56 MSP_GPIO_PERIF_TIMERB = 0xa, /* Only GPIO 0 or 1 */
57 MSP_GPIO_UNKNOWN = 0xb, /* No such GPIO or mode */
58};
59
60/* -- Static Tables -- */
61
62/* Maps pins to data register */
63static volatile u32 * const MSP_GPIO_DATA_REGISTER[] = {
64 /* GPIO 0 and 1 on the first register */
65 GPIO_DATA1_REG, GPIO_DATA1_REG,
66 /* GPIO 2, 3, 4, and 5 on the second register */
67 GPIO_DATA2_REG, GPIO_DATA2_REG, GPIO_DATA2_REG, GPIO_DATA2_REG,
68 /* GPIO 6, 7, 8, and 9 on the third register */
69 GPIO_DATA3_REG, GPIO_DATA3_REG, GPIO_DATA3_REG, GPIO_DATA3_REG,
70 /* GPIO 10, 11, 12, 13, 14, and 15 on the fourth register */
71 GPIO_DATA4_REG, GPIO_DATA4_REG, GPIO_DATA4_REG, GPIO_DATA4_REG,
72 GPIO_DATA4_REG, GPIO_DATA4_REG,
73 /* GPIO 16 - 23 on the first strange EXTENDED register */
74 EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG,
75 EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG,
76 EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG,
77 /* GPIO 24 - 27 on the second strange EXTENDED register */
78 EXTENDED_GPIO2_REG, EXTENDED_GPIO2_REG, EXTENDED_GPIO2_REG,
79 EXTENDED_GPIO2_REG,
80};
81
82/* Maps pins to mode register */
83static volatile u32 * const MSP_GPIO_MODE_REGISTER[] = {
84 /* GPIO 0 and 1 on the first register */
85 GPIO_CFG1_REG, GPIO_CFG1_REG,
86 /* GPIO 2, 3, 4, and 5 on the second register */
87 GPIO_CFG2_REG, GPIO_CFG2_REG, GPIO_CFG2_REG, GPIO_CFG2_REG,
88 /* GPIO 6, 7, 8, and 9 on the third register */
89 GPIO_CFG3_REG, GPIO_CFG3_REG, GPIO_CFG3_REG, GPIO_CFG3_REG,
90 /* GPIO 10, 11, 12, 13, 14, and 15 on the fourth register */
91 GPIO_CFG4_REG, GPIO_CFG4_REG, GPIO_CFG4_REG, GPIO_CFG4_REG,
92 GPIO_CFG4_REG, GPIO_CFG4_REG,
93 /* GPIO 16 - 23 on the first strange EXTENDED register */
94 EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG,
95 EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG,
96 EXTENDED_GPIO1_REG, EXTENDED_GPIO1_REG,
97 /* GPIO 24 - 27 on the second strange EXTENDED register */
98 EXTENDED_GPIO2_REG, EXTENDED_GPIO2_REG, EXTENDED_GPIO2_REG,
99 EXTENDED_GPIO2_REG,
100};
101
102/* Maps 'basic' pins to relative offset from 0 per register */
103static int MSP_GPIO_OFFSET[] = {
104 /* GPIO 0 and 1 on the first register */
105 0, 0,
106 /* GPIO 2, 3, 4, and 5 on the second register */
107 2, 2, 2, 2,
108 /* GPIO 6, 7, 8, and 9 on the third register */
109 6, 6, 6, 6,
110 /* GPIO 10, 11, 12, 13, 14, and 15 on the fourth register */
111 10, 10, 10, 10, 10, 10,
112};
113
114/* Maps MODE to allowed pin mask */
115static unsigned int MSP_GPIO_MODE_ALLOWED[] = {
116 0xffffffff, /* Mode 0 - INPUT */
117 0x00000, /* Mode 1 - INTERRUPT */
118 0x00030, /* Mode 2 - UART_INPUT (GPIO 4, 5)*/
119 0, 0, 0, 0, 0, /* Modes 3, 4, 5, 6, and 7 are reserved */
120 0xffffffff, /* Mode 8 - OUTPUT */
121 0x0000f, /* Mode 9 - UART_OUTPUT/
122 PERF_TIMERA (GPIO 0, 1, 2, 3) */
123 0x00003, /* Mode a - PERF_TIMERB (GPIO 0, 1) */
124 0x00000, /* Mode b - Not really a mode! */
125};
126
127/* -- Bit masks -- */
128
129/* This gives you the 'register relative offset gpio' number */
130#define OFFSET_GPIO_NUMBER(gpio) (gpio - MSP_GPIO_OFFSET[gpio])
131
132/* These take the 'register relative offset gpio' number */
133#define BASIC_DATA_REG_MASK(ogpio) (1 << ogpio)
134#define BASIC_MODE_REG_VALUE(mode, ogpio) \
135 (mode << BASIC_MODE_REG_SHIFT(ogpio))
136#define BASIC_MODE_REG_MASK(ogpio) \
137 BASIC_MODE_REG_VALUE(0xf, ogpio)
138#define BASIC_MODE_REG_SHIFT(ogpio) (ogpio * 4)
139#define BASIC_MODE_REG_FROM_REG(data, ogpio) \
140 ((data & BASIC_MODE_REG_MASK(ogpio)) >> BASIC_MODE_REG_SHIFT(ogpio))
141
142/* These take the actual GPIO number (0 through 15) */
143#define BASIC_DATA_MASK(gpio) \
144 BASIC_DATA_REG_MASK(OFFSET_GPIO_NUMBER(gpio))
145#define BASIC_MODE_MASK(gpio) \
146 BASIC_MODE_REG_MASK(OFFSET_GPIO_NUMBER(gpio))
147#define BASIC_MODE(mode, gpio) \
148 BASIC_MODE_REG_VALUE(mode, OFFSET_GPIO_NUMBER(gpio))
149#define BASIC_MODE_SHIFT(gpio) \
150 BASIC_MODE_REG_SHIFT(OFFSET_GPIO_NUMBER(gpio))
151#define BASIC_MODE_FROM_REG(data, gpio) \
152 BASIC_MODE_REG_FROM_REG(data, OFFSET_GPIO_NUMBER(gpio))
153
154/*
155 * Each extended GPIO register is 32 bits long and is responsible for up to
156 * eight GPIOs. The least significant 16 bits contain the set and clear bit
157 * pair for each of the GPIOs. The most significant 16 bits contain the
158 * disable and enable bit pair for each of the GPIOs. For example, the
159 * extended GPIO reg for GPIOs 16-23 is as follows:
160 *
161 * 31: GPIO23_DISABLE
162 * ...
163 * 19: GPIO17_DISABLE
164 * 18: GPIO17_ENABLE
165 * 17: GPIO16_DISABLE
166 * 16: GPIO16_ENABLE
167 * ...
168 * 3: GPIO17_SET
169 * 2: GPIO17_CLEAR
170 * 1: GPIO16_SET
171 * 0: GPIO16_CLEAR
172 */
173
174/* This gives the 'register relative offset gpio' number */
175#define EXTENDED_OFFSET_GPIO(gpio) (gpio < 24 ? gpio - 16 : gpio - 24)
176
177/* These take the 'register relative offset gpio' number */
178#define EXTENDED_REG_DISABLE(ogpio) (0x2 << ((ogpio * 2) + 16))
179#define EXTENDED_REG_ENABLE(ogpio) (0x1 << ((ogpio * 2) + 16))
180#define EXTENDED_REG_SET(ogpio) (0x2 << (ogpio * 2))
181#define EXTENDED_REG_CLR(ogpio) (0x1 << (ogpio * 2))
182
183/* These take the actual GPIO number (16 through 27) */
184#define EXTENDED_DISABLE(gpio) \
185 EXTENDED_REG_DISABLE(EXTENDED_OFFSET_GPIO(gpio))
186#define EXTENDED_ENABLE(gpio) \
187 EXTENDED_REG_ENABLE(EXTENDED_OFFSET_GPIO(gpio))
188#define EXTENDED_SET(gpio) \
189 EXTENDED_REG_SET(EXTENDED_OFFSET_GPIO(gpio))
190#define EXTENDED_CLR(gpio) \
191 EXTENDED_REG_CLR(EXTENDED_OFFSET_GPIO(gpio))
192
193#define EXTENDED_FULL_MASK (0xffffffff)
194
195/* -- API inline-functions -- */
196
197/*
198 * Gets the current value of the specified pin
199 */
200static inline enum msp_gpio_data msp_gpio_pin_get(unsigned int gpio)
201{
202 u32 pinhi_mask = 0, pinhi_mask2 = 0;
203
204 if (gpio >= MSP_NUM_GPIOS)
205 return MSP_GPIO_NONE;
206
207 if (gpio < 16) {
208 pinhi_mask = BASIC_DATA_MASK(gpio);
209 } else {
210 /*
211 * Two cases are possible with the EXTENDED register:
212 * - In output mode (ENABLED flag set), check the CLR bit
213 * - In input mode (ENABLED flag not set), check the SET bit
214 */
215 pinhi_mask = EXTENDED_ENABLE(gpio) | EXTENDED_CLR(gpio);
216 pinhi_mask2 = EXTENDED_SET(gpio);
217 }
218 if (((*MSP_GPIO_DATA_REGISTER[gpio] & pinhi_mask) == pinhi_mask) ||
219 (*MSP_GPIO_DATA_REGISTER[gpio] & pinhi_mask2))
220 return MSP_GPIO_HI;
221 else
222 return MSP_GPIO_LO;
223}
224
225/* Sets the specified pin to the specified value */
226static inline void msp_gpio_pin_set(enum msp_gpio_data data, unsigned int gpio)
227{
228 if (gpio >= MSP_NUM_GPIOS)
229 return;
230
231 if (gpio < 16) {
232 if (data == MSP_GPIO_TOGGLE)
233 toggle_reg32(MSP_GPIO_DATA_REGISTER[gpio],
234 BASIC_DATA_MASK(gpio));
235 else if (data == MSP_GPIO_HI)
236 set_reg32(MSP_GPIO_DATA_REGISTER[gpio],
237 BASIC_DATA_MASK(gpio));
238 else
239 clear_reg32(MSP_GPIO_DATA_REGISTER[gpio],
240 BASIC_DATA_MASK(gpio));
241 } else {
242 if (data == MSP_GPIO_TOGGLE) {
243 /* Special ugly case:
244 * We have to read the CLR bit.
245 * If set, we write the CLR bit.
246 * If not, we write the SET bit.
247 */
248 u32 tmpdata;
249
250 custom_read_reg32(MSP_GPIO_DATA_REGISTER[gpio],
251 tmpdata);
252 if (tmpdata & EXTENDED_CLR(gpio))
253 tmpdata = EXTENDED_CLR(gpio);
254 else
255 tmpdata = EXTENDED_SET(gpio);
256 custom_write_reg32(MSP_GPIO_DATA_REGISTER[gpio],
257 tmpdata);
258 } else {
259 u32 newdata;
260
261 if (data == MSP_GPIO_HI)
262 newdata = EXTENDED_SET(gpio);
263 else
264 newdata = EXTENDED_CLR(gpio);
265 set_value_reg32(MSP_GPIO_DATA_REGISTER[gpio],
266 EXTENDED_FULL_MASK, newdata);
267 }
268 }
269}
270
271/* Sets the specified pin to the specified value */
272static inline void msp_gpio_pin_hi(unsigned int gpio)
273{
274 msp_gpio_pin_set(MSP_GPIO_HI, gpio);
275}
276
277/* Sets the specified pin to the specified value */
278static inline void msp_gpio_pin_lo(unsigned int gpio)
279{
280 msp_gpio_pin_set(MSP_GPIO_LO, gpio);
281}
282
283/* Sets the specified pin to the opposite value */
284static inline void msp_gpio_pin_toggle(unsigned int gpio)
285{
286 msp_gpio_pin_set(MSP_GPIO_TOGGLE, gpio);
287}
288
289/* Gets the mode of the specified pin */
290static inline enum msp_gpio_mode msp_gpio_pin_get_mode(unsigned int gpio)
291{
292 enum msp_gpio_mode retval = MSP_GPIO_UNKNOWN;
293 uint32_t data;
294
295 if (gpio >= MSP_NUM_GPIOS)
296 return retval;
297
298 data = *MSP_GPIO_MODE_REGISTER[gpio];
299
300 if (gpio < 16) {
301 retval = BASIC_MODE_FROM_REG(data, gpio);
302 } else {
303 /* Extended pins can only be either INPUT or OUTPUT */
304 if (data & EXTENDED_ENABLE(gpio))
305 retval = MSP_GPIO_OUTPUT;
306 else
307 retval = MSP_GPIO_INPUT;
308 }
309
310 return retval;
311}
312
313/*
314 * Sets the specified mode on the requested pin
315 * Returns 0 on success, or -1 if that mode is not allowed on this pin
316 */
317static inline int msp_gpio_pin_mode(enum msp_gpio_mode mode, unsigned int gpio)
318{
319 u32 modemask, newmode;
320
321 if ((1 << gpio) & ~MSP_GPIO_MODE_ALLOWED[mode])
322 return -1;
323
324 if (gpio >= MSP_NUM_GPIOS)
325 return -1;
326
327 if (gpio < 16) {
328 modemask = BASIC_MODE_MASK(gpio);
329 newmode = BASIC_MODE(mode, gpio);
330 } else {
331 modemask = EXTENDED_FULL_MASK;
332 if (mode == MSP_GPIO_INPUT)
333 newmode = EXTENDED_DISABLE(gpio);
334 else
335 newmode = EXTENDED_ENABLE(gpio);
336 }
337 /* Do the set atomically */
338 set_value_reg32(MSP_GPIO_MODE_REGISTER[gpio], modemask, newmode);
339
340 return 0;
341}
342
343#endif /* __MSP_GPIO_MACROS_H__ */
diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regops.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regops.h
index 60a5a38dd5b..7d41474e548 100644
--- a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regops.h
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regops.h
@@ -205,7 +205,7 @@ static inline u32 blocking_read_reg32(volatile u32 *const addr)
205 * custom_read_reg32(address, tmp); <-- Reads the address and put the value 205 * custom_read_reg32(address, tmp); <-- Reads the address and put the value
206 * in the 'tmp' variable given 206 * in the 'tmp' variable given
207 * 207 *
208 * From here on out, you are (basicly) atomic, so don't do anything too 208 * From here on out, you are (basically) atomic, so don't do anything too
209 * fancy! 209 * fancy!
210 * Also, this code may loop if the end of this block fails to write 210 * Also, this code may loop if the end of this block fails to write
211 * everything back safely due do the other CPU, so do NOT do anything 211 * everything back safely due do the other CPU, so do NOT do anything
diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regs.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regs.h
index 603eb737b4a..692c1b658b9 100644
--- a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regs.h
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regs.h
@@ -91,12 +91,10 @@
91 /* MAC C device registers */ 91 /* MAC C device registers */
92#define MSP_ADSL2_BASE (MSP_MSB_BASE + 0xA80000) 92#define MSP_ADSL2_BASE (MSP_MSB_BASE + 0xA80000)
93 /* ADSL2 device registers */ 93 /* ADSL2 device registers */
94#define MSP_USB_BASE (MSP_MSB_BASE + 0xB40000) 94#define MSP_USB0_BASE (MSP_MSB_BASE + 0xB00000)
95 /* USB device registers */ 95 /* USB0 device registers */
96#define MSP_USB_BASE_START (MSP_MSB_BASE + 0xB40100) 96#define MSP_USB1_BASE (MSP_MSB_BASE + 0x300000)
97 /* USB device registers */ 97 /* USB1 device registers */
98#define MSP_USB_BASE_END (MSP_MSB_BASE + 0xB401FF)
99 /* USB device registers */
100#define MSP_CPUIF_BASE (MSP_MSB_BASE + 0xC00000) 98#define MSP_CPUIF_BASE (MSP_MSB_BASE + 0xC00000)
101 /* CPU interface registers */ 99 /* CPU interface registers */
102 100
@@ -319,8 +317,11 @@
319#define CPU_ERR2_REG regptr(MSP_SLP_BASE + 0x184) 317#define CPU_ERR2_REG regptr(MSP_SLP_BASE + 0x184)
320 /* CPU/SLP Error status 1 */ 318 /* CPU/SLP Error status 1 */
321 319
322#define EXTENDED_GPIO_REG regptr(MSP_SLP_BASE + 0x188) 320/* Extended GPIO registers */
323 /* Extended GPIO register */ 321#define EXTENDED_GPIO1_REG regptr(MSP_SLP_BASE + 0x188)
322#define EXTENDED_GPIO2_REG regptr(MSP_SLP_BASE + 0x18c)
323#define EXTENDED_GPIO_REG EXTENDED_GPIO1_REG
324 /* Backward-compatibility */
324 325
325/* System Error registers */ 326/* System Error registers */
326#define SLP_ERR_STS_REG regptr(MSP_SLP_BASE + 0x190) 327#define SLP_ERR_STS_REG regptr(MSP_SLP_BASE + 0x190)
diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_usb.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_usb.h
new file mode 100644
index 00000000000..4c9348df9df
--- /dev/null
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_usb.h
@@ -0,0 +1,144 @@
1/******************************************************************
2 * Copyright (c) 2000-2007 PMC-Sierra INC.
3 *
4 * This program is free software; you can redistribute it
5 * and/or modify it under the terms of the GNU General
6 * Public License as published by the Free Software
7 * Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be
11 * useful, but WITHOUT ANY WARRANTY; without even the implied
12 * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
13 * PURPOSE. See the GNU General Public License for more
14 * details.
15 *
16 * You should have received a copy of the GNU General Public
17 * License along with this program; if not, write to the Free
18 * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
19 * 02139, USA.
20 *
21 * PMC-SIERRA INC. DISCLAIMS ANY LIABILITY OF ANY KIND
22 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS
23 * SOFTWARE.
24 */
25#ifndef MSP_USB_H_
26#define MSP_USB_H_
27
28#ifdef CONFIG_MSP_HAS_DUAL_USB
29#define NUM_USB_DEVS 2
30#else
31#define NUM_USB_DEVS 1
32#endif
33
34/* Register spaces for USB host 0 */
35#define MSP_USB0_MAB_START (MSP_USB0_BASE + 0x0)
36#define MSP_USB0_MAB_END (MSP_USB0_BASE + 0x17)
37#define MSP_USB0_ID_START (MSP_USB0_BASE + 0x40000)
38#define MSP_USB0_ID_END (MSP_USB0_BASE + 0x4008f)
39#define MSP_USB0_HS_START (MSP_USB0_BASE + 0x40100)
40#define MSP_USB0_HS_END (MSP_USB0_BASE + 0x401FF)
41
42/* Register spaces for USB host 1 */
43#define MSP_USB1_MAB_START (MSP_USB1_BASE + 0x0)
44#define MSP_USB1_MAB_END (MSP_USB1_BASE + 0x17)
45#define MSP_USB1_ID_START (MSP_USB1_BASE + 0x40000)
46#define MSP_USB1_ID_END (MSP_USB1_BASE + 0x4008f)
47#define MSP_USB1_HS_START (MSP_USB1_BASE + 0x40100)
48#define MSP_USB1_HS_END (MSP_USB1_BASE + 0x401ff)
49
50/* USB Identification registers */
51struct msp_usbid_regs {
52 u32 id; /* 0x0: Identification register */
53 u32 hwgen; /* 0x4: General HW params */
54 u32 hwhost; /* 0x8: Host HW params */
55 u32 hwdev; /* 0xc: Device HW params */
56 u32 hwtxbuf; /* 0x10: Tx buffer HW params */
57 u32 hwrxbuf; /* 0x14: Rx buffer HW params */
58 u32 reserved[26];
59 u32 timer0_load; /* 0x80: General-purpose timer 0 load*/
60 u32 timer0_ctrl; /* 0x84: General-purpose timer 0 control */
61 u32 timer1_load; /* 0x88: General-purpose timer 1 load*/
62 u32 timer1_ctrl; /* 0x8c: General-purpose timer 1 control */
63};
64
65/* MSBus to AMBA registers */
66struct msp_mab_regs {
67 u32 isr; /* 0x0: Interrupt status */
68 u32 imr; /* 0x4: Interrupt mask */
69 u32 thcr0; /* 0x8: Transaction header capture 0 */
70 u32 thcr1; /* 0xc: Transaction header capture 1 */
71 u32 int_stat; /* 0x10: Interrupt status summary */
72 u32 phy_cfg; /* 0x14: USB phy config */
73};
74
75/* EHCI registers */
76struct msp_usbhs_regs {
77 u32 hciver; /* 0x0: Version and offset to operational regs */
78 u32 hcsparams; /* 0x4: Host control structural parameters */
79 u32 hccparams; /* 0x8: Host control capability parameters */
80 u32 reserved0[5];
81 u32 dciver; /* 0x20: Device interface version */
82 u32 dccparams; /* 0x24: Device control capability parameters */
83 u32 reserved1[6];
84 u32 cmd; /* 0x40: USB command */
85 u32 sts; /* 0x44: USB status */
86 u32 int_ena; /* 0x48: USB interrupt enable */
87 u32 frindex; /* 0x4c: Frame index */
88 u32 reserved3;
89 union {
90 struct {
91 u32 flb_addr; /* 0x54: Frame list base address */
92 u32 next_async_addr; /* 0x58: next asynchronous addr */
93 u32 ttctrl; /* 0x5c: embedded transaction translator
94 async buffer status */
95 u32 burst_size; /* 0x60: Controller burst size */
96 u32 tx_fifo_ctrl; /* 0x64: Tx latency FIFO tuning */
97 u32 reserved0[4];
98 u32 endpt_nak; /* 0x78: Endpoint NAK */
99 u32 endpt_nak_ena; /* 0x7c: Endpoint NAK enable */
100 u32 cfg_flag; /* 0x80: Config flag */
101 u32 port_sc1; /* 0x84: Port status & control 1 */
102 u32 reserved1[7];
103 u32 otgsc; /* 0xa4: OTG status & control */
104 u32 mode; /* 0xa8: USB controller mode */
105 } host;
106
107 struct {
108 u32 dev_addr; /* 0x54: Device address */
109 u32 endpt_list_addr; /* 0x58: Endpoint list address */
110 u32 reserved0[7];
111 u32 endpt_nak; /* 0x74 */
112 u32 endpt_nak_ctrl; /* 0x78 */
113 u32 cfg_flag; /* 0x80 */
114 u32 port_sc1; /* 0x84: Port status & control 1 */
115 u32 reserved[7];
116 u32 otgsc; /* 0xa4: OTG status & control */
117 u32 mode; /* 0xa8: USB controller mode */
118 u32 endpt_setup_stat; /* 0xac */
119 u32 endpt_prime; /* 0xb0 */
120 u32 endpt_flush; /* 0xb4 */
121 u32 endpt_stat; /* 0xb8 */
122 u32 endpt_complete; /* 0xbc */
123 u32 endpt_ctrl0; /* 0xc0 */
124 u32 endpt_ctrl1; /* 0xc4 */
125 u32 endpt_ctrl2; /* 0xc8 */
126 u32 endpt_ctrl3; /* 0xcc */
127 } device;
128 } u;
129};
130/*
131 * Container for the more-generic platform_device.
132 * This exists mainly as a way to map the non-standard register
133 * spaces and make them accessible to the USB ISR.
134 */
135struct mspusb_device {
136 struct msp_mab_regs __iomem *mab_regs;
137 struct msp_usbid_regs __iomem *usbid_regs;
138 struct msp_usbhs_regs __iomem *usbhs_regs;
139 struct platform_device dev;
140};
141
142#define to_mspusb_device(x) container_of((x), struct mspusb_device, dev)
143#define TO_HOST_ID(x) ((x) & 0x3)
144#endif /*MSP_USB_H_*/
diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
index ead6928fa6b..c104f1039a6 100644
--- a/arch/mips/include/asm/processor.h
+++ b/arch/mips/include/asm/processor.h
@@ -337,7 +337,7 @@ unsigned long get_wchan(struct task_struct *p);
337/* 337/*
338 * Return_address is a replacement for __builtin_return_address(count) 338 * Return_address is a replacement for __builtin_return_address(count)
339 * which on certain architectures cannot reasonably be implemented in GCC 339 * which on certain architectures cannot reasonably be implemented in GCC
340 * (MIPS, Alpha) or is unuseable with -fomit-frame-pointer (i386). 340 * (MIPS, Alpha) or is unusable with -fomit-frame-pointer (i386).
341 * Note that __builtin_return_address(x>=1) is forbidden because GCC 341 * Note that __builtin_return_address(x>=1) is forbidden because GCC
342 * aborts compilation on some CPUs. It's simply not possible to unwind 342 * aborts compilation on some CPUs. It's simply not possible to unwind
343 * some CPU's stackframes. 343 * some CPU's stackframes.
diff --git a/arch/mips/include/asm/sgi/ioc.h b/arch/mips/include/asm/sgi/ioc.h
index 57a971904cf..380347b648e 100644
--- a/arch/mips/include/asm/sgi/ioc.h
+++ b/arch/mips/include/asm/sgi/ioc.h
@@ -17,7 +17,7 @@
17#include <asm/sgi/pi1.h> 17#include <asm/sgi/pi1.h>
18 18
19/* 19/*
20 * All registers are 8-bit wide alligned on 32-bit boundary. Bad things 20 * All registers are 8-bit wide aligned on 32-bit boundary. Bad things
21 * happen if you try word access them. You have been warned. 21 * happen if you try word access them. You have been warned.
22 */ 22 */
23 23
diff --git a/arch/mips/include/asm/sibyte/sb1250_mac.h b/arch/mips/include/asm/sibyte/sb1250_mac.h
index 591b9061fd8..77f78728423 100644
--- a/arch/mips/include/asm/sibyte/sb1250_mac.h
+++ b/arch/mips/include/asm/sibyte/sb1250_mac.h
@@ -520,7 +520,7 @@
520#define G_MAC_RX_EOP_COUNTER(x) _SB_GETVALUE(x, S_MAC_RX_EOP_COUNTER, M_MAC_RX_EOP_COUNTER) 520#define G_MAC_RX_EOP_COUNTER(x) _SB_GETVALUE(x, S_MAC_RX_EOP_COUNTER, M_MAC_RX_EOP_COUNTER)
521 521
522/* 522/*
523 * MAC Recieve Address Filter Exact Match Registers (Table 9-21) 523 * MAC Receive Address Filter Exact Match Registers (Table 9-21)
524 * Registers: MAC_ADDR0_0 through MAC_ADDR7_0 524 * Registers: MAC_ADDR0_0 through MAC_ADDR7_0
525 * Registers: MAC_ADDR0_1 through MAC_ADDR7_1 525 * Registers: MAC_ADDR0_1 through MAC_ADDR7_1
526 * Registers: MAC_ADDR0_2 through MAC_ADDR7_2 526 * Registers: MAC_ADDR0_2 through MAC_ADDR7_2
@@ -538,7 +538,7 @@
538/* No bitfields */ 538/* No bitfields */
539 539
540/* 540/*
541 * MAC Recieve Address Filter Hash Match Registers (Table 9-22) 541 * MAC Receive Address Filter Hash Match Registers (Table 9-22)
542 * Registers: MAC_HASH0_0 through MAC_HASH7_0 542 * Registers: MAC_HASH0_0 through MAC_HASH7_0
543 * Registers: MAC_HASH0_1 through MAC_HASH7_1 543 * Registers: MAC_HASH0_1 through MAC_HASH7_1
544 * Registers: MAC_HASH0_2 through MAC_HASH7_2 544 * Registers: MAC_HASH0_2 through MAC_HASH7_2
diff --git a/arch/mips/include/asm/siginfo.h b/arch/mips/include/asm/siginfo.h
index 1ca64b4d33d..20ebeb875ee 100644
--- a/arch/mips/include/asm/siginfo.h
+++ b/arch/mips/include/asm/siginfo.h
@@ -101,7 +101,7 @@ typedef struct siginfo {
101 101
102/* 102/*
103 * si_code values 103 * si_code values
104 * Again these have been choosen to be IRIX compatible. 104 * Again these have been chosen to be IRIX compatible.
105 */ 105 */
106#undef SI_ASYNCIO 106#undef SI_ASYNCIO
107#undef SI_TIMER 107#undef SI_TIMER
diff --git a/arch/mips/include/asm/sn/klconfig.h b/arch/mips/include/asm/sn/klconfig.h
index 09e590daca1..fe02900b930 100644
--- a/arch/mips/include/asm/sn/klconfig.h
+++ b/arch/mips/include/asm/sn/klconfig.h
@@ -78,7 +78,7 @@ typedef s32 klconf_off_t;
78 */ 78 */
79#define MAX_SLOTS_PER_NODE (1 + 2 + 6 + 2) 79#define MAX_SLOTS_PER_NODE (1 + 2 + 6 + 2)
80 80
81/* XXX if each node is guranteed to have some memory */ 81/* XXX if each node is guaranteed to have some memory */
82 82
83#define MAX_PCI_DEVS 8 83#define MAX_PCI_DEVS 8
84 84
@@ -539,7 +539,7 @@ typedef struct klinfo_s { /* Generic info */
539#define KLSTRUCT_IOC3_TTY 24 539#define KLSTRUCT_IOC3_TTY 24
540 540
541/* Early Access IO proms are compatible 541/* Early Access IO proms are compatible
542 only with KLSTRUCT values upto 24. */ 542 only with KLSTRUCT values up to 24. */
543 543
544#define KLSTRUCT_FIBERCHANNEL 25 544#define KLSTRUCT_FIBERCHANNEL 25
545#define KLSTRUCT_MOD_SERIAL_NUM 26 545#define KLSTRUCT_MOD_SERIAL_NUM 26
diff --git a/arch/mips/include/asm/sn/sn0/hubio.h b/arch/mips/include/asm/sn/sn0/hubio.h
index 31c76c021bb..46286d8302a 100644
--- a/arch/mips/include/asm/sn/sn0/hubio.h
+++ b/arch/mips/include/asm/sn/sn0/hubio.h
@@ -622,7 +622,7 @@ typedef union h1_icrbb_u {
622 */ 622 */
623#define IIO_ICRB_PROC0 0 /* Source of request is Proc 0 */ 623#define IIO_ICRB_PROC0 0 /* Source of request is Proc 0 */
624#define IIO_ICRB_PROC1 1 /* Source of request is Proc 1 */ 624#define IIO_ICRB_PROC1 1 /* Source of request is Proc 1 */
625#define IIO_ICRB_GB_REQ 2 /* Source is Guranteed BW request */ 625#define IIO_ICRB_GB_REQ 2 /* Source is Guaranteed BW request */
626#define IIO_ICRB_IO_REQ 3 /* Source is Normal IO request */ 626#define IIO_ICRB_IO_REQ 3 /* Source is Normal IO request */
627 627
628/* 628/*
diff --git a/arch/mips/include/asm/spinlock.h b/arch/mips/include/asm/spinlock.h
index 396e402fbe2..ca61e846ab0 100644
--- a/arch/mips/include/asm/spinlock.h
+++ b/arch/mips/include/asm/spinlock.h
@@ -245,16 +245,16 @@ static inline void arch_read_lock(arch_rwlock_t *rw)
245 __asm__ __volatile__( 245 __asm__ __volatile__(
246 " .set noreorder # arch_read_lock \n" 246 " .set noreorder # arch_read_lock \n"
247 "1: ll %1, %2 \n" 247 "1: ll %1, %2 \n"
248 " bltz %1, 2f \n" 248 " bltz %1, 3f \n"
249 " addu %1, 1 \n" 249 " addu %1, 1 \n"
250 " sc %1, %0 \n" 250 "2: sc %1, %0 \n"
251 " beqz %1, 1b \n" 251 " beqz %1, 1b \n"
252 " nop \n" 252 " nop \n"
253 " .subsection 2 \n" 253 " .subsection 2 \n"
254 "2: ll %1, %2 \n" 254 "3: ll %1, %2 \n"
255 " bltz %1, 2b \n" 255 " bltz %1, 3b \n"
256 " addu %1, 1 \n" 256 " addu %1, 1 \n"
257 " b 1b \n" 257 " b 2b \n"
258 " nop \n" 258 " nop \n"
259 " .previous \n" 259 " .previous \n"
260 " .set reorder \n" 260 " .set reorder \n"
@@ -324,16 +324,16 @@ static inline void arch_write_lock(arch_rwlock_t *rw)
324 __asm__ __volatile__( 324 __asm__ __volatile__(
325 " .set noreorder # arch_write_lock \n" 325 " .set noreorder # arch_write_lock \n"
326 "1: ll %1, %2 \n" 326 "1: ll %1, %2 \n"
327 " bnez %1, 2f \n" 327 " bnez %1, 3f \n"
328 " lui %1, 0x8000 \n" 328 " lui %1, 0x8000 \n"
329 " sc %1, %0 \n" 329 "2: sc %1, %0 \n"
330 " beqz %1, 2f \n" 330 " beqz %1, 3f \n"
331 " nop \n" 331 " nop \n"
332 " .subsection 2 \n" 332 " .subsection 2 \n"
333 "2: ll %1, %2 \n" 333 "3: ll %1, %2 \n"
334 " bnez %1, 2b \n" 334 " bnez %1, 3b \n"
335 " lui %1, 0x8000 \n" 335 " lui %1, 0x8000 \n"
336 " b 1b \n" 336 " b 2b \n"
337 " nop \n" 337 " nop \n"
338 " .previous \n" 338 " .previous \n"
339 " .set reorder \n" 339 " .set reorder \n"
diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
index 58730c5ce4b..b4ba2449444 100644
--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
@@ -346,7 +346,7 @@
346 * we can't dispatch it directly without trashing 346 * we can't dispatch it directly without trashing
347 * some registers, so we'll try to detect this unlikely 347 * some registers, so we'll try to detect this unlikely
348 * case and program a software interrupt in the VPE, 348 * case and program a software interrupt in the VPE,
349 * as would be done for a cross-VPE IPI. To accomodate 349 * as would be done for a cross-VPE IPI. To accommodate
350 * the handling of that case, we're doing a DVPE instead 350 * the handling of that case, we're doing a DVPE instead
351 * of just a DMT here to protect against other threads. 351 * of just a DMT here to protect against other threads.
352 * This is a lot of cruft to cover a tiny window. 352 * This is a lot of cruft to cover a tiny window.
diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h
index d309556cacf..d71160de4d1 100644
--- a/arch/mips/include/asm/thread_info.h
+++ b/arch/mips/include/asm/thread_info.h
@@ -88,9 +88,11 @@ register struct thread_info *__current_thread_info __asm__("$28");
88#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR 88#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
89 89
90#ifdef CONFIG_DEBUG_STACK_USAGE 90#ifdef CONFIG_DEBUG_STACK_USAGE
91#define alloc_thread_info(tsk) kzalloc(THREAD_SIZE, GFP_KERNEL) 91#define alloc_thread_info_node(tsk, node) \
92 kzalloc_node(THREAD_SIZE, GFP_KERNEL, node)
92#else 93#else
93#define alloc_thread_info(tsk) kmalloc(THREAD_SIZE, GFP_KERNEL) 94#define alloc_thread_info_node(tsk, node) \
95 kmalloc_node(THREAD_SIZE, GFP_KERNEL, node)
94#endif 96#endif
95 97
96#define free_thread_info(info) kfree(info) 98#define free_thread_info(info) kfree(info)
diff --git a/arch/mips/include/asm/types.h b/arch/mips/include/asm/types.h
index 544a2854598..533812b6188 100644
--- a/arch/mips/include/asm/types.h
+++ b/arch/mips/include/asm/types.h
@@ -33,14 +33,6 @@ typedef unsigned short umode_t;
33#ifdef __KERNEL__ 33#ifdef __KERNEL__
34#ifndef __ASSEMBLY__ 34#ifndef __ASSEMBLY__
35 35
36#if (defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR)) \
37 || defined(CONFIG_64BIT)
38typedef u64 dma_addr_t;
39#else
40typedef u32 dma_addr_t;
41#endif
42typedef u64 dma64_addr_t;
43
44/* 36/*
45 * Don't use phys_t. You've been warned. 37 * Don't use phys_t. You've been warned.
46 */ 38 */
diff --git a/arch/mips/include/asm/unistd.h b/arch/mips/include/asm/unistd.h
index 550725b881d..fa2e37ea2be 100644
--- a/arch/mips/include/asm/unistd.h
+++ b/arch/mips/include/asm/unistd.h
@@ -359,16 +359,20 @@
359#define __NR_fanotify_init (__NR_Linux + 336) 359#define __NR_fanotify_init (__NR_Linux + 336)
360#define __NR_fanotify_mark (__NR_Linux + 337) 360#define __NR_fanotify_mark (__NR_Linux + 337)
361#define __NR_prlimit64 (__NR_Linux + 338) 361#define __NR_prlimit64 (__NR_Linux + 338)
362#define __NR_name_to_handle_at (__NR_Linux + 339)
363#define __NR_open_by_handle_at (__NR_Linux + 340)
364#define __NR_clock_adjtime (__NR_Linux + 341)
365#define __NR_syncfs (__NR_Linux + 342)
362 366
363/* 367/*
364 * Offset of the last Linux o32 flavoured syscall 368 * Offset of the last Linux o32 flavoured syscall
365 */ 369 */
366#define __NR_Linux_syscalls 338 370#define __NR_Linux_syscalls 342
367 371
368#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ 372#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
369 373
370#define __NR_O32_Linux 4000 374#define __NR_O32_Linux 4000
371#define __NR_O32_Linux_syscalls 338 375#define __NR_O32_Linux_syscalls 342
372 376
373#if _MIPS_SIM == _MIPS_SIM_ABI64 377#if _MIPS_SIM == _MIPS_SIM_ABI64
374 378
@@ -674,16 +678,20 @@
674#define __NR_fanotify_init (__NR_Linux + 295) 678#define __NR_fanotify_init (__NR_Linux + 295)
675#define __NR_fanotify_mark (__NR_Linux + 296) 679#define __NR_fanotify_mark (__NR_Linux + 296)
676#define __NR_prlimit64 (__NR_Linux + 297) 680#define __NR_prlimit64 (__NR_Linux + 297)
681#define __NR_name_to_handle_at (__NR_Linux + 298)
682#define __NR_open_by_handle_at (__NR_Linux + 299)
683#define __NR_clock_adjtime (__NR_Linux + 300)
684#define __NR_syncfs (__NR_Linux + 301)
677 685
678/* 686/*
679 * Offset of the last Linux 64-bit flavoured syscall 687 * Offset of the last Linux 64-bit flavoured syscall
680 */ 688 */
681#define __NR_Linux_syscalls 297 689#define __NR_Linux_syscalls 301
682 690
683#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */ 691#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
684 692
685#define __NR_64_Linux 5000 693#define __NR_64_Linux 5000
686#define __NR_64_Linux_syscalls 297 694#define __NR_64_Linux_syscalls 301
687 695
688#if _MIPS_SIM == _MIPS_SIM_NABI32 696#if _MIPS_SIM == _MIPS_SIM_NABI32
689 697
@@ -994,16 +1002,20 @@
994#define __NR_fanotify_init (__NR_Linux + 300) 1002#define __NR_fanotify_init (__NR_Linux + 300)
995#define __NR_fanotify_mark (__NR_Linux + 301) 1003#define __NR_fanotify_mark (__NR_Linux + 301)
996#define __NR_prlimit64 (__NR_Linux + 302) 1004#define __NR_prlimit64 (__NR_Linux + 302)
1005#define __NR_name_to_handle_at (__NR_Linux + 303)
1006#define __NR_open_by_handle_at (__NR_Linux + 304)
1007#define __NR_clock_adjtime (__NR_Linux + 305)
1008#define __NR_syncfs (__NR_Linux + 306)
997 1009
998/* 1010/*
999 * Offset of the last N32 flavoured syscall 1011 * Offset of the last N32 flavoured syscall
1000 */ 1012 */
1001#define __NR_Linux_syscalls 302 1013#define __NR_Linux_syscalls 306
1002 1014
1003#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */ 1015#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
1004 1016
1005#define __NR_N32_Linux 6000 1017#define __NR_N32_Linux 6000
1006#define __NR_N32_Linux_syscalls 302 1018#define __NR_N32_Linux_syscalls 306
1007 1019
1008#ifdef __KERNEL__ 1020#ifdef __KERNEL__
1009 1021
diff --git a/arch/mips/include/asm/war.h b/arch/mips/include/asm/war.h
index 22361d5e3bf..fa133c1bc1f 100644
--- a/arch/mips/include/asm/war.h
+++ b/arch/mips/include/asm/war.h
@@ -227,7 +227,7 @@
227#endif 227#endif
228 228
229/* 229/*
230 * On the R10000 upto version 2.6 (not sure about 2.7) there is a bug that 230 * On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
231 * may cause ll / sc and lld / scd sequences to execute non-atomically. 231 * may cause ll / sc and lld / scd sequences to execute non-atomically.
232 */ 232 */
233#ifndef R10000_LLSC_WAR 233#ifndef R10000_LLSC_WAR
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-07 02:48:40 -0500