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authorDavid Daney <ddaney@caviumnetworks.com>2009-10-14 15:16:56 -0400
committerRalf Baechle <ralf@linux-mips.org>2009-12-16 20:57:01 -0500
commit82622284dd2f8791f9759f3cef601520a8bc63b2 (patch)
treeee47f43af373d0c021cc83ff9e22925942e9d001 /arch/mips/include/asm/stackframe.h
parent92078e0618f525e22945040b5daea21d4b6d4a16 (diff)
MIPS: Put PGD in C0_CONTEXT for 64-bit R2 processors.
Processors that support the mips64r2 ISA can in four instructions convert a shifted PGD pointer stored in the upper bits of c0_context into a usable pointer. By doing this we save a memory load and associated potential cache miss in the TLB exception handlers. Since the upper bits of c0_context were holding the CPU number, we move this to the upper bits of c0_xcontext which doesn't have enough bits to hold the PGD pointer, but has plenty for the CPU number. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/stackframe.h')
-rw-r--r--arch/mips/include/asm/stackframe.h20
1 files changed, 10 insertions, 10 deletions
diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
index dd7e220e087..3b6da3330e3 100644
--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
@@ -87,15 +87,19 @@
87#ifdef CONFIG_SMP 87#ifdef CONFIG_SMP
88#ifdef CONFIG_MIPS_MT_SMTC 88#ifdef CONFIG_MIPS_MT_SMTC
89#define PTEBASE_SHIFT 19 /* TCBIND */ 89#define PTEBASE_SHIFT 19 /* TCBIND */
90#define CPU_ID_REG CP0_TCBIND
91#define CPU_ID_MFC0 mfc0
92#elif defined(CONFIG_MIPS_PGD_C0_CONTEXT)
93#define PTEBASE_SHIFT 48 /* XCONTEXT */
94#define CPU_ID_REG CP0_XCONTEXT
95#define CPU_ID_MFC0 MFC0
90#else 96#else
91#define PTEBASE_SHIFT 23 /* CONTEXT */ 97#define PTEBASE_SHIFT 23 /* CONTEXT */
98#define CPU_ID_REG CP0_CONTEXT
99#define CPU_ID_MFC0 MFC0
92#endif 100#endif
93 .macro get_saved_sp /* SMP variation */ 101 .macro get_saved_sp /* SMP variation */
94#ifdef CONFIG_MIPS_MT_SMTC 102 CPU_ID_MFC0 k0, CPU_ID_REG
95 mfc0 k0, CP0_TCBIND
96#else
97 MFC0 k0, CP0_CONTEXT
98#endif
99#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) 103#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
100 lui k1, %hi(kernelsp) 104 lui k1, %hi(kernelsp)
101#else 105#else
@@ -111,11 +115,7 @@
111 .endm 115 .endm
112 116
113 .macro set_saved_sp stackp temp temp2 117 .macro set_saved_sp stackp temp temp2
114#ifdef CONFIG_MIPS_MT_SMTC 118 CPU_ID_MFC0 \temp, CPU_ID_REG
115 mfc0 \temp, CP0_TCBIND
116#else
117 MFC0 \temp, CP0_CONTEXT
118#endif
119 LONG_SRL \temp, PTEBASE_SHIFT 119 LONG_SRL \temp, PTEBASE_SHIFT
120 LONG_S \stackp, kernelsp(\temp) 120 LONG_S \stackp, kernelsp(\temp)
121 .endm 121 .endm