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authorRalf Baechle <ralf@linux-mips.org>2009-06-23 05:36:38 -0400
committerRalf Baechle <ralf@linux-mips.org>2009-06-24 13:34:40 -0400
commit773cb77d0e32f0a3c36edf5aaeb9642c18038cd2 (patch)
treef604b52d75aaeffe4c432437f339f13c9e099265 /arch/mips/cavium-octeon/smp.c
parent9801b321ecdb6708365b6825bf728c8e433fca00 (diff)
MIPS: Cavium: Add CPU hotplugging code.
Thanks to Cavium Inc. for the code contribution and help. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/cavium-octeon/smp.c')
-rw-r--r--arch/mips/cavium-octeon/smp.c234
1 files changed, 233 insertions, 1 deletions
diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c
index 24e0ad63980..0b891a9c625 100644
--- a/arch/mips/cavium-octeon/smp.c
+++ b/arch/mips/cavium-octeon/smp.c
@@ -5,6 +5,7 @@
5 * 5 *
6 * Copyright (C) 2004-2008 Cavium Networks 6 * Copyright (C) 2004-2008 Cavium Networks
7 */ 7 */
8#include <linux/cpu.h>
8#include <linux/init.h> 9#include <linux/init.h>
9#include <linux/delay.h> 10#include <linux/delay.h>
10#include <linux/smp.h> 11#include <linux/smp.h>
@@ -19,10 +20,16 @@
19 20
20#include <asm/octeon/octeon.h> 21#include <asm/octeon/octeon.h>
21 22
23#include "octeon_boot.h"
24
22volatile unsigned long octeon_processor_boot = 0xff; 25volatile unsigned long octeon_processor_boot = 0xff;
23volatile unsigned long octeon_processor_sp; 26volatile unsigned long octeon_processor_sp;
24volatile unsigned long octeon_processor_gp; 27volatile unsigned long octeon_processor_gp;
25 28
29#ifdef CONFIG_HOTPLUG_CPU
30static unsigned int InitTLBStart_addr;
31#endif
32
26static irqreturn_t mailbox_interrupt(int irq, void *dev_id) 33static irqreturn_t mailbox_interrupt(int irq, void *dev_id)
27{ 34{
28 const int coreid = cvmx_get_core_num(); 35 const int coreid = cvmx_get_core_num();
@@ -67,8 +74,28 @@ static inline void octeon_send_ipi_mask(cpumask_t mask, unsigned int action)
67} 74}
68 75
69/** 76/**
70 * Detect available CPUs, populate phys_cpu_present_map 77 * Detect available CPUs, populate cpu_possible_map
71 */ 78 */
79static void octeon_smp_hotplug_setup(void)
80{
81#ifdef CONFIG_HOTPLUG_CPU
82 uint32_t labi_signature;
83
84 labi_signature =
85 cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
86 LABI_ADDR_IN_BOOTLOADER +
87 offsetof(struct linux_app_boot_info,
88 labi_signature)));
89 if (labi_signature != LABI_SIGNATURE)
90 pr_err("The bootloader version on this board is incorrect\n");
91 InitTLBStart_addr =
92 cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
93 LABI_ADDR_IN_BOOTLOADER +
94 offsetof(struct linux_app_boot_info,
95 InitTLBStart_addr)));
96#endif
97}
98
72static void octeon_smp_setup(void) 99static void octeon_smp_setup(void)
73{ 100{
74 const int coreid = cvmx_get_core_num(); 101 const int coreid = cvmx_get_core_num();
@@ -91,6 +118,9 @@ static void octeon_smp_setup(void)
91 cpus++; 118 cpus++;
92 } 119 }
93 } 120 }
121 cpu_present_map = cpu_possible_map;
122
123 octeon_smp_hotplug_setup();
94} 124}
95 125
96/** 126/**
@@ -128,6 +158,17 @@ static void octeon_init_secondary(void)
128 const int coreid = cvmx_get_core_num(); 158 const int coreid = cvmx_get_core_num();
129 union cvmx_ciu_intx_sum0 interrupt_enable; 159 union cvmx_ciu_intx_sum0 interrupt_enable;
130 160
161#ifdef CONFIG_HOTPLUG_CPU
162 unsigned int cur_exception_base;
163
164 cur_exception_base = cvmx_read64_uint32(
165 CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
166 LABI_ADDR_IN_BOOTLOADER +
167 offsetof(struct linux_app_boot_info,
168 cur_exception_base)));
169 /* cur_exception_base is incremented in bootloader after setting */
170 write_c0_ebase((unsigned int)(cur_exception_base - EXCEPTION_BASE_INCR));
171#endif
131 octeon_check_cpu_bist(); 172 octeon_check_cpu_bist();
132 octeon_init_cvmcount(); 173 octeon_init_cvmcount();
133 /* 174 /*
@@ -199,6 +240,193 @@ static void octeon_cpus_done(void)
199#endif 240#endif
200} 241}
201 242
243#ifdef CONFIG_HOTPLUG_CPU
244
245/* State of each CPU. */
246DEFINE_PER_CPU(int, cpu_state);
247
248extern void fixup_irqs(void);
249
250static DEFINE_SPINLOCK(smp_reserve_lock);
251
252static int octeon_cpu_disable(void)
253{
254 unsigned int cpu = smp_processor_id();
255
256 if (cpu == 0)
257 return -EBUSY;
258
259 spin_lock(&smp_reserve_lock);
260
261 cpu_clear(cpu, cpu_online_map);
262 cpu_clear(cpu, cpu_callin_map);
263 local_irq_disable();
264 fixup_irqs();
265 local_irq_enable();
266
267 flush_cache_all();
268 local_flush_tlb_all();
269
270 spin_unlock(&smp_reserve_lock);
271
272 return 0;
273}
274
275static void octeon_cpu_die(unsigned int cpu)
276{
277 int coreid = cpu_logical_map(cpu);
278 uint32_t avail_coremask;
279 struct cvmx_bootmem_named_block_desc *block_desc;
280
281#ifdef CONFIG_CAVIUM_OCTEON_WATCHDOG
282 /* Disable the watchdog */
283 cvmx_ciu_wdogx_t ciu_wdog;
284 ciu_wdog.u64 = cvmx_read_csr(CVMX_CIU_WDOGX(cpu));
285 ciu_wdog.s.mode = 0;
286 cvmx_write_csr(CVMX_CIU_WDOGX(cpu), ciu_wdog.u64);
287#endif
288
289 while (per_cpu(cpu_state, cpu) != CPU_DEAD)
290 cpu_relax();
291
292 /*
293 * This is a bit complicated strategics of getting/settig available
294 * cores mask, copied from bootloader
295 */
296 /* LINUX_APP_BOOT_BLOCK is initialized in bootoct binary */
297 block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
298
299 if (!block_desc) {
300 avail_coremask =
301 cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
302 LABI_ADDR_IN_BOOTLOADER +
303 offsetof
304 (struct linux_app_boot_info,
305 avail_coremask)));
306 } else { /* alternative, already initialized */
307 avail_coremask =
308 cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
309 block_desc->base_addr +
310 AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK));
311 }
312
313 avail_coremask |= 1 << coreid;
314
315 /* Setting avail_coremask for bootoct binary */
316 if (!block_desc) {
317 cvmx_write64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
318 LABI_ADDR_IN_BOOTLOADER +
319 offsetof(struct linux_app_boot_info,
320 avail_coremask)),
321 avail_coremask);
322 } else {
323 cvmx_write64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
324 block_desc->base_addr +
325 AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK),
326 avail_coremask);
327 }
328
329 pr_info("Reset core %d. Available Coremask = %x \n", coreid,
330 avail_coremask);
331 cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
332 cvmx_write_csr(CVMX_CIU_PP_RST, 0);
333}
334
335void play_dead(void)
336{
337 int coreid = cvmx_get_core_num();
338
339 idle_task_exit();
340 octeon_processor_boot = 0xff;
341 per_cpu(cpu_state, coreid) = CPU_DEAD;
342
343 while (1) /* core will be reset here */
344 ;
345}
346
347extern void kernel_entry(unsigned long arg1, ...);
348
349static void start_after_reset(void)
350{
351 kernel_entry(0, 0, 0); /* set a2 = 0 for secondary core */
352}
353
354int octeon_update_boot_vector(unsigned int cpu)
355{
356
357 int coreid = cpu_logical_map(cpu);
358 unsigned int avail_coremask;
359 struct cvmx_bootmem_named_block_desc *block_desc;
360 struct boot_init_vector *boot_vect =
361 (struct boot_init_vector *) cvmx_phys_to_ptr(0x0 +
362 BOOTLOADER_BOOT_VECTOR);
363
364 block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
365
366 if (!block_desc) {
367 avail_coremask =
368 cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
369 LABI_ADDR_IN_BOOTLOADER +
370 offsetof(struct linux_app_boot_info,
371 avail_coremask)));
372 } else { /* alternative, already initialized */
373 avail_coremask =
374 cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
375 block_desc->base_addr +
376 AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK));
377 }
378
379 if (!(avail_coremask & (1 << coreid))) {
380 /* core not available, assume, that catched by simple-executive */
381 cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
382 cvmx_write_csr(CVMX_CIU_PP_RST, 0);
383 }
384
385 boot_vect[coreid].app_start_func_addr =
386 (uint32_t) (unsigned long) start_after_reset;
387 boot_vect[coreid].code_addr = InitTLBStart_addr;
388
389 CVMX_SYNC;
390
391 cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask);
392
393 return 0;
394}
395
396static int __cpuinit octeon_cpu_callback(struct notifier_block *nfb,
397 unsigned long action, void *hcpu)
398{
399 unsigned int cpu = (unsigned long)hcpu;
400
401 switch (action) {
402 case CPU_UP_PREPARE:
403 octeon_update_boot_vector(cpu);
404 break;
405 case CPU_ONLINE:
406 pr_info("Cpu %d online\n", cpu);
407 break;
408 case CPU_DEAD:
409 break;
410 }
411
412 return NOTIFY_OK;
413}
414
415static struct notifier_block __cpuinitdata octeon_cpu_notifier = {
416 .notifier_call = octeon_cpu_callback,
417};
418
419static int __cpuinit register_cavium_notifier(void)
420{
421 register_hotcpu_notifier(&octeon_cpu_notifier);
422
423 return 0;
424}
425
426late_initcall(register_cavium_notifier);
427
428#endif /* CONFIG_HOTPLUG_CPU */
429
202struct plat_smp_ops octeon_smp_ops = { 430struct plat_smp_ops octeon_smp_ops = {
203 .send_ipi_single = octeon_send_ipi_single, 431 .send_ipi_single = octeon_send_ipi_single,
204 .send_ipi_mask = octeon_send_ipi_mask, 432 .send_ipi_mask = octeon_send_ipi_mask,
@@ -208,4 +436,8 @@ struct plat_smp_ops octeon_smp_ops = {
208 .boot_secondary = octeon_boot_secondary, 436 .boot_secondary = octeon_boot_secondary,
209 .smp_setup = octeon_smp_setup, 437 .smp_setup = octeon_smp_setup,
210 .prepare_cpus = octeon_prepare_cpus, 438 .prepare_cpus = octeon_prepare_cpus,
439#ifdef CONFIG_HOTPLUG_CPU
440 .cpu_disable = octeon_cpu_disable,
441 .cpu_die = octeon_cpu_die,
442#endif
211}; 443};