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authorManuel Lauss <manuel.lauss@googlemail.com>2009-06-06 08:09:55 -0400
committerRalf Baechle <ralf@linux-mips.org>2009-06-17 06:06:28 -0400
commit51e02b02e650183ff1277bcbad6a01d6ea0e9edb (patch)
tree413dfa5c93e2d01a42309f1cee6d6bf26d871962 /arch/mips/alchemy/Kconfig
parenteeb09e6545bf68222798ccf3f355560a9e406435 (diff)
MIPS: Alchemy: Rewrite GPIO support.
The current in-kernel Alchemy GPIO support is far too inflexible for all my use cases. To address this, the following changes are made: * create generic functions which deal with manipulating the on-chip GPIO1/2 blocks. Such functions are universally useful. * Macros for GPIO2 shared interrupt management and block control. * support for both built-in CONFIG_GPIOLIB and fast, inlined GPIO macros. If CONFIG_GPIOLIB is not enabled, provide linux gpio framework compatibility by directly inlining the GPIO1/2 functions. GPIO access is limited to on-chip ones and they can be accessed as documented in the datasheets (GPIO0-31 and 200-215). If CONFIG_GPIOLIB is selected, two (2) gpio_chip-s, one for GPIO1 and one for GPIO2, are registered. GPIOs can still be accessed by using the numberspace established in the databooks. However this is not yet flexible enough for my uses: My Alchemy systems have a documented "external" gpio interface (fixed, different numberspace) and can support a variety of baseboards, some of which are equipped with I2C gpio expanders. I want to be able to provide the default 16 GPIOs of the CPU board numbered as 0..15 and also support gpio expanders, if present, starting as gpio16. To achieve this, a new Kconfig symbol for Alchemy is introduced, CONFIG_ALCHEMY_GPIO_INDIRECT, which boards can enable to signal that they don't want the Alchemy numberspace exposed to the outside world, but instead want to provide their own. Boards are now respon- sible for providing the linux gpio interface glue code (either in a custom gpio.h header (in board include directory) or with gpio_chips). To make the board-specific inlined gpio functions work, the MIPS Makefile must be changed so that the mach-au1x00/gpio.h header is included _after_ the board headers, by moving the inclusion of the mach-au1x00/ to the end of the header list. See arch/mips/include/asm/mach-au1x00/gpio.h for more info. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Acked-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/alchemy/Kconfig')
-rw-r--r--arch/mips/alchemy/Kconfig19
1 files changed, 18 insertions, 1 deletions
diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig
index 8128aebfb15..00b498e97c8 100644
--- a/arch/mips/alchemy/Kconfig
+++ b/arch/mips/alchemy/Kconfig
@@ -1,3 +1,14 @@
1# au1000-style gpio
2config ALCHEMY_GPIO_AU1000
3 bool
4
5# select this in your board config if you don't want to use the gpio
6# namespace as documented in the manuals. In this case however you need
7# to create the necessary gpio_* functions in your board code/headers!
8# see arch/mips/include/asm/mach-au1x00/gpio.h for more information.
9config ALCHEMY_GPIO_INDIRECT
10 def_bool n
11
1choice 12choice
2 prompt "Machine type" 13 prompt "Machine type"
3 depends on MACH_ALCHEMY 14 depends on MACH_ALCHEMY
@@ -108,22 +119,27 @@ endchoice
108config SOC_AU1000 119config SOC_AU1000
109 bool 120 bool
110 select SOC_AU1X00 121 select SOC_AU1X00
122 select ALCHEMY_GPIO_AU1000
111 123
112config SOC_AU1100 124config SOC_AU1100
113 bool 125 bool
114 select SOC_AU1X00 126 select SOC_AU1X00
127 select ALCHEMY_GPIO_AU1000
115 128
116config SOC_AU1500 129config SOC_AU1500
117 bool 130 bool
118 select SOC_AU1X00 131 select SOC_AU1X00
132 select ALCHEMY_GPIO_AU1000
119 133
120config SOC_AU1550 134config SOC_AU1550
121 bool 135 bool
122 select SOC_AU1X00 136 select SOC_AU1X00
137 select ALCHEMY_GPIO_AU1000
123 138
124config SOC_AU1200 139config SOC_AU1200
125 bool 140 bool
126 select SOC_AU1X00 141 select SOC_AU1X00
142 select ALCHEMY_GPIO_AU1000
127 143
128config SOC_AU1X00 144config SOC_AU1X00
129 bool 145 bool
@@ -134,4 +150,5 @@ config SOC_AU1X00
134 select SYS_HAS_CPU_MIPS32_R1 150 select SYS_HAS_CPU_MIPS32_R1
135 select SYS_SUPPORTS_32BIT_KERNEL 151 select SYS_SUPPORTS_32BIT_KERNEL
136 select SYS_SUPPORTS_APM_EMULATION 152 select SYS_SUPPORTS_APM_EMULATION
137 select ARCH_REQUIRE_GPIOLIB 153 select GENERIC_GPIO
154 select ARCH_WANT_OPTIONAL_GPIOLIB