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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /arch/i386/pci
Linux-2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'arch/i386/pci')
-rw-r--r--arch/i386/pci/Makefile14
-rw-r--r--arch/i386/pci/acpi.c53
-rw-r--r--arch/i386/pci/common.c251
-rw-r--r--arch/i386/pci/direct.c289
-rw-r--r--arch/i386/pci/fixup.c386
-rw-r--r--arch/i386/pci/i386.c304
-rw-r--r--arch/i386/pci/irq.c1119
-rw-r--r--arch/i386/pci/legacy.c54
-rw-r--r--arch/i386/pci/mmconfig.c122
-rw-r--r--arch/i386/pci/numa.c130
-rw-r--r--arch/i386/pci/pcbios.c487
-rw-r--r--arch/i386/pci/pci.h74
-rw-r--r--arch/i386/pci/visws.c110
13 files changed, 3393 insertions, 0 deletions
diff --git a/arch/i386/pci/Makefile b/arch/i386/pci/Makefile
new file mode 100644
index 00000000000..1bff03f3696
--- /dev/null
+++ b/arch/i386/pci/Makefile
@@ -0,0 +1,14 @@
1obj-y := i386.o
2
3obj-$(CONFIG_PCI_BIOS) += pcbios.o
4obj-$(CONFIG_PCI_MMCONFIG) += mmconfig.o
5obj-$(CONFIG_PCI_DIRECT) += direct.o
6
7pci-y := fixup.o
8pci-$(CONFIG_ACPI_PCI) += acpi.o
9pci-y += legacy.o irq.o
10
11pci-$(CONFIG_X86_VISWS) := visws.o fixup.o
12pci-$(CONFIG_X86_NUMAQ) := numa.o irq.o
13
14obj-y += $(pci-y) common.o
diff --git a/arch/i386/pci/acpi.c b/arch/i386/pci/acpi.c
new file mode 100644
index 00000000000..2db65ec45dc
--- /dev/null
+++ b/arch/i386/pci/acpi.c
@@ -0,0 +1,53 @@
1#include <linux/pci.h>
2#include <linux/acpi.h>
3#include <linux/init.h>
4#include <linux/irq.h>
5#include <asm/hw_irq.h>
6#include "pci.h"
7
8struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_device *device, int domain, int busnum)
9{
10 if (domain != 0) {
11 printk(KERN_WARNING "PCI: Multiple domains not supported\n");
12 return NULL;
13 }
14
15 return pcibios_scan_root(busnum);
16}
17
18extern int pci_routeirq;
19static int __init pci_acpi_init(void)
20{
21 struct pci_dev *dev = NULL;
22
23 if (pcibios_scanned)
24 return 0;
25
26 if (acpi_noirq)
27 return 0;
28
29 printk(KERN_INFO "PCI: Using ACPI for IRQ routing\n");
30 acpi_irq_penalty_init();
31 pcibios_scanned++;
32 pcibios_enable_irq = acpi_pci_irq_enable;
33
34 if (pci_routeirq) {
35 /*
36 * PCI IRQ routing is set up by pci_enable_device(), but we
37 * also do it here in case there are still broken drivers that
38 * don't use pci_enable_device().
39 */
40 printk(KERN_INFO "PCI: Routing PCI interrupts for all devices because \"pci=routeirq\" specified\n");
41 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL)
42 acpi_pci_irq_enable(dev);
43 } else
44 printk(KERN_INFO "PCI: If a device doesn't work, try \"pci=routeirq\". If it helps, post a report\n");
45
46#ifdef CONFIG_X86_IO_APIC
47 if (acpi_ioapic)
48 print_IO_APIC();
49#endif
50
51 return 0;
52}
53subsys_initcall(pci_acpi_init);
diff --git a/arch/i386/pci/common.c b/arch/i386/pci/common.c
new file mode 100644
index 00000000000..720975e1af5
--- /dev/null
+++ b/arch/i386/pci/common.c
@@ -0,0 +1,251 @@
1/*
2 * Low-Level PCI Support for PC
3 *
4 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
5 */
6
7#include <linux/sched.h>
8#include <linux/pci.h>
9#include <linux/ioport.h>
10#include <linux/init.h>
11
12#include <asm/acpi.h>
13#include <asm/segment.h>
14#include <asm/io.h>
15#include <asm/smp.h>
16
17#include "pci.h"
18
19#ifdef CONFIG_PCI_BIOS
20extern void pcibios_sort(void);
21#endif
22
23unsigned int pci_probe = PCI_PROBE_BIOS | PCI_PROBE_CONF1 | PCI_PROBE_CONF2 |
24 PCI_PROBE_MMCONF;
25
26int pci_routeirq;
27int pcibios_last_bus = -1;
28struct pci_bus *pci_root_bus = NULL;
29struct pci_raw_ops *raw_pci_ops;
30
31static int pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
32{
33 return raw_pci_ops->read(0, bus->number, devfn, where, size, value);
34}
35
36static int pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
37{
38 return raw_pci_ops->write(0, bus->number, devfn, where, size, value);
39}
40
41struct pci_ops pci_root_ops = {
42 .read = pci_read,
43 .write = pci_write,
44};
45
46/*
47 * legacy, numa, and acpi all want to call pcibios_scan_root
48 * from their initcalls. This flag prevents that.
49 */
50int pcibios_scanned;
51
52/*
53 * This interrupt-safe spinlock protects all accesses to PCI
54 * configuration space.
55 */
56DEFINE_SPINLOCK(pci_config_lock);
57
58/*
59 * Several buggy motherboards address only 16 devices and mirror
60 * them to next 16 IDs. We try to detect this `feature' on all
61 * primary buses (those containing host bridges as they are
62 * expected to be unique) and remove the ghost devices.
63 */
64
65static void __devinit pcibios_fixup_ghosts(struct pci_bus *b)
66{
67 struct list_head *ln, *mn;
68 struct pci_dev *d, *e;
69 int mirror = PCI_DEVFN(16,0);
70 int seen_host_bridge = 0;
71 int i;
72
73 DBG("PCI: Scanning for ghost devices on bus %d\n", b->number);
74 list_for_each(ln, &b->devices) {
75 d = pci_dev_b(ln);
76 if ((d->class >> 8) == PCI_CLASS_BRIDGE_HOST)
77 seen_host_bridge++;
78 for (mn=ln->next; mn != &b->devices; mn=mn->next) {
79 e = pci_dev_b(mn);
80 if (e->devfn != d->devfn + mirror ||
81 e->vendor != d->vendor ||
82 e->device != d->device ||
83 e->class != d->class)
84 continue;
85 for(i=0; i<PCI_NUM_RESOURCES; i++)
86 if (e->resource[i].start != d->resource[i].start ||
87 e->resource[i].end != d->resource[i].end ||
88 e->resource[i].flags != d->resource[i].flags)
89 continue;
90 break;
91 }
92 if (mn == &b->devices)
93 return;
94 }
95 if (!seen_host_bridge)
96 return;
97 printk(KERN_WARNING "PCI: Ignoring ghost devices on bus %02x\n", b->number);
98
99 ln = &b->devices;
100 while (ln->next != &b->devices) {
101 d = pci_dev_b(ln->next);
102 if (d->devfn >= mirror) {
103 list_del(&d->global_list);
104 list_del(&d->bus_list);
105 kfree(d);
106 } else
107 ln = ln->next;
108 }
109}
110
111/*
112 * Called after each bus is probed, but before its children
113 * are examined.
114 */
115
116void __devinit pcibios_fixup_bus(struct pci_bus *b)
117{
118 pcibios_fixup_ghosts(b);
119 pci_read_bridge_bases(b);
120}
121
122
123struct pci_bus * __devinit pcibios_scan_root(int busnum)
124{
125 struct pci_bus *bus = NULL;
126
127 while ((bus = pci_find_next_bus(bus)) != NULL) {
128 if (bus->number == busnum) {
129 /* Already scanned */
130 return bus;
131 }
132 }
133
134 printk("PCI: Probing PCI hardware (bus %02x)\n", busnum);
135
136 return pci_scan_bus(busnum, &pci_root_ops, NULL);
137}
138
139extern u8 pci_cache_line_size;
140
141static int __init pcibios_init(void)
142{
143 struct cpuinfo_x86 *c = &boot_cpu_data;
144
145 if (!raw_pci_ops) {
146 printk("PCI: System does not support PCI\n");
147 return 0;
148 }
149
150 /*
151 * Assume PCI cacheline size of 32 bytes for all x86s except K7/K8
152 * and P4. It's also good for 386/486s (which actually have 16)
153 * as quite a few PCI devices do not support smaller values.
154 */
155 pci_cache_line_size = 32 >> 2;
156 if (c->x86 >= 6 && c->x86_vendor == X86_VENDOR_AMD)
157 pci_cache_line_size = 64 >> 2; /* K7 & K8 */
158 else if (c->x86 > 6 && c->x86_vendor == X86_VENDOR_INTEL)
159 pci_cache_line_size = 128 >> 2; /* P4 */
160
161 pcibios_resource_survey();
162
163#ifdef CONFIG_PCI_BIOS
164 if ((pci_probe & PCI_BIOS_SORT) && !(pci_probe & PCI_NO_SORT))
165 pcibios_sort();
166#endif
167 return 0;
168}
169
170subsys_initcall(pcibios_init);
171
172char * __devinit pcibios_setup(char *str)
173{
174 if (!strcmp(str, "off")) {
175 pci_probe = 0;
176 return NULL;
177 }
178#ifdef CONFIG_PCI_BIOS
179 else if (!strcmp(str, "bios")) {
180 pci_probe = PCI_PROBE_BIOS;
181 return NULL;
182 } else if (!strcmp(str, "nobios")) {
183 pci_probe &= ~PCI_PROBE_BIOS;
184 return NULL;
185 } else if (!strcmp(str, "nosort")) {
186 pci_probe |= PCI_NO_SORT;
187 return NULL;
188 } else if (!strcmp(str, "biosirq")) {
189 pci_probe |= PCI_BIOS_IRQ_SCAN;
190 return NULL;
191 }
192#endif
193#ifdef CONFIG_PCI_DIRECT
194 else if (!strcmp(str, "conf1")) {
195 pci_probe = PCI_PROBE_CONF1 | PCI_NO_CHECKS;
196 return NULL;
197 }
198 else if (!strcmp(str, "conf2")) {
199 pci_probe = PCI_PROBE_CONF2 | PCI_NO_CHECKS;
200 return NULL;
201 }
202#endif
203#ifdef CONFIG_PCI_MMCONFIG
204 else if (!strcmp(str, "nommconf")) {
205 pci_probe &= ~PCI_PROBE_MMCONF;
206 return NULL;
207 }
208#endif
209 else if (!strcmp(str, "noacpi")) {
210 acpi_noirq_set();
211 return NULL;
212 }
213#ifndef CONFIG_X86_VISWS
214 else if (!strcmp(str, "usepirqmask")) {
215 pci_probe |= PCI_USE_PIRQ_MASK;
216 return NULL;
217 } else if (!strncmp(str, "irqmask=", 8)) {
218 pcibios_irq_mask = simple_strtol(str+8, NULL, 0);
219 return NULL;
220 } else if (!strncmp(str, "lastbus=", 8)) {
221 pcibios_last_bus = simple_strtol(str+8, NULL, 0);
222 return NULL;
223 }
224#endif
225 else if (!strcmp(str, "rom")) {
226 pci_probe |= PCI_ASSIGN_ROMS;
227 return NULL;
228 } else if (!strcmp(str, "assign-busses")) {
229 pci_probe |= PCI_ASSIGN_ALL_BUSSES;
230 return NULL;
231 } else if (!strcmp(str, "routeirq")) {
232 pci_routeirq = 1;
233 return NULL;
234 }
235 return str;
236}
237
238unsigned int pcibios_assign_all_busses(void)
239{
240 return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0;
241}
242
243int pcibios_enable_device(struct pci_dev *dev, int mask)
244{
245 int err;
246
247 if ((err = pcibios_enable_resources(dev, mask)) < 0)
248 return err;
249
250 return pcibios_enable_irq(dev);
251}
diff --git a/arch/i386/pci/direct.c b/arch/i386/pci/direct.c
new file mode 100644
index 00000000000..30b7e9b4f6a
--- /dev/null
+++ b/arch/i386/pci/direct.c
@@ -0,0 +1,289 @@
1/*
2 * direct.c - Low-level direct PCI config space access
3 */
4
5#include <linux/pci.h>
6#include <linux/init.h>
7#include "pci.h"
8
9/*
10 * Functions for accessing PCI configuration space with type 1 accesses
11 */
12
13#define PCI_CONF1_ADDRESS(bus, devfn, reg) \
14 (0x80000000 | (bus << 16) | (devfn << 8) | (reg & ~3))
15
16static int pci_conf1_read(unsigned int seg, unsigned int bus,
17 unsigned int devfn, int reg, int len, u32 *value)
18{
19 unsigned long flags;
20
21 if (!value || (bus > 255) || (devfn > 255) || (reg > 255))
22 return -EINVAL;
23
24 spin_lock_irqsave(&pci_config_lock, flags);
25
26 outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8);
27
28 switch (len) {
29 case 1:
30 *value = inb(0xCFC + (reg & 3));
31 break;
32 case 2:
33 *value = inw(0xCFC + (reg & 2));
34 break;
35 case 4:
36 *value = inl(0xCFC);
37 break;
38 }
39
40 spin_unlock_irqrestore(&pci_config_lock, flags);
41
42 return 0;
43}
44
45static int pci_conf1_write(unsigned int seg, unsigned int bus,
46 unsigned int devfn, int reg, int len, u32 value)
47{
48 unsigned long flags;
49
50 if ((bus > 255) || (devfn > 255) || (reg > 255))
51 return -EINVAL;
52
53 spin_lock_irqsave(&pci_config_lock, flags);
54
55 outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8);
56
57 switch (len) {
58 case 1:
59 outb((u8)value, 0xCFC + (reg & 3));
60 break;
61 case 2:
62 outw((u16)value, 0xCFC + (reg & 2));
63 break;
64 case 4:
65 outl((u32)value, 0xCFC);
66 break;
67 }
68
69 spin_unlock_irqrestore(&pci_config_lock, flags);
70
71 return 0;
72}
73
74#undef PCI_CONF1_ADDRESS
75
76struct pci_raw_ops pci_direct_conf1 = {
77 .read = pci_conf1_read,
78 .write = pci_conf1_write,
79};
80
81
82/*
83 * Functions for accessing PCI configuration space with type 2 accesses
84 */
85
86#define PCI_CONF2_ADDRESS(dev, reg) (u16)(0xC000 | (dev << 8) | reg)
87
88static int pci_conf2_read(unsigned int seg, unsigned int bus,
89 unsigned int devfn, int reg, int len, u32 *value)
90{
91 unsigned long flags;
92 int dev, fn;
93
94 if (!value || (bus > 255) || (devfn > 255) || (reg > 255))
95 return -EINVAL;
96
97 dev = PCI_SLOT(devfn);
98 fn = PCI_FUNC(devfn);
99
100 if (dev & 0x10)
101 return PCIBIOS_DEVICE_NOT_FOUND;
102
103 spin_lock_irqsave(&pci_config_lock, flags);
104
105 outb((u8)(0xF0 | (fn << 1)), 0xCF8);
106 outb((u8)bus, 0xCFA);
107
108 switch (len) {
109 case 1:
110 *value = inb(PCI_CONF2_ADDRESS(dev, reg));
111 break;
112 case 2:
113 *value = inw(PCI_CONF2_ADDRESS(dev, reg));
114 break;
115 case 4:
116 *value = inl(PCI_CONF2_ADDRESS(dev, reg));
117 break;
118 }
119
120 outb(0, 0xCF8);
121
122 spin_unlock_irqrestore(&pci_config_lock, flags);
123
124 return 0;
125}
126
127static int pci_conf2_write(unsigned int seg, unsigned int bus,
128 unsigned int devfn, int reg, int len, u32 value)
129{
130 unsigned long flags;
131 int dev, fn;
132
133 if ((bus > 255) || (devfn > 255) || (reg > 255))
134 return -EINVAL;
135
136 dev = PCI_SLOT(devfn);
137 fn = PCI_FUNC(devfn);
138
139 if (dev & 0x10)
140 return PCIBIOS_DEVICE_NOT_FOUND;
141
142 spin_lock_irqsave(&pci_config_lock, flags);
143
144 outb((u8)(0xF0 | (fn << 1)), 0xCF8);
145 outb((u8)bus, 0xCFA);
146
147 switch (len) {
148 case 1:
149 outb((u8)value, PCI_CONF2_ADDRESS(dev, reg));
150 break;
151 case 2:
152 outw((u16)value, PCI_CONF2_ADDRESS(dev, reg));
153 break;
154 case 4:
155 outl((u32)value, PCI_CONF2_ADDRESS(dev, reg));
156 break;
157 }
158
159 outb(0, 0xCF8);
160
161 spin_unlock_irqrestore(&pci_config_lock, flags);
162
163 return 0;
164}
165
166#undef PCI_CONF2_ADDRESS
167
168static struct pci_raw_ops pci_direct_conf2 = {
169 .read = pci_conf2_read,
170 .write = pci_conf2_write,
171};
172
173
174/*
175 * Before we decide to use direct hardware access mechanisms, we try to do some
176 * trivial checks to ensure it at least _seems_ to be working -- we just test
177 * whether bus 00 contains a host bridge (this is similar to checking
178 * techniques used in XFree86, but ours should be more reliable since we
179 * attempt to make use of direct access hints provided by the PCI BIOS).
180 *
181 * This should be close to trivial, but it isn't, because there are buggy
182 * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
183 */
184static int __init pci_sanity_check(struct pci_raw_ops *o)
185{
186 u32 x = 0;
187 int devfn;
188
189 if (pci_probe & PCI_NO_CHECKS)
190 return 1;
191
192 for (devfn = 0; devfn < 0x100; devfn++) {
193 if (o->read(0, 0, devfn, PCI_CLASS_DEVICE, 2, &x))
194 continue;
195 if (x == PCI_CLASS_BRIDGE_HOST || x == PCI_CLASS_DISPLAY_VGA)
196 return 1;
197
198 if (o->read(0, 0, devfn, PCI_VENDOR_ID, 2, &x))
199 continue;
200 if (x == PCI_VENDOR_ID_INTEL || x == PCI_VENDOR_ID_COMPAQ)
201 return 1;
202 }
203
204 DBG("PCI: Sanity check failed\n");
205 return 0;
206}
207
208static int __init pci_check_type1(void)
209{
210 unsigned long flags;
211 unsigned int tmp;
212 int works = 0;
213
214 local_irq_save(flags);
215
216 outb(0x01, 0xCFB);
217 tmp = inl(0xCF8);
218 outl(0x80000000, 0xCF8);
219 if (inl(0xCF8) == 0x80000000 && pci_sanity_check(&pci_direct_conf1)) {
220 works = 1;
221 }
222 outl(tmp, 0xCF8);
223 local_irq_restore(flags);
224
225 return works;
226}
227
228static int __init pci_check_type2(void)
229{
230 unsigned long flags;
231 int works = 0;
232
233 local_irq_save(flags);
234
235 outb(0x00, 0xCFB);
236 outb(0x00, 0xCF8);
237 outb(0x00, 0xCFA);
238 if (inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00 &&
239 pci_sanity_check(&pci_direct_conf2)) {
240 works = 1;
241 }
242
243 local_irq_restore(flags);
244
245 return works;
246}
247
248static int __init pci_direct_init(void)
249{
250 struct resource *region, *region2;
251
252 if ((pci_probe & PCI_PROBE_CONF1) == 0)
253 goto type2;
254 region = request_region(0xCF8, 8, "PCI conf1");
255 if (!region)
256 goto type2;
257
258 if (pci_check_type1()) {
259 printk(KERN_INFO "PCI: Using configuration type 1\n");
260 raw_pci_ops = &pci_direct_conf1;
261 return 0;
262 }
263 release_resource(region);
264
265 type2:
266 if ((pci_probe & PCI_PROBE_CONF2) == 0)
267 goto out;
268 region = request_region(0xCF8, 4, "PCI conf2");
269 if (!region)
270 goto out;
271 region2 = request_region(0xC000, 0x1000, "PCI conf2");
272 if (!region2)
273 goto fail2;
274
275 if (pci_check_type2()) {
276 printk(KERN_INFO "PCI: Using configuration type 2\n");
277 raw_pci_ops = &pci_direct_conf2;
278 return 0;
279 }
280
281 release_resource(region2);
282 fail2:
283 release_resource(region);
284
285 out:
286 return 0;
287}
288
289arch_initcall(pci_direct_init);
diff --git a/arch/i386/pci/fixup.c b/arch/i386/pci/fixup.c
new file mode 100644
index 00000000000..be52c5ac4e0
--- /dev/null
+++ b/arch/i386/pci/fixup.c
@@ -0,0 +1,386 @@
1/*
2 * Exceptions for specific devices. Usually work-arounds for fatal design flaws.
3 */
4
5#include <linux/pci.h>
6#include <linux/init.h>
7#include "pci.h"
8
9
10static void __devinit pci_fixup_i450nx(struct pci_dev *d)
11{
12 /*
13 * i450NX -- Find and scan all secondary buses on all PXB's.
14 */
15 int pxb, reg;
16 u8 busno, suba, subb;
17
18 printk(KERN_WARNING "PCI: Searching for i450NX host bridges on %s\n", pci_name(d));
19 reg = 0xd0;
20 for(pxb=0; pxb<2; pxb++) {
21 pci_read_config_byte(d, reg++, &busno);
22 pci_read_config_byte(d, reg++, &suba);
23 pci_read_config_byte(d, reg++, &subb);
24 DBG("i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno, suba, subb);
25 if (busno)
26 pci_scan_bus(busno, &pci_root_ops, NULL); /* Bus A */
27 if (suba < subb)
28 pci_scan_bus(suba+1, &pci_root_ops, NULL); /* Bus B */
29 }
30 pcibios_last_bus = -1;
31}
32DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx);
33
34static void __devinit pci_fixup_i450gx(struct pci_dev *d)
35{
36 /*
37 * i450GX and i450KX -- Find and scan all secondary buses.
38 * (called separately for each PCI bridge found)
39 */
40 u8 busno;
41 pci_read_config_byte(d, 0x4a, &busno);
42 printk(KERN_INFO "PCI: i440KX/GX host bridge %s: secondary bus %02x\n", pci_name(d), busno);
43 pci_scan_bus(busno, &pci_root_ops, NULL);
44 pcibios_last_bus = -1;
45}
46DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454GX, pci_fixup_i450gx);
47
48static void __devinit pci_fixup_umc_ide(struct pci_dev *d)
49{
50 /*
51 * UM8886BF IDE controller sets region type bits incorrectly,
52 * therefore they look like memory despite of them being I/O.
53 */
54 int i;
55
56 printk(KERN_WARNING "PCI: Fixing base address flags for device %s\n", pci_name(d));
57 for(i=0; i<4; i++)
58 d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO;
59}
60DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, pci_fixup_umc_ide);
61
62static void __devinit pci_fixup_ncr53c810(struct pci_dev *d)
63{
64 /*
65 * NCR 53C810 returns class code 0 (at least on some systems).
66 * Fix class to be PCI_CLASS_STORAGE_SCSI
67 */
68 if (!d->class) {
69 printk(KERN_WARNING "PCI: fixing NCR 53C810 class code for %s\n", pci_name(d));
70 d->class = PCI_CLASS_STORAGE_SCSI << 8;
71 }
72}
73DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, pci_fixup_ncr53c810);
74
75static void __devinit pci_fixup_ide_bases(struct pci_dev *d)
76{
77 int i;
78
79 /*
80 * PCI IDE controllers use non-standard I/O port decoding, respect it.
81 */
82 if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
83 return;
84 DBG("PCI: IDE base address fixup for %s\n", pci_name(d));
85 for(i=0; i<4; i++) {
86 struct resource *r = &d->resource[i];
87 if ((r->start & ~0x80) == 0x374) {
88 r->start |= 2;
89 r->end = r->start;
90 }
91 }
92}
93DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
94
95static void __devinit pci_fixup_ide_trash(struct pci_dev *d)
96{
97 int i;
98
99 /*
100 * Runs the fixup only for the first IDE controller
101 * (Shai Fultheim - shai@ftcon.com)
102 */
103 static int called = 0;
104 if (called)
105 return;
106 called = 1;
107
108 /*
109 * There exist PCI IDE controllers which have utter garbage
110 * in first four base registers. Ignore that.
111 */
112 DBG("PCI: IDE base address trash cleared for %s\n", pci_name(d));
113 for(i=0; i<4; i++)
114 d->resource[i].start = d->resource[i].end = d->resource[i].flags = 0;
115}
116DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513, pci_fixup_ide_trash);
117DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, pci_fixup_ide_trash);
118DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_11, pci_fixup_ide_trash);
119DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_9, pci_fixup_ide_trash);
120
121static void __devinit pci_fixup_latency(struct pci_dev *d)
122{
123 /*
124 * SiS 5597 and 5598 chipsets require latency timer set to
125 * at most 32 to avoid lockups.
126 */
127 DBG("PCI: Setting max latency to 32\n");
128 pcibios_max_latency = 32;
129}
130DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency);
131DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5598, pci_fixup_latency);
132
133static void __devinit pci_fixup_piix4_acpi(struct pci_dev *d)
134{
135 /*
136 * PIIX4 ACPI device: hardwired IRQ9
137 */
138 d->irq = 9;
139}
140DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, pci_fixup_piix4_acpi);
141
142/*
143 * Addresses issues with problems in the memory write queue timer in
144 * certain VIA Northbridges. This bugfix is per VIA's specifications,
145 * except for the KL133/KM133: clearing bit 5 on those Northbridges seems
146 * to trigger a bug in its integrated ProSavage video card, which
147 * causes screen corruption. We only clear bits 6 and 7 for that chipset,
148 * until VIA can provide us with definitive information on why screen
149 * corruption occurs, and what exactly those bits do.
150 *
151 * VIA 8363,8622,8361 Northbridges:
152 * - bits 5, 6, 7 at offset 0x55 need to be turned off
153 * VIA 8367 (KT266x) Northbridges:
154 * - bits 5, 6, 7 at offset 0x95 need to be turned off
155 * VIA 8363 rev 0x81/0x84 (KL133/KM133) Northbridges:
156 * - bits 6, 7 at offset 0x55 need to be turned off
157 */
158
159#define VIA_8363_KL133_REVISION_ID 0x81
160#define VIA_8363_KM133_REVISION_ID 0x84
161
162static void __devinit pci_fixup_via_northbridge_bug(struct pci_dev *d)
163{
164 u8 v;
165 u8 revision;
166 int where = 0x55;
167 int mask = 0x1f; /* clear bits 5, 6, 7 by default */
168
169 pci_read_config_byte(d, PCI_REVISION_ID, &revision);
170
171 if (d->device == PCI_DEVICE_ID_VIA_8367_0) {
172 /* fix pci bus latency issues resulted by NB bios error
173 it appears on bug free^Wreduced kt266x's bios forces
174 NB latency to zero */
175 pci_write_config_byte(d, PCI_LATENCY_TIMER, 0);
176
177 where = 0x95; /* the memory write queue timer register is
178 different for the KT266x's: 0x95 not 0x55 */
179 } else if (d->device == PCI_DEVICE_ID_VIA_8363_0 &&
180 (revision == VIA_8363_KL133_REVISION_ID ||
181 revision == VIA_8363_KM133_REVISION_ID)) {
182 mask = 0x3f; /* clear only bits 6 and 7; clearing bit 5
183 causes screen corruption on the KL133/KM133 */
184 }
185
186 pci_read_config_byte(d, where, &v);
187 if (v & ~mask) {
188 printk(KERN_WARNING "Disabling VIA memory write queue (PCI ID %04x, rev %02x): [%02x] %02x & %02x -> %02x\n", \
189 d->device, revision, where, v, mask, v & mask);
190 v &= mask;
191 pci_write_config_byte(d, where, v);
192 }
193}
194DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug);
195DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug);
196DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug);
197DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug);
198
199/*
200 * For some reasons Intel decided that certain parts of their
201 * 815, 845 and some other chipsets must look like PCI-to-PCI bridges
202 * while they are obviously not. The 82801 family (AA, AB, BAM/CAM,
203 * BA/CA/DB and E) PCI bridges are actually HUB-to-PCI ones, according
204 * to Intel terminology. These devices do forward all addresses from
205 * system to PCI bus no matter what are their window settings, so they are
206 * "transparent" (or subtractive decoding) from programmers point of view.
207 */
208static void __devinit pci_fixup_transparent_bridge(struct pci_dev *dev)
209{
210 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
211 (dev->device & 0xff00) == 0x2400)
212 dev->transparent = 1;
213}
214DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_fixup_transparent_bridge);
215
216/*
217 * Fixup for C1 Halt Disconnect problem on nForce2 systems.
218 *
219 * From information provided by "Allen Martin" <AMartin@nvidia.com>:
220 *
221 * A hang is caused when the CPU generates a very fast CONNECT/HALT cycle
222 * sequence. Workaround is to set the SYSTEM_IDLE_TIMEOUT to 80 ns.
223 * This allows the state-machine and timer to return to a proper state within
224 * 80 ns of the CONNECT and probe appearing together. Since the CPU will not
225 * issue another HALT within 80 ns of the initial HALT, the failure condition
226 * is avoided.
227 */
228static void __init pci_fixup_nforce2(struct pci_dev *dev)
229{
230 u32 val;
231
232 /*
233 * Chip Old value New value
234 * C17 0x1F0FFF01 0x1F01FF01
235 * C18D 0x9F0FFF01 0x9F01FF01
236 *
237 * Northbridge chip version may be determined by
238 * reading the PCI revision ID (0xC1 or greater is C18D).
239 */
240 pci_read_config_dword(dev, 0x6c, &val);
241
242 /*
243 * Apply fixup if needed, but don't touch disconnect state
244 */
245 if ((val & 0x00FF0000) != 0x00010000) {
246 printk(KERN_WARNING "PCI: nForce2 C1 Halt Disconnect fixup\n");
247 pci_write_config_dword(dev, 0x6c, (val & 0xFF00FFFF) | 0x00010000);
248 }
249}
250DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2);
251
252/* Max PCI Express root ports */
253#define MAX_PCIEROOT 6
254static int quirk_aspm_offset[MAX_PCIEROOT << 3];
255
256#define GET_INDEX(a, b) (((a - PCI_DEVICE_ID_INTEL_MCH_PA) << 3) + b)
257
258static int quirk_pcie_aspm_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
259{
260 return raw_pci_ops->read(0, bus->number, devfn, where, size, value);
261}
262
263/*
264 * Replace the original pci bus ops for write with a new one that will filter
265 * the request to insure ASPM cannot be enabled.
266 */
267static int quirk_pcie_aspm_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
268{
269 u8 offset;
270
271 offset = quirk_aspm_offset[GET_INDEX(bus->self->device, devfn)];
272
273 if ((offset) && (where == offset))
274 value = value & 0xfffffffc;
275
276 return raw_pci_ops->write(0, bus->number, devfn, where, size, value);
277}
278
279static struct pci_ops quirk_pcie_aspm_ops = {
280 .read = quirk_pcie_aspm_read,
281 .write = quirk_pcie_aspm_write,
282};
283
284/*
285 * Prevents PCI Express ASPM (Active State Power Management) being enabled.
286 *
287 * Save the register offset, where the ASPM control bits are located,
288 * for each PCI Express device that is in the device list of
289 * the root port in an array for fast indexing. Replace the bus ops
290 * with the modified one.
291 */
292static void pcie_rootport_aspm_quirk(struct pci_dev *pdev)
293{
294 int cap_base, i;
295 struct pci_bus *pbus;
296 struct pci_dev *dev;
297
298 if ((pbus = pdev->subordinate) == NULL)
299 return;
300
301 /*
302 * Check if the DID of pdev matches one of the six root ports. This
303 * check is needed in the case this function is called directly by the
304 * hot-plug driver.
305 */
306 if ((pdev->device < PCI_DEVICE_ID_INTEL_MCH_PA) ||
307 (pdev->device > PCI_DEVICE_ID_INTEL_MCH_PC1))
308 return;
309
310 if (list_empty(&pbus->devices)) {
311 /*
312 * If no device is attached to the root port at power-up or
313 * after hot-remove, the pbus->devices is empty and this code
314 * will set the offsets to zero and the bus ops to parent's bus
315 * ops, which is unmodified.
316 */
317 for (i= GET_INDEX(pdev->device, 0); i <= GET_INDEX(pdev->device, 7); ++i)
318 quirk_aspm_offset[i] = 0;
319
320 pbus->ops = pbus->parent->ops;
321 } else {
322 /*
323 * If devices are attached to the root port at power-up or
324 * after hot-add, the code loops through the device list of
325 * each root port to save the register offsets and replace the
326 * bus ops.
327 */
328 list_for_each_entry(dev, &pbus->devices, bus_list) {
329 /* There are 0 to 8 devices attached to this bus */
330 cap_base = pci_find_capability(dev, PCI_CAP_ID_EXP);
331 quirk_aspm_offset[GET_INDEX(pdev->device, dev->devfn)]= cap_base + 0x10;
332 }
333 pbus->ops = &quirk_pcie_aspm_ops;
334 }
335}
336DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PA, pcie_rootport_aspm_quirk );
337DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PA1, pcie_rootport_aspm_quirk );
338DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PB, pcie_rootport_aspm_quirk );
339DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PB1, pcie_rootport_aspm_quirk );
340DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PC, pcie_rootport_aspm_quirk );
341DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PC1, pcie_rootport_aspm_quirk );
342
343/*
344 * Fixup to mark boot BIOS video selected by BIOS before it changes
345 *
346 * From information provided by "Jon Smirl" <jonsmirl@gmail.com>
347 *
348 * The standard boot ROM sequence for an x86 machine uses the BIOS
349 * to select an initial video card for boot display. This boot video
350 * card will have it's BIOS copied to C0000 in system RAM.
351 * IORESOURCE_ROM_SHADOW is used to associate the boot video
352 * card with this copy. On laptops this copy has to be used since
353 * the main ROM may be compressed or combined with another image.
354 * See pci_map_rom() for use of this flag. IORESOURCE_ROM_SHADOW
355 * is marked here since the boot video device will be the only enabled
356 * video device at this point.
357 */
358
359static void __devinit pci_fixup_video(struct pci_dev *pdev)
360{
361 struct pci_dev *bridge;
362 struct pci_bus *bus;
363 u16 config;
364
365 if ((pdev->class >> 8) != PCI_CLASS_DISPLAY_VGA)
366 return;
367
368 /* Is VGA routed to us? */
369 bus = pdev->bus;
370 while (bus) {
371 bridge = bus->self;
372 if (bridge) {
373 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
374 &config);
375 if (!(config & PCI_BRIDGE_CTL_VGA))
376 return;
377 }
378 bus = bus->parent;
379 }
380 pci_read_config_word(pdev, PCI_COMMAND, &config);
381 if (config & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
382 pdev->resource[PCI_ROM_RESOURCE].flags |= IORESOURCE_ROM_SHADOW;
383 printk(KERN_DEBUG "Boot video device is %s\n", pci_name(pdev));
384 }
385}
386DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_video);
diff --git a/arch/i386/pci/i386.c b/arch/i386/pci/i386.c
new file mode 100644
index 00000000000..c205ea7e233
--- /dev/null
+++ b/arch/i386/pci/i386.c
@@ -0,0 +1,304 @@
1/*
2 * Low-Level PCI Access for i386 machines
3 *
4 * Copyright 1993, 1994 Drew Eckhardt
5 * Visionary Computing
6 * (Unix and Linux consulting and custom programming)
7 * Drew@Colorado.EDU
8 * +1 (303) 786-7975
9 *
10 * Drew's work was sponsored by:
11 * iX Multiuser Multitasking Magazine
12 * Hannover, Germany
13 * hm@ix.de
14 *
15 * Copyright 1997--2000 Martin Mares <mj@ucw.cz>
16 *
17 * For more information, please consult the following manuals (look at
18 * http://www.pcisig.com/ for how to get them):
19 *
20 * PCI BIOS Specification
21 * PCI Local Bus Specification
22 * PCI to PCI Bridge Specification
23 * PCI System Design Guide
24 *
25 */
26
27#include <linux/types.h>
28#include <linux/kernel.h>
29#include <linux/pci.h>
30#include <linux/init.h>
31#include <linux/ioport.h>
32#include <linux/errno.h>
33
34#include "pci.h"
35
36/*
37 * We need to avoid collisions with `mirrored' VGA ports
38 * and other strange ISA hardware, so we always want the
39 * addresses to be allocated in the 0x000-0x0ff region
40 * modulo 0x400.
41 *
42 * Why? Because some silly external IO cards only decode
43 * the low 10 bits of the IO address. The 0x00-0xff region
44 * is reserved for motherboard devices that decode all 16
45 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
46 * but we want to try to avoid allocating at 0x2900-0x2bff
47 * which might have be mirrored at 0x0100-0x03ff..
48 */
49void
50pcibios_align_resource(void *data, struct resource *res,
51 unsigned long size, unsigned long align)
52{
53 if (res->flags & IORESOURCE_IO) {
54 unsigned long start = res->start;
55
56 if (start & 0x300) {
57 start = (start + 0x3ff) & ~0x3ff;
58 res->start = start;
59 }
60 }
61}
62
63
64/*
65 * Handle resources of PCI devices. If the world were perfect, we could
66 * just allocate all the resource regions and do nothing more. It isn't.
67 * On the other hand, we cannot just re-allocate all devices, as it would
68 * require us to know lots of host bridge internals. So we attempt to
69 * keep as much of the original configuration as possible, but tweak it
70 * when it's found to be wrong.
71 *
72 * Known BIOS problems we have to work around:
73 * - I/O or memory regions not configured
74 * - regions configured, but not enabled in the command register
75 * - bogus I/O addresses above 64K used
76 * - expansion ROMs left enabled (this may sound harmless, but given
77 * the fact the PCI specs explicitly allow address decoders to be
78 * shared between expansion ROMs and other resource regions, it's
79 * at least dangerous)
80 *
81 * Our solution:
82 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
83 * This gives us fixed barriers on where we can allocate.
84 * (2) Allocate resources for all enabled devices. If there is
85 * a collision, just mark the resource as unallocated. Also
86 * disable expansion ROMs during this step.
87 * (3) Try to allocate resources for disabled devices. If the
88 * resources were assigned correctly, everything goes well,
89 * if they weren't, they won't disturb allocation of other
90 * resources.
91 * (4) Assign new addresses to resources which were either
92 * not configured at all or misconfigured. If explicitly
93 * requested by the user, configure expansion ROM address
94 * as well.
95 */
96
97static void __init pcibios_allocate_bus_resources(struct list_head *bus_list)
98{
99 struct pci_bus *bus;
100 struct pci_dev *dev;
101 int idx;
102 struct resource *r, *pr;
103
104 /* Depth-First Search on bus tree */
105 list_for_each_entry(bus, bus_list, node) {
106 if ((dev = bus->self)) {
107 for (idx = PCI_BRIDGE_RESOURCES; idx < PCI_NUM_RESOURCES; idx++) {
108 r = &dev->resource[idx];
109 if (!r->start)
110 continue;
111 pr = pci_find_parent_resource(dev, r);
112 if (!pr || request_resource(pr, r) < 0)
113 printk(KERN_ERR "PCI: Cannot allocate resource region %d of bridge %s\n", idx, pci_name(dev));
114 }
115 }
116 pcibios_allocate_bus_resources(&bus->children);
117 }
118}
119
120static void __init pcibios_allocate_resources(int pass)
121{
122 struct pci_dev *dev = NULL;
123 int idx, disabled;
124 u16 command;
125 struct resource *r, *pr;
126
127 for_each_pci_dev(dev) {
128 pci_read_config_word(dev, PCI_COMMAND, &command);
129 for(idx = 0; idx < 6; idx++) {
130 r = &dev->resource[idx];
131 if (r->parent) /* Already allocated */
132 continue;
133 if (!r->start) /* Address not assigned at all */
134 continue;
135 if (r->flags & IORESOURCE_IO)
136 disabled = !(command & PCI_COMMAND_IO);
137 else
138 disabled = !(command & PCI_COMMAND_MEMORY);
139 if (pass == disabled) {
140 DBG("PCI: Resource %08lx-%08lx (f=%lx, d=%d, p=%d)\n",
141 r->start, r->end, r->flags, disabled, pass);
142 pr = pci_find_parent_resource(dev, r);
143 if (!pr || request_resource(pr, r) < 0) {
144 printk(KERN_ERR "PCI: Cannot allocate resource region %d of device %s\n", idx, pci_name(dev));
145 /* We'll assign a new address later */
146 r->end -= r->start;
147 r->start = 0;
148 }
149 }
150 }
151 if (!pass) {
152 r = &dev->resource[PCI_ROM_RESOURCE];
153 if (r->flags & IORESOURCE_ROM_ENABLE) {
154 /* Turn the ROM off, leave the resource region, but keep it unregistered. */
155 u32 reg;
156 DBG("PCI: Switching off ROM of %s\n", pci_name(dev));
157 r->flags &= ~IORESOURCE_ROM_ENABLE;
158 pci_read_config_dword(dev, dev->rom_base_reg, &reg);
159 pci_write_config_dword(dev, dev->rom_base_reg, reg & ~PCI_ROM_ADDRESS_ENABLE);
160 }
161 }
162 }
163}
164
165static int __init pcibios_assign_resources(void)
166{
167 struct pci_dev *dev = NULL;
168 int idx;
169 struct resource *r;
170
171 for_each_pci_dev(dev) {
172 int class = dev->class >> 8;
173
174 /* Don't touch classless devices and host bridges */
175 if (!class || class == PCI_CLASS_BRIDGE_HOST)
176 continue;
177
178 for(idx=0; idx<6; idx++) {
179 r = &dev->resource[idx];
180
181 /*
182 * Don't touch IDE controllers and I/O ports of video cards!
183 */
184 if ((class == PCI_CLASS_STORAGE_IDE && idx < 4) ||
185 (class == PCI_CLASS_DISPLAY_VGA && (r->flags & IORESOURCE_IO)))
186 continue;
187
188 /*
189 * We shall assign a new address to this resource, either because
190 * the BIOS forgot to do so or because we have decided the old
191 * address was unusable for some reason.
192 */
193 if (!r->start && r->end)
194 pci_assign_resource(dev, idx);
195 }
196
197 if (pci_probe & PCI_ASSIGN_ROMS) {
198 r = &dev->resource[PCI_ROM_RESOURCE];
199 r->end -= r->start;
200 r->start = 0;
201 if (r->end)
202 pci_assign_resource(dev, PCI_ROM_RESOURCE);
203 }
204 }
205 return 0;
206}
207
208void __init pcibios_resource_survey(void)
209{
210 DBG("PCI: Allocating resources\n");
211 pcibios_allocate_bus_resources(&pci_root_buses);
212 pcibios_allocate_resources(0);
213 pcibios_allocate_resources(1);
214}
215
216/**
217 * called in fs_initcall (one below subsys_initcall),
218 * give a chance for motherboard reserve resources
219 */
220fs_initcall(pcibios_assign_resources);
221
222int pcibios_enable_resources(struct pci_dev *dev, int mask)
223{
224 u16 cmd, old_cmd;
225 int idx;
226 struct resource *r;
227
228 pci_read_config_word(dev, PCI_COMMAND, &cmd);
229 old_cmd = cmd;
230 for(idx=0; idx<6; idx++) {
231 /* Only set up the requested stuff */
232 if (!(mask & (1<<idx)))
233 continue;
234
235 r = &dev->resource[idx];
236 if (!r->start && r->end) {
237 printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
238 return -EINVAL;
239 }
240 if (r->flags & IORESOURCE_IO)
241 cmd |= PCI_COMMAND_IO;
242 if (r->flags & IORESOURCE_MEM)
243 cmd |= PCI_COMMAND_MEMORY;
244 }
245 if (dev->resource[PCI_ROM_RESOURCE].start)
246 cmd |= PCI_COMMAND_MEMORY;
247 if (cmd != old_cmd) {
248 printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
249 pci_write_config_word(dev, PCI_COMMAND, cmd);
250 }
251 return 0;
252}
253
254/*
255 * If we set up a device for bus mastering, we need to check the latency
256 * timer as certain crappy BIOSes forget to set it properly.
257 */
258unsigned int pcibios_max_latency = 255;
259
260void pcibios_set_master(struct pci_dev *dev)
261{
262 u8 lat;
263 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
264 if (lat < 16)
265 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
266 else if (lat > pcibios_max_latency)
267 lat = pcibios_max_latency;
268 else
269 return;
270 printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", pci_name(dev), lat);
271 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
272}
273
274int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
275 enum pci_mmap_state mmap_state, int write_combine)
276{
277 unsigned long prot;
278
279 /* I/O space cannot be accessed via normal processor loads and
280 * stores on this platform.
281 */
282 if (mmap_state == pci_mmap_io)
283 return -EINVAL;
284
285 /* Leave vm_pgoff as-is, the PCI space address is the physical
286 * address on this platform.
287 */
288 vma->vm_flags |= (VM_SHM | VM_LOCKED | VM_IO);
289
290 prot = pgprot_val(vma->vm_page_prot);
291 if (boot_cpu_data.x86 > 3)
292 prot |= _PAGE_PCD | _PAGE_PWT;
293 vma->vm_page_prot = __pgprot(prot);
294
295 /* Write-combine setting is ignored, it is changed via the mtrr
296 * interfaces on this platform.
297 */
298 if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
299 vma->vm_end - vma->vm_start,
300 vma->vm_page_prot))
301 return -EAGAIN;
302
303 return 0;
304}
diff --git a/arch/i386/pci/irq.c b/arch/i386/pci/irq.c
new file mode 100644
index 00000000000..1128451b5d7
--- /dev/null
+++ b/arch/i386/pci/irq.c
@@ -0,0 +1,1119 @@
1/*
2 * Low-Level PCI Support for PC -- Routing of Interrupts
3 *
4 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
5 */
6
7#include <linux/config.h>
8#include <linux/types.h>
9#include <linux/kernel.h>
10#include <linux/pci.h>
11#include <linux/init.h>
12#include <linux/slab.h>
13#include <linux/interrupt.h>
14#include <linux/irq.h>
15#include <linux/dmi.h>
16#include <asm/io.h>
17#include <asm/smp.h>
18#include <asm/io_apic.h>
19#include <asm/hw_irq.h>
20#include <linux/acpi.h>
21
22#include "pci.h"
23
24#define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
25#define PIRQ_VERSION 0x0100
26
27static int broken_hp_bios_irq9;
28static int acer_tm360_irqrouting;
29
30static struct irq_routing_table *pirq_table;
31
32static int pirq_enable_irq(struct pci_dev *dev);
33
34/*
35 * Never use: 0, 1, 2 (timer, keyboard, and cascade)
36 * Avoid using: 13, 14 and 15 (FP error and IDE).
37 * Penalize: 3, 4, 6, 7, 12 (known ISA uses: serial, floppy, parallel and mouse)
38 */
39unsigned int pcibios_irq_mask = 0xfff8;
40
41static int pirq_penalty[16] = {
42 1000000, 1000000, 1000000, 1000, 1000, 0, 1000, 1000,
43 0, 0, 0, 0, 1000, 100000, 100000, 100000
44};
45
46struct irq_router {
47 char *name;
48 u16 vendor, device;
49 int (*get)(struct pci_dev *router, struct pci_dev *dev, int pirq);
50 int (*set)(struct pci_dev *router, struct pci_dev *dev, int pirq, int new);
51};
52
53struct irq_router_handler {
54 u16 vendor;
55 int (*probe)(struct irq_router *r, struct pci_dev *router, u16 device);
56};
57
58int (*pcibios_enable_irq)(struct pci_dev *dev) = NULL;
59
60/*
61 * Search 0xf0000 -- 0xfffff for the PCI IRQ Routing Table.
62 */
63
64static struct irq_routing_table * __init pirq_find_routing_table(void)
65{
66 u8 *addr;
67 struct irq_routing_table *rt;
68 int i;
69 u8 sum;
70
71 for(addr = (u8 *) __va(0xf0000); addr < (u8 *) __va(0x100000); addr += 16) {
72 rt = (struct irq_routing_table *) addr;
73 if (rt->signature != PIRQ_SIGNATURE ||
74 rt->version != PIRQ_VERSION ||
75 rt->size % 16 ||
76 rt->size < sizeof(struct irq_routing_table))
77 continue;
78 sum = 0;
79 for(i=0; i<rt->size; i++)
80 sum += addr[i];
81 if (!sum) {
82 DBG("PCI: Interrupt Routing Table found at 0x%p\n", rt);
83 return rt;
84 }
85 }
86 return NULL;
87}
88
89/*
90 * If we have a IRQ routing table, use it to search for peer host
91 * bridges. It's a gross hack, but since there are no other known
92 * ways how to get a list of buses, we have to go this way.
93 */
94
95static void __init pirq_peer_trick(void)
96{
97 struct irq_routing_table *rt = pirq_table;
98 u8 busmap[256];
99 int i;
100 struct irq_info *e;
101
102 memset(busmap, 0, sizeof(busmap));
103 for(i=0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) {
104 e = &rt->slots[i];
105#ifdef DEBUG
106 {
107 int j;
108 DBG("%02x:%02x slot=%02x", e->bus, e->devfn/8, e->slot);
109 for(j=0; j<4; j++)
110 DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap);
111 DBG("\n");
112 }
113#endif
114 busmap[e->bus] = 1;
115 }
116 for(i = 1; i < 256; i++) {
117 if (!busmap[i] || pci_find_bus(0, i))
118 continue;
119 if (pci_scan_bus(i, &pci_root_ops, NULL))
120 printk(KERN_INFO "PCI: Discovered primary peer bus %02x [IRQ]\n", i);
121 }
122 pcibios_last_bus = -1;
123}
124
125/*
126 * Code for querying and setting of IRQ routes on various interrupt routers.
127 */
128
129void eisa_set_level_irq(unsigned int irq)
130{
131 unsigned char mask = 1 << (irq & 7);
132 unsigned int port = 0x4d0 + (irq >> 3);
133 unsigned char val;
134 static u16 eisa_irq_mask;
135
136 if (irq >= 16 || (1 << irq) & eisa_irq_mask)
137 return;
138
139 eisa_irq_mask |= (1 << irq);
140 printk("PCI: setting IRQ %u as level-triggered\n", irq);
141 val = inb(port);
142 if (!(val & mask)) {
143 DBG(" -> edge");
144 outb(val | mask, port);
145 }
146}
147
148/*
149 * Common IRQ routing practice: nybbles in config space,
150 * offset by some magic constant.
151 */
152static unsigned int read_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr)
153{
154 u8 x;
155 unsigned reg = offset + (nr >> 1);
156
157 pci_read_config_byte(router, reg, &x);
158 return (nr & 1) ? (x >> 4) : (x & 0xf);
159}
160
161static void write_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr, unsigned int val)
162{
163 u8 x;
164 unsigned reg = offset + (nr >> 1);
165
166 pci_read_config_byte(router, reg, &x);
167 x = (nr & 1) ? ((x & 0x0f) | (val << 4)) : ((x & 0xf0) | val);
168 pci_write_config_byte(router, reg, x);
169}
170
171/*
172 * ALI pirq entries are damn ugly, and completely undocumented.
173 * This has been figured out from pirq tables, and it's not a pretty
174 * picture.
175 */
176static int pirq_ali_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
177{
178 static unsigned char irqmap[16] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 };
179
180 return irqmap[read_config_nybble(router, 0x48, pirq-1)];
181}
182
183static int pirq_ali_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
184{
185 static unsigned char irqmap[16] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 };
186 unsigned int val = irqmap[irq];
187
188 if (val) {
189 write_config_nybble(router, 0x48, pirq-1, val);
190 return 1;
191 }
192 return 0;
193}
194
195/*
196 * The Intel PIIX4 pirq rules are fairly simple: "pirq" is
197 * just a pointer to the config space.
198 */
199static int pirq_piix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
200{
201 u8 x;
202
203 pci_read_config_byte(router, pirq, &x);
204 return (x < 16) ? x : 0;
205}
206
207static int pirq_piix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
208{
209 pci_write_config_byte(router, pirq, irq);
210 return 1;
211}
212
213/*
214 * The VIA pirq rules are nibble-based, like ALI,
215 * but without the ugly irq number munging.
216 * However, PIRQD is in the upper instead of lower 4 bits.
217 */
218static int pirq_via_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
219{
220 return read_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq);
221}
222
223static int pirq_via_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
224{
225 write_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq, irq);
226 return 1;
227}
228
229/*
230 * ITE 8330G pirq rules are nibble-based
231 * FIXME: pirqmap may be { 1, 0, 3, 2 },
232 * 2+3 are both mapped to irq 9 on my system
233 */
234static int pirq_ite_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
235{
236 static unsigned char pirqmap[4] = { 1, 0, 2, 3 };
237 return read_config_nybble(router,0x43, pirqmap[pirq-1]);
238}
239
240static int pirq_ite_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
241{
242 static unsigned char pirqmap[4] = { 1, 0, 2, 3 };
243 write_config_nybble(router, 0x43, pirqmap[pirq-1], irq);
244 return 1;
245}
246
247/*
248 * OPTI: high four bits are nibble pointer..
249 * I wonder what the low bits do?
250 */
251static int pirq_opti_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
252{
253 return read_config_nybble(router, 0xb8, pirq >> 4);
254}
255
256static int pirq_opti_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
257{
258 write_config_nybble(router, 0xb8, pirq >> 4, irq);
259 return 1;
260}
261
262/*
263 * Cyrix: nibble offset 0x5C
264 * 0x5C bits 7:4 is INTB bits 3:0 is INTA
265 * 0x5D bits 7:4 is INTD bits 3:0 is INTC
266 */
267static int pirq_cyrix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
268{
269 return read_config_nybble(router, 0x5C, (pirq-1)^1);
270}
271
272static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
273{
274 write_config_nybble(router, 0x5C, (pirq-1)^1, irq);
275 return 1;
276}
277
278/*
279 * PIRQ routing for SiS 85C503 router used in several SiS chipsets.
280 * We have to deal with the following issues here:
281 * - vendors have different ideas about the meaning of link values
282 * - some onboard devices (integrated in the chipset) have special
283 * links and are thus routed differently (i.e. not via PCI INTA-INTD)
284 * - different revision of the router have a different layout for
285 * the routing registers, particularly for the onchip devices
286 *
287 * For all routing registers the common thing is we have one byte
288 * per routeable link which is defined as:
289 * bit 7 IRQ mapping enabled (0) or disabled (1)
290 * bits [6:4] reserved (sometimes used for onchip devices)
291 * bits [3:0] IRQ to map to
292 * allowed: 3-7, 9-12, 14-15
293 * reserved: 0, 1, 2, 8, 13
294 *
295 * The config-space registers located at 0x41/0x42/0x43/0x44 are
296 * always used to route the normal PCI INT A/B/C/D respectively.
297 * Apparently there are systems implementing PCI routing table using
298 * link values 0x01-0x04 and others using 0x41-0x44 for PCI INTA..D.
299 * We try our best to handle both link mappings.
300 *
301 * Currently (2003-05-21) it appears most SiS chipsets follow the
302 * definition of routing registers from the SiS-5595 southbridge.
303 * According to the SiS 5595 datasheets the revision id's of the
304 * router (ISA-bridge) should be 0x01 or 0xb0.
305 *
306 * Furthermore we've also seen lspci dumps with revision 0x00 and 0xb1.
307 * Looks like these are used in a number of SiS 5xx/6xx/7xx chipsets.
308 * They seem to work with the current routing code. However there is
309 * some concern because of the two USB-OHCI HCs (original SiS 5595
310 * had only one). YMMV.
311 *
312 * Onchip routing for router rev-id 0x01/0xb0 and probably 0x00/0xb1:
313 *
314 * 0x61: IDEIRQ:
315 * bits [6:5] must be written 01
316 * bit 4 channel-select primary (0), secondary (1)
317 *
318 * 0x62: USBIRQ:
319 * bit 6 OHCI function disabled (0), enabled (1)
320 *
321 * 0x6a: ACPI/SCI IRQ: bits 4-6 reserved
322 *
323 * 0x7e: Data Acq. Module IRQ - bits 4-6 reserved
324 *
325 * We support USBIRQ (in addition to INTA-INTD) and keep the
326 * IDE, ACPI and DAQ routing untouched as set by the BIOS.
327 *
328 * Currently the only reported exception is the new SiS 65x chipset
329 * which includes the SiS 69x southbridge. Here we have the 85C503
330 * router revision 0x04 and there are changes in the register layout
331 * mostly related to the different USB HCs with USB 2.0 support.
332 *
333 * Onchip routing for router rev-id 0x04 (try-and-error observation)
334 *
335 * 0x60/0x61/0x62/0x63: 1xEHCI and 3xOHCI (companion) USB-HCs
336 * bit 6-4 are probably unused, not like 5595
337 */
338
339#define PIRQ_SIS_IRQ_MASK 0x0f
340#define PIRQ_SIS_IRQ_DISABLE 0x80
341#define PIRQ_SIS_USB_ENABLE 0x40
342
343static int pirq_sis_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
344{
345 u8 x;
346 int reg;
347
348 reg = pirq;
349 if (reg >= 0x01 && reg <= 0x04)
350 reg += 0x40;
351 pci_read_config_byte(router, reg, &x);
352 return (x & PIRQ_SIS_IRQ_DISABLE) ? 0 : (x & PIRQ_SIS_IRQ_MASK);
353}
354
355static int pirq_sis_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
356{
357 u8 x;
358 int reg;
359
360 reg = pirq;
361 if (reg >= 0x01 && reg <= 0x04)
362 reg += 0x40;
363 pci_read_config_byte(router, reg, &x);
364 x &= ~(PIRQ_SIS_IRQ_MASK | PIRQ_SIS_IRQ_DISABLE);
365 x |= irq ? irq: PIRQ_SIS_IRQ_DISABLE;
366 pci_write_config_byte(router, reg, x);
367 return 1;
368}
369
370
371/*
372 * VLSI: nibble offset 0x74 - educated guess due to routing table and
373 * config space of VLSI 82C534 PCI-bridge/router (1004:0102)
374 * Tested on HP OmniBook 800 covering PIRQ 1, 2, 4, 8 for onboard
375 * devices, PIRQ 3 for non-pci(!) soundchip and (untested) PIRQ 6
376 * for the busbridge to the docking station.
377 */
378
379static int pirq_vlsi_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
380{
381 if (pirq > 8) {
382 printk(KERN_INFO "VLSI router pirq escape (%d)\n", pirq);
383 return 0;
384 }
385 return read_config_nybble(router, 0x74, pirq-1);
386}
387
388static int pirq_vlsi_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
389{
390 if (pirq > 8) {
391 printk(KERN_INFO "VLSI router pirq escape (%d)\n", pirq);
392 return 0;
393 }
394 write_config_nybble(router, 0x74, pirq-1, irq);
395 return 1;
396}
397
398/*
399 * ServerWorks: PCI interrupts mapped to system IRQ lines through Index
400 * and Redirect I/O registers (0x0c00 and 0x0c01). The Index register
401 * format is (PCIIRQ## | 0x10), e.g.: PCIIRQ10=0x1a. The Redirect
402 * register is a straight binary coding of desired PIC IRQ (low nibble).
403 *
404 * The 'link' value in the PIRQ table is already in the correct format
405 * for the Index register. There are some special index values:
406 * 0x00 for ACPI (SCI), 0x01 for USB, 0x02 for IDE0, 0x04 for IDE1,
407 * and 0x03 for SMBus.
408 */
409static int pirq_serverworks_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
410{
411 outb_p(pirq, 0xc00);
412 return inb(0xc01) & 0xf;
413}
414
415static int pirq_serverworks_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
416{
417 outb_p(pirq, 0xc00);
418 outb_p(irq, 0xc01);
419 return 1;
420}
421
422/* Support for AMD756 PCI IRQ Routing
423 * Jhon H. Caicedo <jhcaiced@osso.org.co>
424 * Jun/21/2001 0.2.0 Release, fixed to use "nybble" functions... (jhcaiced)
425 * Jun/19/2001 Alpha Release 0.1.0 (jhcaiced)
426 * The AMD756 pirq rules are nibble-based
427 * offset 0x56 0-3 PIRQA 4-7 PIRQB
428 * offset 0x57 0-3 PIRQC 4-7 PIRQD
429 */
430static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
431{
432 u8 irq;
433 irq = 0;
434 if (pirq <= 4)
435 {
436 irq = read_config_nybble(router, 0x56, pirq - 1);
437 }
438 printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d get irq : %2d\n",
439 dev->vendor, dev->device, pirq, irq);
440 return irq;
441}
442
443static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
444{
445 printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d SET irq : %2d\n",
446 dev->vendor, dev->device, pirq, irq);
447 if (pirq <= 4)
448 {
449 write_config_nybble(router, 0x56, pirq - 1, irq);
450 }
451 return 1;
452}
453
454#ifdef CONFIG_PCI_BIOS
455
456static int pirq_bios_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
457{
458 struct pci_dev *bridge;
459 int pin = pci_get_interrupt_pin(dev, &bridge);
460 return pcibios_set_irq_routing(bridge, pin, irq);
461}
462
463#endif
464
465static __init int intel_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
466{
467 static struct pci_device_id pirq_440gx[] = {
468 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0) },
469 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2) },
470 { },
471 };
472
473 /* 440GX has a proprietary PIRQ router -- don't use it */
474 if (pci_dev_present(pirq_440gx))
475 return 0;
476
477 switch(device)
478 {
479 case PCI_DEVICE_ID_INTEL_82371FB_0:
480 case PCI_DEVICE_ID_INTEL_82371SB_0:
481 case PCI_DEVICE_ID_INTEL_82371AB_0:
482 case PCI_DEVICE_ID_INTEL_82371MX:
483 case PCI_DEVICE_ID_INTEL_82443MX_0:
484 case PCI_DEVICE_ID_INTEL_82801AA_0:
485 case PCI_DEVICE_ID_INTEL_82801AB_0:
486 case PCI_DEVICE_ID_INTEL_82801BA_0:
487 case PCI_DEVICE_ID_INTEL_82801BA_10:
488 case PCI_DEVICE_ID_INTEL_82801CA_0:
489 case PCI_DEVICE_ID_INTEL_82801CA_12:
490 case PCI_DEVICE_ID_INTEL_82801DB_0:
491 case PCI_DEVICE_ID_INTEL_82801E_0:
492 case PCI_DEVICE_ID_INTEL_82801EB_0:
493 case PCI_DEVICE_ID_INTEL_ESB_1:
494 case PCI_DEVICE_ID_INTEL_ICH6_0:
495 case PCI_DEVICE_ID_INTEL_ICH6_1:
496 case PCI_DEVICE_ID_INTEL_ICH7_0:
497 case PCI_DEVICE_ID_INTEL_ICH7_1:
498 r->name = "PIIX/ICH";
499 r->get = pirq_piix_get;
500 r->set = pirq_piix_set;
501 return 1;
502 }
503 return 0;
504}
505
506static __init int via_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
507{
508 /* FIXME: We should move some of the quirk fixup stuff here */
509 switch(device)
510 {
511 case PCI_DEVICE_ID_VIA_82C586_0:
512 case PCI_DEVICE_ID_VIA_82C596:
513 case PCI_DEVICE_ID_VIA_82C686:
514 case PCI_DEVICE_ID_VIA_8231:
515 /* FIXME: add new ones for 8233/5 */
516 r->name = "VIA";
517 r->get = pirq_via_get;
518 r->set = pirq_via_set;
519 return 1;
520 }
521 return 0;
522}
523
524static __init int vlsi_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
525{
526 switch(device)
527 {
528 case PCI_DEVICE_ID_VLSI_82C534:
529 r->name = "VLSI 82C534";
530 r->get = pirq_vlsi_get;
531 r->set = pirq_vlsi_set;
532 return 1;
533 }
534 return 0;
535}
536
537
538static __init int serverworks_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
539{
540 switch(device)
541 {
542 case PCI_DEVICE_ID_SERVERWORKS_OSB4:
543 case PCI_DEVICE_ID_SERVERWORKS_CSB5:
544 r->name = "ServerWorks";
545 r->get = pirq_serverworks_get;
546 r->set = pirq_serverworks_set;
547 return 1;
548 }
549 return 0;
550}
551
552static __init int sis_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
553{
554 if (device != PCI_DEVICE_ID_SI_503)
555 return 0;
556
557 r->name = "SIS";
558 r->get = pirq_sis_get;
559 r->set = pirq_sis_set;
560 return 1;
561}
562
563static __init int cyrix_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
564{
565 switch(device)
566 {
567 case PCI_DEVICE_ID_CYRIX_5520:
568 r->name = "NatSemi";
569 r->get = pirq_cyrix_get;
570 r->set = pirq_cyrix_set;
571 return 1;
572 }
573 return 0;
574}
575
576static __init int opti_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
577{
578 switch(device)
579 {
580 case PCI_DEVICE_ID_OPTI_82C700:
581 r->name = "OPTI";
582 r->get = pirq_opti_get;
583 r->set = pirq_opti_set;
584 return 1;
585 }
586 return 0;
587}
588
589static __init int ite_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
590{
591 switch(device)
592 {
593 case PCI_DEVICE_ID_ITE_IT8330G_0:
594 r->name = "ITE";
595 r->get = pirq_ite_get;
596 r->set = pirq_ite_set;
597 return 1;
598 }
599 return 0;
600}
601
602static __init int ali_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
603{
604 switch(device)
605 {
606 case PCI_DEVICE_ID_AL_M1533:
607 case PCI_DEVICE_ID_AL_M1563:
608 printk("PCI: Using ALI IRQ Router\n");
609 r->name = "ALI";
610 r->get = pirq_ali_get;
611 r->set = pirq_ali_set;
612 return 1;
613 }
614 return 0;
615}
616
617static __init int amd_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
618{
619 switch(device)
620 {
621 case PCI_DEVICE_ID_AMD_VIPER_740B:
622 r->name = "AMD756";
623 break;
624 case PCI_DEVICE_ID_AMD_VIPER_7413:
625 r->name = "AMD766";
626 break;
627 case PCI_DEVICE_ID_AMD_VIPER_7443:
628 r->name = "AMD768";
629 break;
630 default:
631 return 0;
632 }
633 r->get = pirq_amd756_get;
634 r->set = pirq_amd756_set;
635 return 1;
636}
637
638static __initdata struct irq_router_handler pirq_routers[] = {
639 { PCI_VENDOR_ID_INTEL, intel_router_probe },
640 { PCI_VENDOR_ID_AL, ali_router_probe },
641 { PCI_VENDOR_ID_ITE, ite_router_probe },
642 { PCI_VENDOR_ID_VIA, via_router_probe },
643 { PCI_VENDOR_ID_OPTI, opti_router_probe },
644 { PCI_VENDOR_ID_SI, sis_router_probe },
645 { PCI_VENDOR_ID_CYRIX, cyrix_router_probe },
646 { PCI_VENDOR_ID_VLSI, vlsi_router_probe },
647 { PCI_VENDOR_ID_SERVERWORKS, serverworks_router_probe },
648 { PCI_VENDOR_ID_AMD, amd_router_probe },
649 /* Someone with docs needs to add the ATI Radeon IGP */
650 { 0, NULL }
651};
652static struct irq_router pirq_router;
653static struct pci_dev *pirq_router_dev;
654
655
656/*
657 * FIXME: should we have an option to say "generic for
658 * chipset" ?
659 */
660
661static void __init pirq_find_router(struct irq_router *r)
662{
663 struct irq_routing_table *rt = pirq_table;
664 struct irq_router_handler *h;
665
666#ifdef CONFIG_PCI_BIOS
667 if (!rt->signature) {
668 printk(KERN_INFO "PCI: Using BIOS for IRQ routing\n");
669 r->set = pirq_bios_set;
670 r->name = "BIOS";
671 return;
672 }
673#endif
674
675 /* Default unless a driver reloads it */
676 r->name = "default";
677 r->get = NULL;
678 r->set = NULL;
679
680 DBG("PCI: Attempting to find IRQ router for %04x:%04x\n",
681 rt->rtr_vendor, rt->rtr_device);
682
683 pirq_router_dev = pci_find_slot(rt->rtr_bus, rt->rtr_devfn);
684 if (!pirq_router_dev) {
685 DBG("PCI: Interrupt router not found at %02x:%02x\n", rt->rtr_bus, rt->rtr_devfn);
686 return;
687 }
688
689 for( h = pirq_routers; h->vendor; h++) {
690 /* First look for a router match */
691 if (rt->rtr_vendor == h->vendor && h->probe(r, pirq_router_dev, rt->rtr_device))
692 break;
693 /* Fall back to a device match */
694 if (pirq_router_dev->vendor == h->vendor && h->probe(r, pirq_router_dev, pirq_router_dev->device))
695 break;
696 }
697 printk(KERN_INFO "PCI: Using IRQ router %s [%04x/%04x] at %s\n",
698 pirq_router.name,
699 pirq_router_dev->vendor,
700 pirq_router_dev->device,
701 pci_name(pirq_router_dev));
702}
703
704static struct irq_info *pirq_get_info(struct pci_dev *dev)
705{
706 struct irq_routing_table *rt = pirq_table;
707 int entries = (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info);
708 struct irq_info *info;
709
710 for (info = rt->slots; entries--; info++)
711 if (info->bus == dev->bus->number && PCI_SLOT(info->devfn) == PCI_SLOT(dev->devfn))
712 return info;
713 return NULL;
714}
715
716static int pcibios_lookup_irq(struct pci_dev *dev, int assign)
717{
718 u8 pin;
719 struct irq_info *info;
720 int i, pirq, newirq;
721 int irq = 0;
722 u32 mask;
723 struct irq_router *r = &pirq_router;
724 struct pci_dev *dev2 = NULL;
725 char *msg = NULL;
726
727 /* Find IRQ pin */
728 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
729 if (!pin) {
730 DBG(" -> no interrupt pin\n");
731 return 0;
732 }
733 pin = pin - 1;
734
735 /* Find IRQ routing entry */
736
737 if (!pirq_table)
738 return 0;
739
740 DBG("IRQ for %s[%c]", pci_name(dev), 'A' + pin);
741 info = pirq_get_info(dev);
742 if (!info) {
743 DBG(" -> not found in routing table\n");
744 return 0;
745 }
746 pirq = info->irq[pin].link;
747 mask = info->irq[pin].bitmap;
748 if (!pirq) {
749 DBG(" -> not routed\n");
750 return 0;
751 }
752 DBG(" -> PIRQ %02x, mask %04x, excl %04x", pirq, mask, pirq_table->exclusive_irqs);
753 mask &= pcibios_irq_mask;
754
755 /* Work around broken HP Pavilion Notebooks which assign USB to
756 IRQ 9 even though it is actually wired to IRQ 11 */
757
758 if (broken_hp_bios_irq9 && pirq == 0x59 && dev->irq == 9) {
759 dev->irq = 11;
760 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
761 r->set(pirq_router_dev, dev, pirq, 11);
762 }
763
764 /* same for Acer Travelmate 360, but with CB and irq 11 -> 10 */
765 if (acer_tm360_irqrouting && dev->irq == 11 && dev->vendor == PCI_VENDOR_ID_O2) {
766 pirq = 0x68;
767 mask = 0x400;
768 dev->irq = r->get(pirq_router_dev, dev, pirq);
769 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
770 }
771
772 /*
773 * Find the best IRQ to assign: use the one
774 * reported by the device if possible.
775 */
776 newirq = dev->irq;
777 if (!((1 << newirq) & mask)) {
778 if ( pci_probe & PCI_USE_PIRQ_MASK) newirq = 0;
779 else printk(KERN_WARNING "PCI: IRQ %i for device %s doesn't match PIRQ mask - try pci=usepirqmask\n", newirq, pci_name(dev));
780 }
781 if (!newirq && assign) {
782 for (i = 0; i < 16; i++) {
783 if (!(mask & (1 << i)))
784 continue;
785 if (pirq_penalty[i] < pirq_penalty[newirq] && can_request_irq(i, SA_SHIRQ))
786 newirq = i;
787 }
788 }
789 DBG(" -> newirq=%d", newirq);
790
791 /* Check if it is hardcoded */
792 if ((pirq & 0xf0) == 0xf0) {
793 irq = pirq & 0xf;
794 DBG(" -> hardcoded IRQ %d\n", irq);
795 msg = "Hardcoded";
796 } else if ( r->get && (irq = r->get(pirq_router_dev, dev, pirq)) && \
797 ((!(pci_probe & PCI_USE_PIRQ_MASK)) || ((1 << irq) & mask)) ) {
798 DBG(" -> got IRQ %d\n", irq);
799 msg = "Found";
800 } else if (newirq && r->set && (dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) {
801 DBG(" -> assigning IRQ %d", newirq);
802 if (r->set(pirq_router_dev, dev, pirq, newirq)) {
803 eisa_set_level_irq(newirq);
804 DBG(" ... OK\n");
805 msg = "Assigned";
806 irq = newirq;
807 }
808 }
809
810 if (!irq) {
811 DBG(" ... failed\n");
812 if (newirq && mask == (1 << newirq)) {
813 msg = "Guessed";
814 irq = newirq;
815 } else
816 return 0;
817 }
818 printk(KERN_INFO "PCI: %s IRQ %d for device %s\n", msg, irq, pci_name(dev));
819
820 /* Update IRQ for all devices with the same pirq value */
821 while ((dev2 = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev2)) != NULL) {
822 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin);
823 if (!pin)
824 continue;
825 pin--;
826 info = pirq_get_info(dev2);
827 if (!info)
828 continue;
829 if (info->irq[pin].link == pirq) {
830 /* We refuse to override the dev->irq information. Give a warning! */
831 if ( dev2->irq && dev2->irq != irq && \
832 (!(pci_probe & PCI_USE_PIRQ_MASK) || \
833 ((1 << dev2->irq) & mask)) ) {
834#ifndef CONFIG_PCI_MSI
835 printk(KERN_INFO "IRQ routing conflict for %s, have irq %d, want irq %d\n",
836 pci_name(dev2), dev2->irq, irq);
837#endif
838 continue;
839 }
840 dev2->irq = irq;
841 pirq_penalty[irq]++;
842 if (dev != dev2)
843 printk(KERN_INFO "PCI: Sharing IRQ %d with %s\n", irq, pci_name(dev2));
844 }
845 }
846 return 1;
847}
848
849static void __init pcibios_fixup_irqs(void)
850{
851 struct pci_dev *dev = NULL;
852 u8 pin;
853
854 DBG("PCI: IRQ fixup\n");
855 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
856 /*
857 * If the BIOS has set an out of range IRQ number, just ignore it.
858 * Also keep track of which IRQ's are already in use.
859 */
860 if (dev->irq >= 16) {
861 DBG("%s: ignoring bogus IRQ %d\n", pci_name(dev), dev->irq);
862 dev->irq = 0;
863 }
864 /* If the IRQ is already assigned to a PCI device, ignore its ISA use penalty */
865 if (pirq_penalty[dev->irq] >= 100 && pirq_penalty[dev->irq] < 100000)
866 pirq_penalty[dev->irq] = 0;
867 pirq_penalty[dev->irq]++;
868 }
869
870 dev = NULL;
871 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
872 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
873#ifdef CONFIG_X86_IO_APIC
874 /*
875 * Recalculate IRQ numbers if we use the I/O APIC.
876 */
877 if (io_apic_assign_pci_irqs)
878 {
879 int irq;
880
881 if (pin) {
882 pin--; /* interrupt pins are numbered starting from 1 */
883 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, PCI_SLOT(dev->devfn), pin);
884 /*
885 * Busses behind bridges are typically not listed in the MP-table.
886 * In this case we have to look up the IRQ based on the parent bus,
887 * parent slot, and pin number. The SMP code detects such bridged
888 * busses itself so we should get into this branch reliably.
889 */
890 if (irq < 0 && dev->bus->parent) { /* go back to the bridge */
891 struct pci_dev * bridge = dev->bus->self;
892
893 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
894 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
895 PCI_SLOT(bridge->devfn), pin);
896 if (irq >= 0)
897 printk(KERN_WARNING "PCI: using PPB %s[%c] to get irq %d\n",
898 pci_name(bridge), 'A' + pin, irq);
899 }
900 if (irq >= 0) {
901 if (use_pci_vector() &&
902 !platform_legacy_irq(irq))
903 irq = IO_APIC_VECTOR(irq);
904
905 printk(KERN_INFO "PCI->APIC IRQ transform: %s[%c] -> IRQ %d\n",
906 pci_name(dev), 'A' + pin, irq);
907 dev->irq = irq;
908 }
909 }
910 }
911#endif
912 /*
913 * Still no IRQ? Try to lookup one...
914 */
915 if (pin && !dev->irq)
916 pcibios_lookup_irq(dev, 0);
917 }
918}
919
920/*
921 * Work around broken HP Pavilion Notebooks which assign USB to
922 * IRQ 9 even though it is actually wired to IRQ 11
923 */
924static int __init fix_broken_hp_bios_irq9(struct dmi_system_id *d)
925{
926 if (!broken_hp_bios_irq9) {
927 broken_hp_bios_irq9 = 1;
928 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n", d->ident);
929 }
930 return 0;
931}
932
933/*
934 * Work around broken Acer TravelMate 360 Notebooks which assign
935 * Cardbus to IRQ 11 even though it is actually wired to IRQ 10
936 */
937static int __init fix_acer_tm360_irqrouting(struct dmi_system_id *d)
938{
939 if (!acer_tm360_irqrouting) {
940 acer_tm360_irqrouting = 1;
941 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n", d->ident);
942 }
943 return 0;
944}
945
946static struct dmi_system_id __initdata pciirq_dmi_table[] = {
947 {
948 .callback = fix_broken_hp_bios_irq9,
949 .ident = "HP Pavilion N5400 Series Laptop",
950 .matches = {
951 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
952 DMI_MATCH(DMI_BIOS_VERSION, "GE.M1.03"),
953 DMI_MATCH(DMI_PRODUCT_VERSION, "HP Pavilion Notebook Model GE"),
954 DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"),
955 },
956 },
957 {
958 .callback = fix_acer_tm360_irqrouting,
959 .ident = "Acer TravelMate 36x Laptop",
960 .matches = {
961 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
962 DMI_MATCH(DMI_PRODUCT_NAME, "TravelMate 360"),
963 },
964 },
965 { }
966};
967
968static int __init pcibios_irq_init(void)
969{
970 DBG("PCI: IRQ init\n");
971
972 if (pcibios_enable_irq || raw_pci_ops == NULL)
973 return 0;
974
975 dmi_check_system(pciirq_dmi_table);
976
977 pirq_table = pirq_find_routing_table();
978
979#ifdef CONFIG_PCI_BIOS
980 if (!pirq_table && (pci_probe & PCI_BIOS_IRQ_SCAN))
981 pirq_table = pcibios_get_irq_routing_table();
982#endif
983 if (pirq_table) {
984 pirq_peer_trick();
985 pirq_find_router(&pirq_router);
986 if (pirq_table->exclusive_irqs) {
987 int i;
988 for (i=0; i<16; i++)
989 if (!(pirq_table->exclusive_irqs & (1 << i)))
990 pirq_penalty[i] += 100;
991 }
992 /* If we're using the I/O APIC, avoid using the PCI IRQ routing table */
993 if (io_apic_assign_pci_irqs)
994 pirq_table = NULL;
995 }
996
997 pcibios_enable_irq = pirq_enable_irq;
998
999 pcibios_fixup_irqs();
1000 return 0;
1001}
1002
1003subsys_initcall(pcibios_irq_init);
1004
1005
1006static void pirq_penalize_isa_irq(int irq)
1007{
1008 /*
1009 * If any ISAPnP device reports an IRQ in its list of possible
1010 * IRQ's, we try to avoid assigning it to PCI devices.
1011 */
1012 if (irq < 16)
1013 pirq_penalty[irq] += 100;
1014}
1015
1016void pcibios_penalize_isa_irq(int irq)
1017{
1018#ifdef CONFIG_ACPI_PCI
1019 if (!acpi_noirq)
1020 acpi_penalize_isa_irq(irq);
1021 else
1022#endif
1023 pirq_penalize_isa_irq(irq);
1024}
1025
1026static int pirq_enable_irq(struct pci_dev *dev)
1027{
1028 u8 pin;
1029 extern int via_interrupt_line_quirk;
1030 struct pci_dev *temp_dev;
1031
1032 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1033 if (pin && !pcibios_lookup_irq(dev, 1) && !dev->irq) {
1034 char *msg = "";
1035
1036 pin--; /* interrupt pins are numbered starting from 1 */
1037
1038 if (io_apic_assign_pci_irqs) {
1039 int irq;
1040
1041 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, PCI_SLOT(dev->devfn), pin);
1042 /*
1043 * Busses behind bridges are typically not listed in the MP-table.
1044 * In this case we have to look up the IRQ based on the parent bus,
1045 * parent slot, and pin number. The SMP code detects such bridged
1046 * busses itself so we should get into this branch reliably.
1047 */
1048 temp_dev = dev;
1049 while (irq < 0 && dev->bus->parent) { /* go back to the bridge */
1050 struct pci_dev * bridge = dev->bus->self;
1051
1052 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
1053 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
1054 PCI_SLOT(bridge->devfn), pin);
1055 if (irq >= 0)
1056 printk(KERN_WARNING "PCI: using PPB %s[%c] to get irq %d\n",
1057 pci_name(bridge), 'A' + pin, irq);
1058 dev = bridge;
1059 }
1060 dev = temp_dev;
1061 if (irq >= 0) {
1062#ifdef CONFIG_PCI_MSI
1063 if (!platform_legacy_irq(irq))
1064 irq = IO_APIC_VECTOR(irq);
1065#endif
1066 printk(KERN_INFO "PCI->APIC IRQ transform: %s[%c] -> IRQ %d\n",
1067 pci_name(dev), 'A' + pin, irq);
1068 dev->irq = irq;
1069 return 0;
1070 } else
1071 msg = " Probably buggy MP table.";
1072 } else if (pci_probe & PCI_BIOS_IRQ_SCAN)
1073 msg = "";
1074 else
1075 msg = " Please try using pci=biosirq.";
1076
1077 /* With IDE legacy devices the IRQ lookup failure is not a problem.. */
1078 if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE && !(dev->class & 0x5))
1079 return 0;
1080
1081 printk(KERN_WARNING "PCI: No IRQ known for interrupt pin %c of device %s.%s\n",
1082 'A' + pin, pci_name(dev), msg);
1083 }
1084 /* VIA bridges use interrupt line for apic/pci steering across
1085 the V-Link */
1086 else if (via_interrupt_line_quirk)
1087 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq & 15);
1088 return 0;
1089}
1090
1091int pci_vector_resources(int last, int nr_released)
1092{
1093 int count = nr_released;
1094
1095 int next = last;
1096 int offset = (last % 8);
1097
1098 while (next < FIRST_SYSTEM_VECTOR) {
1099 next += 8;
1100#ifdef CONFIG_X86_64
1101 if (next == IA32_SYSCALL_VECTOR)
1102 continue;
1103#else
1104 if (next == SYSCALL_VECTOR)
1105 continue;
1106#endif
1107 count++;
1108 if (next >= FIRST_SYSTEM_VECTOR) {
1109 if (offset%8) {
1110 next = FIRST_DEVICE_VECTOR + offset;
1111 offset++;
1112 continue;
1113 }
1114 count--;
1115 }
1116 }
1117
1118 return count;
1119}
diff --git a/arch/i386/pci/legacy.c b/arch/i386/pci/legacy.c
new file mode 100644
index 00000000000..1492e375386
--- /dev/null
+++ b/arch/i386/pci/legacy.c
@@ -0,0 +1,54 @@
1/*
2 * legacy.c - traditional, old school PCI bus probing
3 */
4#include <linux/init.h>
5#include <linux/pci.h>
6#include "pci.h"
7
8/*
9 * Discover remaining PCI buses in case there are peer host bridges.
10 * We use the number of last PCI bus provided by the PCI BIOS.
11 */
12static void __devinit pcibios_fixup_peer_bridges(void)
13{
14 int n, devfn;
15
16 if (pcibios_last_bus <= 0 || pcibios_last_bus >= 0xff)
17 return;
18 DBG("PCI: Peer bridge fixup\n");
19
20 for (n=0; n <= pcibios_last_bus; n++) {
21 u32 l;
22 if (pci_find_bus(0, n))
23 continue;
24 for (devfn = 0; devfn < 256; devfn += 8) {
25 if (!raw_pci_ops->read(0, n, devfn, PCI_VENDOR_ID, 2, &l) &&
26 l != 0x0000 && l != 0xffff) {
27 DBG("Found device at %02x:%02x [%04x]\n", n, devfn, l);
28 printk(KERN_INFO "PCI: Discovered peer bus %02x\n", n);
29 pci_scan_bus(n, &pci_root_ops, NULL);
30 break;
31 }
32 }
33 }
34}
35
36static int __init pci_legacy_init(void)
37{
38 if (!raw_pci_ops) {
39 printk("PCI: System does not support PCI\n");
40 return 0;
41 }
42
43 if (pcibios_scanned++)
44 return 0;
45
46 printk("PCI: Probing PCI hardware\n");
47 pci_root_bus = pcibios_scan_root(0);
48
49 pcibios_fixup_peer_bridges();
50
51 return 0;
52}
53
54subsys_initcall(pci_legacy_init);
diff --git a/arch/i386/pci/mmconfig.c b/arch/i386/pci/mmconfig.c
new file mode 100644
index 00000000000..021a50aa51f
--- /dev/null
+++ b/arch/i386/pci/mmconfig.c
@@ -0,0 +1,122 @@
1/*
2 * Copyright (C) 2004 Matthew Wilcox <matthew@wil.cx>
3 * Copyright (C) 2004 Intel Corp.
4 *
5 * This code is released under the GNU General Public License version 2.
6 */
7
8/*
9 * mmconfig.c - Low-level direct PCI config space access via MMCONFIG
10 */
11
12#include <linux/pci.h>
13#include <linux/init.h>
14#include "pci.h"
15
16/* The physical address of the MMCONFIG aperture. Set from ACPI tables. */
17u32 pci_mmcfg_base_addr;
18
19#define mmcfg_virt_addr ((void __iomem *) fix_to_virt(FIX_PCIE_MCFG))
20
21/* The base address of the last MMCONFIG device accessed */
22static u32 mmcfg_last_accessed_device;
23
24/*
25 * Functions for accessing PCI configuration space with MMCONFIG accesses
26 */
27
28static inline void pci_exp_set_dev_base(int bus, int devfn)
29{
30 u32 dev_base = pci_mmcfg_base_addr | (bus << 20) | (devfn << 12);
31 if (dev_base != mmcfg_last_accessed_device) {
32 mmcfg_last_accessed_device = dev_base;
33 set_fixmap_nocache(FIX_PCIE_MCFG, dev_base);
34 }
35}
36
37static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
38 unsigned int devfn, int reg, int len, u32 *value)
39{
40 unsigned long flags;
41
42 if (!value || (bus > 255) || (devfn > 255) || (reg > 4095))
43 return -EINVAL;
44
45 spin_lock_irqsave(&pci_config_lock, flags);
46
47 pci_exp_set_dev_base(bus, devfn);
48
49 switch (len) {
50 case 1:
51 *value = readb(mmcfg_virt_addr + reg);
52 break;
53 case 2:
54 *value = readw(mmcfg_virt_addr + reg);
55 break;
56 case 4:
57 *value = readl(mmcfg_virt_addr + reg);
58 break;
59 }
60
61 spin_unlock_irqrestore(&pci_config_lock, flags);
62
63 return 0;
64}
65
66static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
67 unsigned int devfn, int reg, int len, u32 value)
68{
69 unsigned long flags;
70
71 if ((bus > 255) || (devfn > 255) || (reg > 4095))
72 return -EINVAL;
73
74 spin_lock_irqsave(&pci_config_lock, flags);
75
76 pci_exp_set_dev_base(bus, devfn);
77
78 switch (len) {
79 case 1:
80 writeb(value, mmcfg_virt_addr + reg);
81 break;
82 case 2:
83 writew(value, mmcfg_virt_addr + reg);
84 break;
85 case 4:
86 writel(value, mmcfg_virt_addr + reg);
87 break;
88 }
89
90 spin_unlock_irqrestore(&pci_config_lock, flags);
91
92 return 0;
93}
94
95static struct pci_raw_ops pci_mmcfg = {
96 .read = pci_mmcfg_read,
97 .write = pci_mmcfg_write,
98};
99
100static int __init pci_mmcfg_init(void)
101{
102 if ((pci_probe & PCI_PROBE_MMCONF) == 0)
103 goto out;
104 if (!pci_mmcfg_base_addr)
105 goto out;
106
107 /* Kludge for now. Don't use mmconfig on AMD systems because
108 those have some busses where mmconfig doesn't work,
109 and we don't parse ACPI MCFG well enough to handle that.
110 Remove when proper handling is added. */
111 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
112 goto out;
113
114 printk(KERN_INFO "PCI: Using MMCONFIG\n");
115 raw_pci_ops = &pci_mmcfg;
116 pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
117
118 out:
119 return 0;
120}
121
122arch_initcall(pci_mmcfg_init);
diff --git a/arch/i386/pci/numa.c b/arch/i386/pci/numa.c
new file mode 100644
index 00000000000..9e369546189
--- /dev/null
+++ b/arch/i386/pci/numa.c
@@ -0,0 +1,130 @@
1/*
2 * numa.c - Low-level PCI access for NUMA-Q machines
3 */
4
5#include <linux/pci.h>
6#include <linux/init.h>
7#include <linux/nodemask.h>
8#include "pci.h"
9
10#define BUS2QUAD(global) (mp_bus_id_to_node[global])
11#define BUS2LOCAL(global) (mp_bus_id_to_local[global])
12#define QUADLOCAL2BUS(quad,local) (quad_local_to_mp_bus_id[quad][local])
13
14#define PCI_CONF1_MQ_ADDRESS(bus, devfn, reg) \
15 (0x80000000 | (BUS2LOCAL(bus) << 16) | (devfn << 8) | (reg & ~3))
16
17static int pci_conf1_mq_read(unsigned int seg, unsigned int bus,
18 unsigned int devfn, int reg, int len, u32 *value)
19{
20 unsigned long flags;
21
22 if (!value || (bus >= MAX_MP_BUSSES) || (devfn > 255) || (reg > 255))
23 return -EINVAL;
24
25 spin_lock_irqsave(&pci_config_lock, flags);
26
27 outl_quad(PCI_CONF1_MQ_ADDRESS(bus, devfn, reg), 0xCF8, BUS2QUAD(bus));
28
29 switch (len) {
30 case 1:
31 *value = inb_quad(0xCFC + (reg & 3), BUS2QUAD(bus));
32 break;
33 case 2:
34 *value = inw_quad(0xCFC + (reg & 2), BUS2QUAD(bus));
35 break;
36 case 4:
37 *value = inl_quad(0xCFC, BUS2QUAD(bus));
38 break;
39 }
40
41 spin_unlock_irqrestore(&pci_config_lock, flags);
42
43 return 0;
44}
45
46static int pci_conf1_mq_write(unsigned int seg, unsigned int bus,
47 unsigned int devfn, int reg, int len, u32 value)
48{
49 unsigned long flags;
50
51 if ((bus >= MAX_MP_BUSSES) || (devfn > 255) || (reg > 255))
52 return -EINVAL;
53
54 spin_lock_irqsave(&pci_config_lock, flags);
55
56 outl_quad(PCI_CONF1_MQ_ADDRESS(bus, devfn, reg), 0xCF8, BUS2QUAD(bus));
57
58 switch (len) {
59 case 1:
60 outb_quad((u8)value, 0xCFC + (reg & 3), BUS2QUAD(bus));
61 break;
62 case 2:
63 outw_quad((u16)value, 0xCFC + (reg & 2), BUS2QUAD(bus));
64 break;
65 case 4:
66 outl_quad((u32)value, 0xCFC, BUS2QUAD(bus));
67 break;
68 }
69
70 spin_unlock_irqrestore(&pci_config_lock, flags);
71
72 return 0;
73}
74
75#undef PCI_CONF1_MQ_ADDRESS
76
77static struct pci_raw_ops pci_direct_conf1_mq = {
78 .read = pci_conf1_mq_read,
79 .write = pci_conf1_mq_write
80};
81
82
83static void __devinit pci_fixup_i450nx(struct pci_dev *d)
84{
85 /*
86 * i450NX -- Find and scan all secondary buses on all PXB's.
87 */
88 int pxb, reg;
89 u8 busno, suba, subb;
90 int quad = BUS2QUAD(d->bus->number);
91
92 printk("PCI: Searching for i450NX host bridges on %s\n", pci_name(d));
93 reg = 0xd0;
94 for(pxb=0; pxb<2; pxb++) {
95 pci_read_config_byte(d, reg++, &busno);
96 pci_read_config_byte(d, reg++, &suba);
97 pci_read_config_byte(d, reg++, &subb);
98 DBG("i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno, suba, subb);
99 if (busno)
100 pci_scan_bus(QUADLOCAL2BUS(quad,busno), &pci_root_ops, NULL); /* Bus A */
101 if (suba < subb)
102 pci_scan_bus(QUADLOCAL2BUS(quad,suba+1), &pci_root_ops, NULL); /* Bus B */
103 }
104 pcibios_last_bus = -1;
105}
106DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx);
107
108static int __init pci_numa_init(void)
109{
110 int quad;
111
112 raw_pci_ops = &pci_direct_conf1_mq;
113
114 if (pcibios_scanned++)
115 return 0;
116
117 pci_root_bus = pcibios_scan_root(0);
118 if (num_online_nodes() > 1)
119 for_each_online_node(quad) {
120 if (quad == 0)
121 continue;
122 printk("Scanning PCI bus %d for quad %d\n",
123 QUADLOCAL2BUS(quad,0), quad);
124 pci_scan_bus(QUADLOCAL2BUS(quad,0),
125 &pci_root_ops, NULL);
126 }
127 return 0;
128}
129
130subsys_initcall(pci_numa_init);
diff --git a/arch/i386/pci/pcbios.c b/arch/i386/pci/pcbios.c
new file mode 100644
index 00000000000..141421b673b
--- /dev/null
+++ b/arch/i386/pci/pcbios.c
@@ -0,0 +1,487 @@
1/*
2 * BIOS32 and PCI BIOS handling.
3 */
4
5#include <linux/pci.h>
6#include <linux/init.h>
7#include "pci.h"
8#include "pci-functions.h"
9
10
11/* BIOS32 signature: "_32_" */
12#define BIOS32_SIGNATURE (('_' << 0) + ('3' << 8) + ('2' << 16) + ('_' << 24))
13
14/* PCI signature: "PCI " */
15#define PCI_SIGNATURE (('P' << 0) + ('C' << 8) + ('I' << 16) + (' ' << 24))
16
17/* PCI service signature: "$PCI" */
18#define PCI_SERVICE (('$' << 0) + ('P' << 8) + ('C' << 16) + ('I' << 24))
19
20/* PCI BIOS hardware mechanism flags */
21#define PCIBIOS_HW_TYPE1 0x01
22#define PCIBIOS_HW_TYPE2 0x02
23#define PCIBIOS_HW_TYPE1_SPEC 0x10
24#define PCIBIOS_HW_TYPE2_SPEC 0x20
25
26/*
27 * This is the standard structure used to identify the entry point
28 * to the BIOS32 Service Directory, as documented in
29 * Standard BIOS 32-bit Service Directory Proposal
30 * Revision 0.4 May 24, 1993
31 * Phoenix Technologies Ltd.
32 * Norwood, MA
33 * and the PCI BIOS specification.
34 */
35
36union bios32 {
37 struct {
38 unsigned long signature; /* _32_ */
39 unsigned long entry; /* 32 bit physical address */
40 unsigned char revision; /* Revision level, 0 */
41 unsigned char length; /* Length in paragraphs should be 01 */
42 unsigned char checksum; /* All bytes must add up to zero */
43 unsigned char reserved[5]; /* Must be zero */
44 } fields;
45 char chars[16];
46};
47
48/*
49 * Physical address of the service directory. I don't know if we're
50 * allowed to have more than one of these or not, so just in case
51 * we'll make pcibios_present() take a memory start parameter and store
52 * the array there.
53 */
54
55static struct {
56 unsigned long address;
57 unsigned short segment;
58} bios32_indirect = { 0, __KERNEL_CS };
59
60/*
61 * Returns the entry point for the given service, NULL on error
62 */
63
64static unsigned long bios32_service(unsigned long service)
65{
66 unsigned char return_code; /* %al */
67 unsigned long address; /* %ebx */
68 unsigned long length; /* %ecx */
69 unsigned long entry; /* %edx */
70 unsigned long flags;
71
72 local_irq_save(flags);
73 __asm__("lcall *(%%edi); cld"
74 : "=a" (return_code),
75 "=b" (address),
76 "=c" (length),
77 "=d" (entry)
78 : "0" (service),
79 "1" (0),
80 "D" (&bios32_indirect));
81 local_irq_restore(flags);
82
83 switch (return_code) {
84 case 0:
85 return address + entry;
86 case 0x80: /* Not present */
87 printk(KERN_WARNING "bios32_service(0x%lx): not present\n", service);
88 return 0;
89 default: /* Shouldn't happen */
90 printk(KERN_WARNING "bios32_service(0x%lx): returned 0x%x -- BIOS bug!\n",
91 service, return_code);
92 return 0;
93 }
94}
95
96static struct {
97 unsigned long address;
98 unsigned short segment;
99} pci_indirect = { 0, __KERNEL_CS };
100
101static int pci_bios_present;
102
103static int __devinit check_pcibios(void)
104{
105 u32 signature, eax, ebx, ecx;
106 u8 status, major_ver, minor_ver, hw_mech;
107 unsigned long flags, pcibios_entry;
108
109 if ((pcibios_entry = bios32_service(PCI_SERVICE))) {
110 pci_indirect.address = pcibios_entry + PAGE_OFFSET;
111
112 local_irq_save(flags);
113 __asm__(
114 "lcall *(%%edi); cld\n\t"
115 "jc 1f\n\t"
116 "xor %%ah, %%ah\n"
117 "1:"
118 : "=d" (signature),
119 "=a" (eax),
120 "=b" (ebx),
121 "=c" (ecx)
122 : "1" (PCIBIOS_PCI_BIOS_PRESENT),
123 "D" (&pci_indirect)
124 : "memory");
125 local_irq_restore(flags);
126
127 status = (eax >> 8) & 0xff;
128 hw_mech = eax & 0xff;
129 major_ver = (ebx >> 8) & 0xff;
130 minor_ver = ebx & 0xff;
131 if (pcibios_last_bus < 0)
132 pcibios_last_bus = ecx & 0xff;
133 DBG("PCI: BIOS probe returned s=%02x hw=%02x ver=%02x.%02x l=%02x\n",
134 status, hw_mech, major_ver, minor_ver, pcibios_last_bus);
135 if (status || signature != PCI_SIGNATURE) {
136 printk (KERN_ERR "PCI: BIOS BUG #%x[%08x] found\n",
137 status, signature);
138 return 0;
139 }
140 printk(KERN_INFO "PCI: PCI BIOS revision %x.%02x entry at 0x%lx, last bus=%d\n",
141 major_ver, minor_ver, pcibios_entry, pcibios_last_bus);
142#ifdef CONFIG_PCI_DIRECT
143 if (!(hw_mech & PCIBIOS_HW_TYPE1))
144 pci_probe &= ~PCI_PROBE_CONF1;
145 if (!(hw_mech & PCIBIOS_HW_TYPE2))
146 pci_probe &= ~PCI_PROBE_CONF2;
147#endif
148 return 1;
149 }
150 return 0;
151}
152
153static int __devinit pci_bios_find_device (unsigned short vendor, unsigned short device_id,
154 unsigned short index, unsigned char *bus, unsigned char *device_fn)
155{
156 unsigned short bx;
157 unsigned short ret;
158
159 __asm__("lcall *(%%edi); cld\n\t"
160 "jc 1f\n\t"
161 "xor %%ah, %%ah\n"
162 "1:"
163 : "=b" (bx),
164 "=a" (ret)
165 : "1" (PCIBIOS_FIND_PCI_DEVICE),
166 "c" (device_id),
167 "d" (vendor),
168 "S" ((int) index),
169 "D" (&pci_indirect));
170 *bus = (bx >> 8) & 0xff;
171 *device_fn = bx & 0xff;
172 return (int) (ret & 0xff00) >> 8;
173}
174
175static int pci_bios_read(unsigned int seg, unsigned int bus,
176 unsigned int devfn, int reg, int len, u32 *value)
177{
178 unsigned long result = 0;
179 unsigned long flags;
180 unsigned long bx = (bus << 8) | devfn;
181
182 if (!value || (bus > 255) || (devfn > 255) || (reg > 255))
183 return -EINVAL;
184
185 spin_lock_irqsave(&pci_config_lock, flags);
186
187 switch (len) {
188 case 1:
189 __asm__("lcall *(%%esi); cld\n\t"
190 "jc 1f\n\t"
191 "xor %%ah, %%ah\n"
192 "1:"
193 : "=c" (*value),
194 "=a" (result)
195 : "1" (PCIBIOS_READ_CONFIG_BYTE),
196 "b" (bx),
197 "D" ((long)reg),
198 "S" (&pci_indirect));
199 break;
200 case 2:
201 __asm__("lcall *(%%esi); cld\n\t"
202 "jc 1f\n\t"
203 "xor %%ah, %%ah\n"
204 "1:"
205 : "=c" (*value),
206 "=a" (result)
207 : "1" (PCIBIOS_READ_CONFIG_WORD),
208 "b" (bx),
209 "D" ((long)reg),
210 "S" (&pci_indirect));
211 break;
212 case 4:
213 __asm__("lcall *(%%esi); cld\n\t"
214 "jc 1f\n\t"
215 "xor %%ah, %%ah\n"
216 "1:"
217 : "=c" (*value),
218 "=a" (result)
219 : "1" (PCIBIOS_READ_CONFIG_DWORD),
220 "b" (bx),
221 "D" ((long)reg),
222 "S" (&pci_indirect));
223 break;
224 }
225
226 spin_unlock_irqrestore(&pci_config_lock, flags);
227
228 return (int)((result & 0xff00) >> 8);
229}
230
231static int pci_bios_write(unsigned int seg, unsigned int bus,
232 unsigned int devfn, int reg, int len, u32 value)
233{
234 unsigned long result = 0;
235 unsigned long flags;
236 unsigned long bx = (bus << 8) | devfn;
237
238 if ((bus > 255) || (devfn > 255) || (reg > 255))
239 return -EINVAL;
240
241 spin_lock_irqsave(&pci_config_lock, flags);
242
243 switch (len) {
244 case 1:
245 __asm__("lcall *(%%esi); cld\n\t"
246 "jc 1f\n\t"
247 "xor %%ah, %%ah\n"
248 "1:"
249 : "=a" (result)
250 : "0" (PCIBIOS_WRITE_CONFIG_BYTE),
251 "c" (value),
252 "b" (bx),
253 "D" ((long)reg),
254 "S" (&pci_indirect));
255 break;
256 case 2:
257 __asm__("lcall *(%%esi); cld\n\t"
258 "jc 1f\n\t"
259 "xor %%ah, %%ah\n"
260 "1:"
261 : "=a" (result)
262 : "0" (PCIBIOS_WRITE_CONFIG_WORD),
263 "c" (value),
264 "b" (bx),
265 "D" ((long)reg),
266 "S" (&pci_indirect));
267 break;
268 case 4:
269 __asm__("lcall *(%%esi); cld\n\t"
270 "jc 1f\n\t"
271 "xor %%ah, %%ah\n"
272 "1:"
273 : "=a" (result)
274 : "0" (PCIBIOS_WRITE_CONFIG_DWORD),
275 "c" (value),
276 "b" (bx),
277 "D" ((long)reg),
278 "S" (&pci_indirect));
279 break;
280 }
281
282 spin_unlock_irqrestore(&pci_config_lock, flags);
283
284 return (int)((result & 0xff00) >> 8);
285}
286
287
288/*
289 * Function table for BIOS32 access
290 */
291
292static struct pci_raw_ops pci_bios_access = {
293 .read = pci_bios_read,
294 .write = pci_bios_write
295};
296
297/*
298 * Try to find PCI BIOS.
299 */
300
301static struct pci_raw_ops * __devinit pci_find_bios(void)
302{
303 union bios32 *check;
304 unsigned char sum;
305 int i, length;
306
307 /*
308 * Follow the standard procedure for locating the BIOS32 Service
309 * directory by scanning the permissible address range from
310 * 0xe0000 through 0xfffff for a valid BIOS32 structure.
311 */
312
313 for (check = (union bios32 *) __va(0xe0000);
314 check <= (union bios32 *) __va(0xffff0);
315 ++check) {
316 if (check->fields.signature != BIOS32_SIGNATURE)
317 continue;
318 length = check->fields.length * 16;
319 if (!length)
320 continue;
321 sum = 0;
322 for (i = 0; i < length ; ++i)
323 sum += check->chars[i];
324 if (sum != 0)
325 continue;
326 if (check->fields.revision != 0) {
327 printk("PCI: unsupported BIOS32 revision %d at 0x%p\n",
328 check->fields.revision, check);
329 continue;
330 }
331 DBG("PCI: BIOS32 Service Directory structure at 0x%p\n", check);
332 if (check->fields.entry >= 0x100000) {
333 printk("PCI: BIOS32 entry (0x%p) in high memory, cannot use.\n", check);
334 return NULL;
335 } else {
336 unsigned long bios32_entry = check->fields.entry;
337 DBG("PCI: BIOS32 Service Directory entry at 0x%lx\n", bios32_entry);
338 bios32_indirect.address = bios32_entry + PAGE_OFFSET;
339 if (check_pcibios())
340 return &pci_bios_access;
341 }
342 break; /* Hopefully more than one BIOS32 cannot happen... */
343 }
344
345 return NULL;
346}
347
348/*
349 * Sort the device list according to PCI BIOS. Nasty hack, but since some
350 * fool forgot to define the `correct' device order in the PCI BIOS specs
351 * and we want to be (possibly bug-to-bug ;-]) compatible with older kernels
352 * which used BIOS ordering, we are bound to do this...
353 */
354
355void __devinit pcibios_sort(void)
356{
357 LIST_HEAD(sorted_devices);
358 struct list_head *ln;
359 struct pci_dev *dev, *d;
360 int idx, found;
361 unsigned char bus, devfn;
362
363 DBG("PCI: Sorting device list...\n");
364 while (!list_empty(&pci_devices)) {
365 ln = pci_devices.next;
366 dev = pci_dev_g(ln);
367 idx = found = 0;
368 while (pci_bios_find_device(dev->vendor, dev->device, idx, &bus, &devfn) == PCIBIOS_SUCCESSFUL) {
369 idx++;
370 list_for_each(ln, &pci_devices) {
371 d = pci_dev_g(ln);
372 if (d->bus->number == bus && d->devfn == devfn) {
373 list_del(&d->global_list);
374 list_add_tail(&d->global_list, &sorted_devices);
375 if (d == dev)
376 found = 1;
377 break;
378 }
379 }
380 if (ln == &pci_devices) {
381 printk(KERN_WARNING "PCI: BIOS reporting unknown device %02x:%02x\n", bus, devfn);
382 /*
383 * We must not continue scanning as several buggy BIOSes
384 * return garbage after the last device. Grr.
385 */
386 break;
387 }
388 }
389 if (!found) {
390 printk(KERN_WARNING "PCI: Device %s not found by BIOS\n",
391 pci_name(dev));
392 list_del(&dev->global_list);
393 list_add_tail(&dev->global_list, &sorted_devices);
394 }
395 }
396 list_splice(&sorted_devices, &pci_devices);
397}
398
399/*
400 * BIOS Functions for IRQ Routing
401 */
402
403struct irq_routing_options {
404 u16 size;
405 struct irq_info *table;
406 u16 segment;
407} __attribute__((packed));
408
409struct irq_routing_table * __devinit pcibios_get_irq_routing_table(void)
410{
411 struct irq_routing_options opt;
412 struct irq_routing_table *rt = NULL;
413 int ret, map;
414 unsigned long page;
415
416 if (!pci_bios_present)
417 return NULL;
418 page = __get_free_page(GFP_KERNEL);
419 if (!page)
420 return NULL;
421 opt.table = (struct irq_info *) page;
422 opt.size = PAGE_SIZE;
423 opt.segment = __KERNEL_DS;
424
425 DBG("PCI: Fetching IRQ routing table... ");
426 __asm__("push %%es\n\t"
427 "push %%ds\n\t"
428 "pop %%es\n\t"
429 "lcall *(%%esi); cld\n\t"
430 "pop %%es\n\t"
431 "jc 1f\n\t"
432 "xor %%ah, %%ah\n"
433 "1:"
434 : "=a" (ret),
435 "=b" (map),
436 "=m" (opt)
437 : "0" (PCIBIOS_GET_ROUTING_OPTIONS),
438 "1" (0),
439 "D" ((long) &opt),
440 "S" (&pci_indirect),
441 "m" (opt)
442 : "memory");
443 DBG("OK ret=%d, size=%d, map=%x\n", ret, opt.size, map);
444 if (ret & 0xff00)
445 printk(KERN_ERR "PCI: Error %02x when fetching IRQ routing table.\n", (ret >> 8) & 0xff);
446 else if (opt.size) {
447 rt = kmalloc(sizeof(struct irq_routing_table) + opt.size, GFP_KERNEL);
448 if (rt) {
449 memset(rt, 0, sizeof(struct irq_routing_table));
450 rt->size = opt.size + sizeof(struct irq_routing_table);
451 rt->exclusive_irqs = map;
452 memcpy(rt->slots, (void *) page, opt.size);
453 printk(KERN_INFO "PCI: Using BIOS Interrupt Routing Table\n");
454 }
455 }
456 free_page(page);
457 return rt;
458}
459
460
461int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq)
462{
463 int ret;
464
465 __asm__("lcall *(%%esi); cld\n\t"
466 "jc 1f\n\t"
467 "xor %%ah, %%ah\n"
468 "1:"
469 : "=a" (ret)
470 : "0" (PCIBIOS_SET_PCI_HW_INT),
471 "b" ((dev->bus->number << 8) | dev->devfn),
472 "c" ((irq << 8) | (pin + 10)),
473 "S" (&pci_indirect));
474 return !(ret & 0xff00);
475}
476
477static int __init pci_pcbios_init(void)
478{
479 if ((pci_probe & PCI_PROBE_BIOS)
480 && ((raw_pci_ops = pci_find_bios()))) {
481 pci_probe |= PCI_BIOS_SORT;
482 pci_bios_present = 1;
483 }
484 return 0;
485}
486
487arch_initcall(pci_pcbios_init);
diff --git a/arch/i386/pci/pci.h b/arch/i386/pci/pci.h
new file mode 100644
index 00000000000..a8fc80ca69f
--- /dev/null
+++ b/arch/i386/pci/pci.h
@@ -0,0 +1,74 @@
1/*
2 * Low-Level PCI Access for i386 machines.
3 *
4 * (c) 1999 Martin Mares <mj@ucw.cz>
5 */
6
7#undef DEBUG
8
9#ifdef DEBUG
10#define DBG(x...) printk(x)
11#else
12#define DBG(x...)
13#endif
14
15#define PCI_PROBE_BIOS 0x0001
16#define PCI_PROBE_CONF1 0x0002
17#define PCI_PROBE_CONF2 0x0004
18#define PCI_PROBE_MMCONF 0x0008
19#define PCI_PROBE_MASK 0x000f
20
21#define PCI_NO_SORT 0x0100
22#define PCI_BIOS_SORT 0x0200
23#define PCI_NO_CHECKS 0x0400
24#define PCI_USE_PIRQ_MASK 0x0800
25#define PCI_ASSIGN_ROMS 0x1000
26#define PCI_BIOS_IRQ_SCAN 0x2000
27#define PCI_ASSIGN_ALL_BUSSES 0x4000
28
29extern unsigned int pci_probe;
30
31/* pci-i386.c */
32
33extern unsigned int pcibios_max_latency;
34
35void pcibios_resource_survey(void);
36int pcibios_enable_resources(struct pci_dev *, int);
37
38/* pci-pc.c */
39
40extern int pcibios_last_bus;
41extern struct pci_bus *pci_root_bus;
42extern struct pci_ops pci_root_ops;
43
44/* pci-irq.c */
45
46struct irq_info {
47 u8 bus, devfn; /* Bus, device and function */
48 struct {
49 u8 link; /* IRQ line ID, chipset dependent, 0=not routed */
50 u16 bitmap; /* Available IRQs */
51 } __attribute__((packed)) irq[4];
52 u8 slot; /* Slot number, 0=onboard */
53 u8 rfu;
54} __attribute__((packed));
55
56struct irq_routing_table {
57 u32 signature; /* PIRQ_SIGNATURE should be here */
58 u16 version; /* PIRQ_VERSION */
59 u16 size; /* Table size in bytes */
60 u8 rtr_bus, rtr_devfn; /* Where the interrupt router lies */
61 u16 exclusive_irqs; /* IRQs devoted exclusively to PCI usage */
62 u16 rtr_vendor, rtr_device; /* Vendor and device ID of interrupt router */
63 u32 miniport_data; /* Crap */
64 u8 rfu[11];
65 u8 checksum; /* Modulo 256 checksum must give zero */
66 struct irq_info slots[0];
67} __attribute__((packed));
68
69extern unsigned int pcibios_irq_mask;
70
71extern int pcibios_scanned;
72extern spinlock_t pci_config_lock;
73
74extern int (*pcibios_enable_irq)(struct pci_dev *dev);
diff --git a/arch/i386/pci/visws.c b/arch/i386/pci/visws.c
new file mode 100644
index 00000000000..6a924878443
--- /dev/null
+++ b/arch/i386/pci/visws.c
@@ -0,0 +1,110 @@
1/*
2 * Low-Level PCI Support for SGI Visual Workstation
3 *
4 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
5 */
6
7#include <linux/config.h>
8#include <linux/kernel.h>
9#include <linux/pci.h>
10#include <linux/init.h>
11
12#include "cobalt.h"
13#include "lithium.h"
14
15#include "pci.h"
16
17
18extern struct pci_raw_ops pci_direct_conf1;
19
20static int pci_visws_enable_irq(struct pci_dev *dev) { return 0; }
21
22int (*pcibios_enable_irq)(struct pci_dev *dev) = &pci_visws_enable_irq;
23
24void __init pcibios_penalize_isa_irq(int irq) {}
25
26
27unsigned int pci_bus0, pci_bus1;
28
29static inline u8 bridge_swizzle(u8 pin, u8 slot)
30{
31 return (((pin - 1) + slot) % 4) + 1;
32}
33
34static u8 __init visws_swizzle(struct pci_dev *dev, u8 *pinp)
35{
36 u8 pin = *pinp;
37
38 while (dev->bus->self) { /* Move up the chain of bridges. */
39 pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
40 dev = dev->bus->self;
41 }
42 *pinp = pin;
43
44 return PCI_SLOT(dev->devfn);
45}
46
47static int __init visws_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
48{
49 int irq, bus = dev->bus->number;
50
51 pin--;
52
53 /* Nothing useful at PIIX4 pin 1 */
54 if (bus == pci_bus0 && slot == 4 && pin == 0)
55 return -1;
56
57 /* PIIX4 USB is on Bus 0, Slot 4, Line 3 */
58 if (bus == pci_bus0 && slot == 4 && pin == 3) {
59 irq = CO_IRQ(CO_APIC_PIIX4_USB);
60 goto out;
61 }
62
63 /* First pin spread down 1 APIC entry per slot */
64 if (pin == 0) {
65 irq = CO_IRQ((bus == pci_bus0 ? CO_APIC_PCIB_BASE0 :
66 CO_APIC_PCIA_BASE0) + slot);
67 goto out;
68 }
69
70 /* lines 1,2,3 from any slot is shared in this twirly pattern */
71 if (bus == pci_bus1) {
72 /* lines 1-3 from devices 0 1 rotate over 2 apic entries */
73 irq = CO_IRQ(CO_APIC_PCIA_BASE123 + ((slot + (pin - 1)) % 2));
74 } else { /* bus == pci_bus0 */
75 /* lines 1-3 from devices 0-3 rotate over 3 apic entries */
76 if (slot == 0)
77 slot = 3; /* same pattern */
78 irq = CO_IRQ(CO_APIC_PCIA_BASE123 + ((3 - slot) + (pin - 1) % 3));
79 }
80out:
81 printk(KERN_DEBUG "PCI: Bus %d Slot %d Line %d -> IRQ %d\n", bus, slot, pin, irq);
82 return irq;
83}
84
85void __init pcibios_update_irq(struct pci_dev *dev, int irq)
86{
87 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
88}
89
90static int __init pcibios_init(void)
91{
92 /* The VISWS supports configuration access type 1 only */
93 pci_probe = (pci_probe | PCI_PROBE_CONF1) &
94 ~(PCI_PROBE_BIOS | PCI_PROBE_CONF2);
95
96 pci_bus0 = li_pcib_read16(LI_PCI_BUSNUM) & 0xff;
97 pci_bus1 = li_pcia_read16(LI_PCI_BUSNUM) & 0xff;
98
99 printk(KERN_INFO "PCI: Lithium bridge A bus: %u, "
100 "bridge B (PIIX4) bus: %u\n", pci_bus1, pci_bus0);
101
102 raw_pci_ops = &pci_direct_conf1;
103 pci_scan_bus(pci_bus0, &pci_root_ops, NULL);
104 pci_scan_bus(pci_bus1, &pci_root_ops, NULL);
105 pci_fixup_irqs(visws_swizzle, visws_map_irq);
106 pcibios_resource_survey();
107 return 0;
108}
109
110subsys_initcall(pcibios_init);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-18 05:23:06 -0500