[PATCH] paravirt: header and stubs for paravirtualisation

Create a paravirt.h header for all the critical operations which need to be
replaced with hypervisor calls, and include that instead of defining native
operations, when CONFIG_PARAVIRT.

This patch does the dumbest possible replacement of paravirtualized
instructions: calls through a "paravirt_ops" structure.  Currently these are
function implementations of native hardware: hypervisors will override the ops
structure with their own variants.

All the pv-ops functions are declared "fastcall" so that a specific
register-based ABI is used, to make inlining assember easier.

And:

+From: Andy Whitcroft <apw@shadowen.org>

The paravirt ops introduce a 'weak' attribute onto memory_setup().
Code ordering leads to the following warnings on x86:

    arch/i386/kernel/setup.c:651: warning: weak declaration of
                `memory_setup' after first use results in unspecified behavior

Move memory_setup() to avoid this.

Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
Signed-off-by: Chris Wright <chrisw@sous-sol.org>
Signed-off-by: Andi Kleen <ak@suse.de>
Cc: Jeremy Fitzhardinge <jeremy@goop.org>
Cc: Zachary Amsden <zach@vmware.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Andy Whitcroft <apw@shadowen.org>

1 files changed, 404 insertions, 0 deletions

diff --git a/arch/i386/kernel/paravirt.c b/arch/i386/kernel/paravirt.c
new file mode 100644
index 00000000000..478192cd4b9
--- /dev/null
+++ b/arch/i386/kernel/paravirt.c
@@ -0,0 +1,404 @@
+/*  Paravirtualization interfaces
+    Copyright (C) 2006 Rusty Russell IBM Corporation
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+#include <linux/errno.h>
+#include <linux/module.h>
+#include <linux/efi.h>
+#include <linux/bcd.h>
+
+#include <asm/bug.h>
+#include <asm/paravirt.h>
+#include <asm/desc.h>
+#include <asm/setup.h>
+#include <asm/arch_hooks.h>
+#include <asm/time.h>
+#include <asm/irq.h>
+#include <asm/delay.h>
+
+/* nop stub */
+static void native_nop(void)
+{
+}
+
+static void __init default_banner(void)
+{
+        printk(KERN_INFO "Booting paravirtualized kernel on %s\n",
+               paravirt_ops.name);
+}
+
+char *memory_setup(void)
+{
+        return paravirt_ops.memory_setup();
+}
+
+static fastcall unsigned long native_get_debugreg(int regno)
+{
+        unsigned long val = 0;  /* Damn you, gcc! */
+
+        switch (regno) {
+        case 0:
+                asm("movl %%db0, %0" :"=r" (val)); break;
+        case 1:
+                asm("movl %%db1, %0" :"=r" (val)); break;
+        case 2:
+                asm("movl %%db2, %0" :"=r" (val)); break;
+        case 3:
+                asm("movl %%db3, %0" :"=r" (val)); break;
+        case 6:
+                asm("movl %%db6, %0" :"=r" (val)); break;
+        case 7:
+                asm("movl %%db7, %0" :"=r" (val)); break;
+        default:
+                BUG();
+        }
+        return val;
+}
+
+static fastcall void native_set_debugreg(int regno, unsigned long value)
+{
+        switch (regno) {
+        case 0:
+                asm("movl %0,%%db0"     : /* no output */ :"r" (value));
+                break;
+        case 1:
+                asm("movl %0,%%db1"     : /* no output */ :"r" (value));
+                break;
+        case 2:
+                asm("movl %0,%%db2"     : /* no output */ :"r" (value));
+                break;
+        case 3:
+                asm("movl %0,%%db3"     : /* no output */ :"r" (value));
+                break;
+        case 6:
+                asm("movl %0,%%db6"     : /* no output */ :"r" (value));
+                break;
+        case 7:
+                asm("movl %0,%%db7"     : /* no output */ :"r" (value));
+                break;
+        default:
+                BUG();
+        }
+}
+
+void init_IRQ(void)
+{
+        paravirt_ops.init_IRQ();
+}
+
+static fastcall void native_clts(void)
+{
+        asm volatile ("clts");
+}
+
+static fastcall unsigned long native_read_cr0(void)
+{
+        unsigned long val;
+        asm volatile("movl %%cr0,%0\n\t" :"=r" (val));
+        return val;
+}
+
+static fastcall void native_write_cr0(unsigned long val)
+{
+        asm volatile("movl %0,%%cr0": :"r" (val));
+}
+
+static fastcall unsigned long native_read_cr2(void)
+{
+        unsigned long val;
+        asm volatile("movl %%cr2,%0\n\t" :"=r" (val));
+        return val;
+}
+
+static fastcall void native_write_cr2(unsigned long val)
+{
+        asm volatile("movl %0,%%cr2": :"r" (val));
+}
+
+static fastcall unsigned long native_read_cr3(void)
+{
+        unsigned long val;
+        asm volatile("movl %%cr3,%0\n\t" :"=r" (val));
+        return val;
+}
+
+static fastcall void native_write_cr3(unsigned long val)
+{
+        asm volatile("movl %0,%%cr3": :"r" (val));
+}
+
+static fastcall unsigned long native_read_cr4(void)
+{
+        unsigned long val;
+        asm volatile("movl %%cr4,%0\n\t" :"=r" (val));
+        return val;
+}
+
+static fastcall unsigned long native_read_cr4_safe(void)
+{
+        unsigned long val;
+        /* This could fault if %cr4 does not exist */
+        asm("1: movl %%cr4, %0          \n"
+                "2:                             \n"
+                ".section __ex_table,\"a\"      \n"
+                ".long 1b,2b                    \n"
+                ".previous                      \n"
+                : "=r" (val): "0" (0));
+        return val;
+}
+
+static fastcall void native_write_cr4(unsigned long val)
+{
+        asm volatile("movl %0,%%cr4": :"r" (val));
+}
+
+static fastcall unsigned long native_save_fl(void)
+{
+        unsigned long f;
+        asm volatile("pushfl ; popl %0":"=g" (f): /* no input */);
+        return f;
+}
+
+static fastcall void native_restore_fl(unsigned long f)
+{
+        asm volatile("pushl %0 ; popfl": /* no output */
+                             :"g" (f)
+                             :"memory", "cc");
+}
+
+static fastcall void native_irq_disable(void)
+{
+        asm volatile("cli": : :"memory");
+}
+
+static fastcall void native_irq_enable(void)
+{
+        asm volatile("sti": : :"memory");
+}
+
+static fastcall void native_safe_halt(void)
+{
+        asm volatile("sti; hlt": : :"memory");
+}
+
+static fastcall void native_halt(void)
+{
+        asm volatile("hlt": : :"memory");
+}
+
+static fastcall void native_wbinvd(void)
+{
+        asm volatile("wbinvd": : :"memory");
+}
+
+static fastcall unsigned long long native_read_msr(unsigned int msr, int *err)
+{
+        unsigned long long val;
+
+        asm volatile("2: rdmsr ; xorl %0,%0\n"
+                     "1:\n\t"
+                     ".section .fixup,\"ax\"\n\t"
+                     "3:  movl %3,%0 ; jmp 1b\n\t"
+                     ".previous\n\t"
+                     ".section __ex_table,\"a\"\n"
+                     "   .align 4\n\t"
+                     "   .long  2b,3b\n\t"
+                     ".previous"
+                     : "=r" (*err), "=A" (val)
+                     : "c" (msr), "i" (-EFAULT));
+
+        return val;
+}
+
+static fastcall int native_write_msr(unsigned int msr, unsigned long long val)
+{
+        int err;
+        asm volatile("2: wrmsr ; xorl %0,%0\n"
+                     "1:\n\t"
+                     ".section .fixup,\"ax\"\n\t"
+                     "3:  movl %4,%0 ; jmp 1b\n\t"
+                     ".previous\n\t"
+                     ".section __ex_table,\"a\"\n"
+                     "   .align 4\n\t"
+                     "   .long  2b,3b\n\t"
+                     ".previous"
+                     : "=a" (err)
+                     : "c" (msr), "0" ((u32)val), "d" ((u32)(val>>32)),
+                       "i" (-EFAULT));
+        return err;
+}
+
+static fastcall unsigned long long native_read_tsc(void)
+{
+        unsigned long long val;
+        asm volatile("rdtsc" : "=A" (val));
+        return val;
+}
+
+static fastcall unsigned long long native_read_pmc(void)
+{
+        unsigned long long val;
+        asm volatile("rdpmc" : "=A" (val));
+        return val;
+}
+
+static fastcall void native_load_tr_desc(void)
+{
+        asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8));
+}
+
+static fastcall void native_load_gdt(const struct Xgt_desc_struct *dtr)
+{
+        asm volatile("lgdt %0"::"m" (*dtr));
+}
+
+static fastcall void native_load_idt(const struct Xgt_desc_struct *dtr)
+{
+        asm volatile("lidt %0"::"m" (*dtr));
+}
+
+static fastcall void native_store_gdt(struct Xgt_desc_struct *dtr)
+{
+        asm ("sgdt %0":"=m" (*dtr));
+}
+
+static fastcall void native_store_idt(struct Xgt_desc_struct *dtr)
+{
+        asm ("sidt %0":"=m" (*dtr));
+}
+
+static fastcall unsigned long native_store_tr(void)
+{
+        unsigned long tr;
+        asm ("str %0":"=r" (tr));
+        return tr;
+}
+
+static fastcall void native_load_tls(struct thread_struct *t, unsigned int cpu)
+{
+#define C(i) get_cpu_gdt_table(cpu)[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i]
+        C(0); C(1); C(2);
+#undef C
+}
+
+static inline void native_write_dt_entry(void *dt, int entry, u32 entry_low, u32 entry_high)
+{
+        u32 *lp = (u32 *)((char *)dt + entry*8);
+        lp[0] = entry_low;
+        lp[1] = entry_high;
+}
+
+static fastcall void native_write_ldt_entry(void *dt, int entrynum, u32 low, u32 high)
+{
+        native_write_dt_entry(dt, entrynum, low, high);
+}
+
+static fastcall void native_write_gdt_entry(void *dt, int entrynum, u32 low, u32 high)
+{
+        native_write_dt_entry(dt, entrynum, low, high);
+}
+
+static fastcall void native_write_idt_entry(void *dt, int entrynum, u32 low, u32 high)
+{
+        native_write_dt_entry(dt, entrynum, low, high);
+}
+
+static fastcall void native_load_esp0(struct tss_struct *tss,
+                                      struct thread_struct *thread)
+{
+        tss->esp0 = thread->esp0;
+
+        /* This can only happen when SEP is enabled, no need to test "SEP"arately */
+        if (unlikely(tss->ss1 != thread->sysenter_cs)) {
+                tss->ss1 = thread->sysenter_cs;
+                wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
+        }
+}
+
+static fastcall void native_io_delay(void)
+{
+        asm volatile("outb %al,$0x80");
+}
+
+/* These are in entry.S */
+extern fastcall void native_iret(void);
+extern fastcall void native_irq_enable_sysexit(void);
+
+static int __init print_banner(void)
+{
+        paravirt_ops.banner();
+        return 0;
+}
+core_initcall(print_banner);
+
+struct paravirt_ops paravirt_ops = {
+        .name = "bare hardware",
+        .paravirt_enabled = 0,
+        .kernel_rpl = 0,
+
+        .banner = default_banner,
+        .arch_setup = native_nop,
+        .memory_setup = machine_specific_memory_setup,
+        .get_wallclock = native_get_wallclock,
+        .set_wallclock = native_set_wallclock,
+        .time_init = time_init_hook,
+        .init_IRQ = native_init_IRQ,
+
+        .cpuid = native_cpuid,
+        .get_debugreg = native_get_debugreg,
+        .set_debugreg = native_set_debugreg,
+        .clts = native_clts,
+        .read_cr0 = native_read_cr0,
+        .write_cr0 = native_write_cr0,
+        .read_cr2 = native_read_cr2,
+        .write_cr2 = native_write_cr2,
+        .read_cr3 = native_read_cr3,
+        .write_cr3 = native_write_cr3,
+        .read_cr4 = native_read_cr4,
+        .read_cr4_safe = native_read_cr4_safe,
+        .write_cr4 = native_write_cr4,
+        .save_fl = native_save_fl,
+        .restore_fl = native_restore_fl,
+        .irq_disable = native_irq_disable,
+        .irq_enable = native_irq_enable,
+        .safe_halt = native_safe_halt,
+        .halt = native_halt,
+        .wbinvd = native_wbinvd,
+        .read_msr = native_read_msr,
+        .write_msr = native_write_msr,
+        .read_tsc = native_read_tsc,
+        .read_pmc = native_read_pmc,
+        .load_tr_desc = native_load_tr_desc,
+        .set_ldt = native_set_ldt,
+        .load_gdt = native_load_gdt,
+        .load_idt = native_load_idt,
+        .store_gdt = native_store_gdt,
+        .store_idt = native_store_idt,
+        .store_tr = native_store_tr,
+        .load_tls = native_load_tls,
+        .write_ldt_entry = native_write_ldt_entry,
+        .write_gdt_entry = native_write_gdt_entry,
+        .write_idt_entry = native_write_idt_entry,
+        .load_esp0 = native_load_esp0,
+
+        .set_iopl_mask = native_set_iopl_mask,
+        .io_delay = native_io_delay,
+        .const_udelay = __const_udelay,
+
+        .irq_enable_sysexit = native_irq_enable_sysexit,
+        .iret = native_iret,
+};
+EXPORT_SYMBOL(paravirt_ops);