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authorMike Frysinger <vapier@gentoo.org>2009-10-20 13:30:58 -0400
committerMike Frysinger <vapier@gentoo.org>2009-12-15 00:14:31 -0500
commit60883e28b3dc6a85fca6f45f2306599523657a49 (patch)
treea3ec87a38813e78cd766904e2c061f785f9fe5ac /arch/blackfin
parent4ed250a563203efd98db05905839269e145785d5 (diff)
Blackfin: unify BF547/8/9 headers
No point in duplicating entire lists when we can simply tail into other parts for most of the MMRs. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin')
-rw-r--r--arch/blackfin/mach-bf548/include/mach/cdefBF548.h788
-rw-r--r--arch/blackfin/mach-bf548/include/mach/cdefBF549.h1533
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF548.h1203
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF549.h1582
4 files changed, 8 insertions, 5098 deletions
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF548.h b/arch/blackfin/mach-bf548/include/mach/cdefBF548.h
index df84180410c..3523e08f796 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF548.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF548.h
@@ -18,165 +18,8 @@
18/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */ 18/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
19#include "cdefBF54x_base.h" 19#include "cdefBF54x_base.h"
20 20
21/* The following are the #defines needed by ADSP-BF548 that are not in the common header */ 21/* The BF548 is like the BF547, but has additional CANs */
22 22#include "cdefBF547.h"
23/* Timer Registers */
24
25#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
26#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
27#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
28#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
29#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
30#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
31#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
32#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
33#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
34#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
35#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
36#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
37#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
38#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
39#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
40#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
41#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
42#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
43#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
44#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
45#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
46#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
47#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
48#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
49
50/* Timer Groubfin_read_() of 3 */
51
52#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1)
53#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)
54#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1)
55#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
56#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)
57#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
58
59/* SPORT0 Registers */
60
61#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
62#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
63#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
64#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
65#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
66#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
67#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
68#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
69#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
70#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
71#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
72#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
73#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
74#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
75#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
76#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
77#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
78#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
79#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
80#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
81#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
82#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
83#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
84#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
85#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
86#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
87#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
88#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
89#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
90#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
91#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
92#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
93#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
94#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
95#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
96#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
97#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
98#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
99#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
100#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
101#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
102#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
103#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
104#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
105
106/* EPPI0 Registers */
107
108#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS)
109#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)
110#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT)
111#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)
112#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY)
113#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)
114#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT)
115#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)
116#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY)
117#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)
118#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME)
119#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val)
120#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE)
121#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val)
122#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)
123#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
124#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL)
125#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val)
126#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL)
127#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
128#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL)
129#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
130#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB)
131#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
132#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF)
133#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
134#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP)
135#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val)
136
137/* UART2 Registers */
138
139#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL)
140#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val)
141#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH)
142#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val)
143#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL)
144#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val)
145#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR)
146#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val)
147#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR)
148#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val)
149#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR)
150#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val)
151#define bfin_read_UART2_MSR() bfin_read16(UART2_MSR)
152#define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val)
153#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR)
154#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val)
155#define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET)
156#define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val)
157#define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR)
158#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
159#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR)
160#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val)
161
162/* Two Wire Interface Registers (TWI1) */
163
164/* SPI2 Registers */
165
166#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL)
167#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val)
168#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG)
169#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val)
170#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT)
171#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val)
172#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR)
173#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val)
174#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR)
175#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val)
176#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD)
177#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val)
178#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW)
179#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val)
180 23
181/* CAN Controller 1 Config 1 Registers */ 24/* CAN Controller 1 Config 1 Registers */
182 25
@@ -923,631 +766,4 @@
923#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1) 766#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1)
924#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val) 767#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val)
925 768
926/* ATAPI Registers */
927
928#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL)
929#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val)
930#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS)
931#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
932#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR)
933#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
934#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF)
935#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
936#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF)
937#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
938#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK)
939#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
940#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS)
941#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
942#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN)
943#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
944#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS)
945#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
946#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE)
947#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
948#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE)
949#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
950#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT)
951#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
952#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT)
953#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
954#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
955#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
956#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
957#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
958#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0)
959#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
960#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0)
961#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
962#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1)
963#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
964#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0)
965#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
966#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1)
967#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
968#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2)
969#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
970#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0)
971#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
972#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1)
973#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
974#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2)
975#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
976#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3)
977#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
978
979/* SDH Registers */
980
981#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL)
982#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val)
983#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL)
984#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val)
985#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT)
986#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val)
987#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND)
988#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val)
989#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD)
990#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val)
991#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0)
992#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val)
993#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1)
994#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val)
995#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2)
996#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val)
997#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3)
998#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val)
999#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER)
1000#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
1001#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH)
1002#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val)
1003#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL)
1004#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val)
1005#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT)
1006#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val)
1007#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS)
1008#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val)
1009#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR)
1010#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
1011#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0)
1012#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val)
1013#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1)
1014#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val)
1015#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT)
1016#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val)
1017#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO)
1018#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val)
1019#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS)
1020#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val)
1021#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK)
1022#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val)
1023#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG)
1024#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val)
1025#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN)
1026#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
1027#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0)
1028#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val)
1029#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1)
1030#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val)
1031#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2)
1032#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val)
1033#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3)
1034#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val)
1035#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4)
1036#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val)
1037#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5)
1038#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val)
1039#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6)
1040#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val)
1041#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7)
1042#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val)
1043
1044/* HOST Port Registers */
1045
1046#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
1047#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
1048#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
1049#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
1050#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
1051#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
1052
1053/* USB Control Registers */
1054
1055#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
1056#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
1057#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
1058#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
1059#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
1060#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
1061#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
1062#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
1063#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
1064#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
1065#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
1066#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
1067#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
1068#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
1069#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
1070#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
1071#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
1072#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
1073#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
1074#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
1075#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
1076#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
1077#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
1078#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
1079#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
1080#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
1081
1082/* USB Packet Control Registers */
1083
1084#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
1085#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
1086#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
1087#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
1088#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
1089#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
1090#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
1091#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
1092#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
1093#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
1094#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
1095#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
1096#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
1097#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
1098#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
1099#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
1100#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
1101#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
1102#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
1103#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
1104#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
1105#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
1106#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
1107#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
1108#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
1109#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
1110
1111/* USB Endbfin_read_()oint FIFO Registers */
1112
1113#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
1114#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
1115#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
1116#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
1117#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
1118#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
1119#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
1120#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
1121#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
1122#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
1123#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
1124#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
1125#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
1126#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
1127#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
1128#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
1129
1130/* USB OTG Control Registers */
1131
1132#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
1133#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
1134#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
1135#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
1136#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
1137#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
1138
1139/* USB Phy Control Registers */
1140
1141#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
1142#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
1143#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
1144#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
1145#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
1146#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
1147#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
1148#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
1149#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
1150#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
1151
1152/* (APHY_CNTRL is for ADI usage only) */
1153
1154#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
1155#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
1156
1157/* (APHY_CALIB is for ADI usage only) */
1158
1159#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
1160#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
1161#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
1162#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
1163
1164/* (PHY_TEST is for ADI usage only) */
1165
1166#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
1167#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
1168#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
1169#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
1170#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
1171#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
1172
1173/* USB Endbfin_read_()oint 0 Control Registers */
1174
1175#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
1176#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
1177#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
1178#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
1179#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
1180#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
1181#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
1182#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
1183#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
1184#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
1185#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
1186#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
1187#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
1188#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
1189#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
1190#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
1191#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
1192#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
1193
1194/* USB Endbfin_read_()oint 1 Control Registers */
1195
1196#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
1197#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
1198#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
1199#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
1200#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
1201#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
1202#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
1203#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
1204#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
1205#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
1206#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
1207#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
1208#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
1209#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
1210#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
1211#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
1212#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
1213#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
1214#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
1215#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
1216
1217/* USB Endbfin_read_()oint 2 Control Registers */
1218
1219#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
1220#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
1221#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
1222#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
1223#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
1224#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
1225#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
1226#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
1227#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
1228#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
1229#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
1230#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
1231#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
1232#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
1233#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
1234#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
1235#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
1236#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
1237#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
1238#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
1239
1240/* USB Endbfin_read_()oint 3 Control Registers */
1241
1242#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
1243#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
1244#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
1245#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
1246#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
1247#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
1248#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
1249#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
1250#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
1251#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
1252#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
1253#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
1254#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
1255#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
1256#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
1257#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
1258#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
1259#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
1260#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
1261#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
1262
1263/* USB Endbfin_read_()oint 4 Control Registers */
1264
1265#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
1266#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
1267#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
1268#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
1269#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
1270#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
1271#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
1272#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
1273#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
1274#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
1275#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
1276#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
1277#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
1278#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
1279#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
1280#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
1281#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
1282#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
1283#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
1284#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
1285
1286/* USB Endbfin_read_()oint 5 Control Registers */
1287
1288#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
1289#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
1290#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
1291#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
1292#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
1293#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
1294#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
1295#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
1296#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
1297#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
1298#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
1299#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
1300#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
1301#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
1302#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
1303#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
1304#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
1305#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
1306#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
1307#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
1308
1309/* USB Endbfin_read_()oint 6 Control Registers */
1310
1311#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
1312#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
1313#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
1314#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
1315#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
1316#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
1317#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
1318#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
1319#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
1320#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
1321#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
1322#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
1323#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
1324#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
1325#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
1326#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
1327#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
1328#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
1329#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
1330#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
1331
1332/* USB Endbfin_read_()oint 7 Control Registers */
1333
1334#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
1335#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
1336#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
1337#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
1338#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
1339#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
1340#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
1341#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
1342#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
1343#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
1344#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
1345#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
1346#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
1347#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
1348#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
1349#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
1350#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
1351#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
1352#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
1353#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
1354#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
1355#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
1356#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
1357#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
1358
1359/* USB Channel 0 Config Registers */
1360
1361#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
1362#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
1363#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
1364#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
1365#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
1366#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
1367#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
1368#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
1369#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
1370#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
1371
1372/* USB Channel 1 Config Registers */
1373
1374#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
1375#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
1376#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
1377#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
1378#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
1379#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
1380#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
1381#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
1382#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
1383#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
1384
1385/* USB Channel 2 Config Registers */
1386
1387#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
1388#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
1389#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
1390#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
1391#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
1392#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
1393#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
1394#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
1395#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
1396#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
1397
1398/* USB Channel 3 Config Registers */
1399
1400#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
1401#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
1402#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
1403#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
1404#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
1405#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
1406#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
1407#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
1408#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
1409#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
1410
1411/* USB Channel 4 Config Registers */
1412
1413#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
1414#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
1415#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
1416#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
1417#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
1418#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
1419#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
1420#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
1421#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
1422#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
1423
1424/* USB Channel 5 Config Registers */
1425
1426#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
1427#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
1428#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
1429#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
1430#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
1431#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
1432#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
1433#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
1434#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
1435#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
1436
1437/* USB Channel 6 Config Registers */
1438
1439#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
1440#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
1441#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
1442#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
1443#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
1444#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
1445#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
1446#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
1447#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
1448#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
1449
1450/* USB Channel 7 Config Registers */
1451
1452#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
1453#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
1454#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
1455#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
1456#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
1457#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
1458#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
1459#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
1460#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
1461#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
1462
1463/* Keybfin_read_()ad Registers */
1464
1465#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL)
1466#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val)
1467#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE)
1468#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val)
1469#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL)
1470#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val)
1471#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL)
1472#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val)
1473#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT)
1474#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val)
1475#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL)
1476#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val)
1477
1478/* Pixel Combfin_read_()ositor (PIXC) Registers */
1479
1480#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL)
1481#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val)
1482#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL)
1483#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val)
1484#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF)
1485#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val)
1486#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART)
1487#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val)
1488#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND)
1489#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val)
1490#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART)
1491#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val)
1492#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND)
1493#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val)
1494#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP)
1495#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val)
1496#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART)
1497#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val)
1498#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND)
1499#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val)
1500#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART)
1501#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val)
1502#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND)
1503#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val)
1504#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP)
1505#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val)
1506#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT)
1507#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val)
1508#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON)
1509#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val)
1510#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON)
1511#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val)
1512#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON)
1513#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val)
1514#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS)
1515#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val)
1516#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC)
1517#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val)
1518
1519/* Handshake MDMA 0 Registers */
1520
1521#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
1522#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
1523#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
1524#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
1525#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
1526#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
1527#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
1528#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
1529#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
1530#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
1531#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
1532#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
1533#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
1534#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
1535
1536/* Handshake MDMA 1 Registers */
1537
1538#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
1539#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
1540#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
1541#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
1542#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
1543#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
1544#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
1545#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
1546#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
1547#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
1548#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
1549#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
1550#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
1551#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
1552
1553#endif /* _CDEF_BF548_H */ 769#endif /* _CDEF_BF548_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF549.h b/arch/blackfin/mach-bf548/include/mach/cdefBF549.h
index 34c84c7fb25..80201ed41f8 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF549.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF549.h
@@ -18,165 +18,8 @@
18/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */ 18/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
19#include "cdefBF54x_base.h" 19#include "cdefBF54x_base.h"
20 20
21/* The following are the #defines needed by ADSP-BF549 that are not in the common header */ 21/* The BF549 is like the BF544, but has MXVR */
22 22#include "cdefBF547.h"
23/* Timer Registers */
24
25#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
26#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
27#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
28#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
29#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
30#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
31#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
32#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
33#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
34#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
35#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
36#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
37#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
38#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
39#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
40#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
41#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
42#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
43#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
44#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
45#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
46#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
47#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
48#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
49
50/* Timer Groubfin_read_() of 3 */
51
52#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1)
53#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)
54#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1)
55#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
56#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)
57#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
58
59/* SPORT0 Registers */
60
61#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
62#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
63#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
64#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
65#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
66#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
67#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
68#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
69#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
70#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
71#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
72#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
73#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
74#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
75#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
76#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
77#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
78#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
79#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
80#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
81#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
82#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
83#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
84#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
85#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
86#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
87#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
88#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
89#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
90#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
91#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
92#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
93#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
94#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
95#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
96#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
97#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
98#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
99#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
100#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
101#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
102#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
103#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
104#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
105
106/* EPPI0 Registers */
107
108#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS)
109#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)
110#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT)
111#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)
112#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY)
113#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)
114#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT)
115#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)
116#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY)
117#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)
118#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME)
119#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val)
120#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE)
121#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val)
122#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)
123#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
124#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL)
125#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val)
126#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL)
127#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
128#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL)
129#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
130#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB)
131#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
132#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF)
133#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
134#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP)
135#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val)
136
137/* UART2 Registers */
138
139#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL)
140#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val)
141#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH)
142#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val)
143#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL)
144#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val)
145#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR)
146#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val)
147#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR)
148#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val)
149#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR)
150#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val)
151#define bfin_read_UART2_MSR() bfin_read16(UART2_MSR)
152#define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val)
153#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR)
154#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val)
155#define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET)
156#define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val)
157#define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR)
158#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
159#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR)
160#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val)
161
162/* Two Wire Interface Registers (TWI1) */
163
164/* SPI2 Registers */
165
166#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL)
167#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val)
168#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG)
169#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val)
170#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT)
171#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val)
172#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR)
173#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val)
174#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR)
175#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val)
176#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD)
177#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val)
178#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW)
179#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val)
180 23
181/* MXVR Registers */ 24/* MXVR Registers */
182 25
@@ -464,1376 +307,4 @@
464#define bfin_read_MXVR_SCLK_CNT() bfin_read16(MXVR_SCLK_CNT) 307#define bfin_read_MXVR_SCLK_CNT() bfin_read16(MXVR_SCLK_CNT)
465#define bfin_write_MXVR_SCLK_CNT(val) bfin_write16(MXVR_SCLK_CNT, val) 308#define bfin_write_MXVR_SCLK_CNT(val) bfin_write16(MXVR_SCLK_CNT, val)
466 309
467/* CAN Controller 1 Config 1 Registers */
468
469#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1)
470#define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val)
471#define bfin_read_CAN1_MD1() bfin_read16(CAN1_MD1)
472#define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val)
473#define bfin_read_CAN1_TRS1() bfin_read16(CAN1_TRS1)
474#define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val)
475#define bfin_read_CAN1_TRR1() bfin_read16(CAN1_TRR1)
476#define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val)
477#define bfin_read_CAN1_TA1() bfin_read16(CAN1_TA1)
478#define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val)
479#define bfin_read_CAN1_AA1() bfin_read16(CAN1_AA1)
480#define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val)
481#define bfin_read_CAN1_RMP1() bfin_read16(CAN1_RMP1)
482#define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val)
483#define bfin_read_CAN1_RML1() bfin_read16(CAN1_RML1)
484#define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val)
485#define bfin_read_CAN1_MBTIF1() bfin_read16(CAN1_MBTIF1)
486#define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val)
487#define bfin_read_CAN1_MBRIF1() bfin_read16(CAN1_MBRIF1)
488#define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val)
489#define bfin_read_CAN1_MBIM1() bfin_read16(CAN1_MBIM1)
490#define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val)
491#define bfin_read_CAN1_RFH1() bfin_read16(CAN1_RFH1)
492#define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val)
493#define bfin_read_CAN1_OPSS1() bfin_read16(CAN1_OPSS1)
494#define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val)
495
496/* CAN Controller 1 Config 2 Registers */
497
498#define bfin_read_CAN1_MC2() bfin_read16(CAN1_MC2)
499#define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val)
500#define bfin_read_CAN1_MD2() bfin_read16(CAN1_MD2)
501#define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val)
502#define bfin_read_CAN1_TRS2() bfin_read16(CAN1_TRS2)
503#define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val)
504#define bfin_read_CAN1_TRR2() bfin_read16(CAN1_TRR2)
505#define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val)
506#define bfin_read_CAN1_TA2() bfin_read16(CAN1_TA2)
507#define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val)
508#define bfin_read_CAN1_AA2() bfin_read16(CAN1_AA2)
509#define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val)
510#define bfin_read_CAN1_RMP2() bfin_read16(CAN1_RMP2)
511#define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val)
512#define bfin_read_CAN1_RML2() bfin_read16(CAN1_RML2)
513#define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val)
514#define bfin_read_CAN1_MBTIF2() bfin_read16(CAN1_MBTIF2)
515#define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val)
516#define bfin_read_CAN1_MBRIF2() bfin_read16(CAN1_MBRIF2)
517#define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val)
518#define bfin_read_CAN1_MBIM2() bfin_read16(CAN1_MBIM2)
519#define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val)
520#define bfin_read_CAN1_RFH2() bfin_read16(CAN1_RFH2)
521#define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val)
522#define bfin_read_CAN1_OPSS2() bfin_read16(CAN1_OPSS2)
523#define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val)
524
525/* CAN Controller 1 Clock/Interrubfin_read_()t/Counter Registers */
526
527#define bfin_read_CAN1_CLOCK() bfin_read16(CAN1_CLOCK)
528#define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val)
529#define bfin_read_CAN1_TIMING() bfin_read16(CAN1_TIMING)
530#define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val)
531#define bfin_read_CAN1_DEBUG() bfin_read16(CAN1_DEBUG)
532#define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val)
533#define bfin_read_CAN1_STATUS() bfin_read16(CAN1_STATUS)
534#define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val)
535#define bfin_read_CAN1_CEC() bfin_read16(CAN1_CEC)
536#define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val)
537#define bfin_read_CAN1_GIS() bfin_read16(CAN1_GIS)
538#define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val)
539#define bfin_read_CAN1_GIM() bfin_read16(CAN1_GIM)
540#define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val)
541#define bfin_read_CAN1_GIF() bfin_read16(CAN1_GIF)
542#define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val)
543#define bfin_read_CAN1_CONTROL() bfin_read16(CAN1_CONTROL)
544#define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val)
545#define bfin_read_CAN1_INTR() bfin_read16(CAN1_INTR)
546#define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val)
547#define bfin_read_CAN1_MBTD() bfin_read16(CAN1_MBTD)
548#define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val)
549#define bfin_read_CAN1_EWR() bfin_read16(CAN1_EWR)
550#define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val)
551#define bfin_read_CAN1_ESR() bfin_read16(CAN1_ESR)
552#define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val)
553#define bfin_read_CAN1_UCCNT() bfin_read16(CAN1_UCCNT)
554#define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val)
555#define bfin_read_CAN1_UCRC() bfin_read16(CAN1_UCRC)
556#define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val)
557#define bfin_read_CAN1_UCCNF() bfin_read16(CAN1_UCCNF)
558#define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val)
559
560/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
561
562#define bfin_read_CAN1_AM00L() bfin_read16(CAN1_AM00L)
563#define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val)
564#define bfin_read_CAN1_AM00H() bfin_read16(CAN1_AM00H)
565#define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val)
566#define bfin_read_CAN1_AM01L() bfin_read16(CAN1_AM01L)
567#define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val)
568#define bfin_read_CAN1_AM01H() bfin_read16(CAN1_AM01H)
569#define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val)
570#define bfin_read_CAN1_AM02L() bfin_read16(CAN1_AM02L)
571#define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val)
572#define bfin_read_CAN1_AM02H() bfin_read16(CAN1_AM02H)
573#define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val)
574#define bfin_read_CAN1_AM03L() bfin_read16(CAN1_AM03L)
575#define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val)
576#define bfin_read_CAN1_AM03H() bfin_read16(CAN1_AM03H)
577#define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val)
578#define bfin_read_CAN1_AM04L() bfin_read16(CAN1_AM04L)
579#define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val)
580#define bfin_read_CAN1_AM04H() bfin_read16(CAN1_AM04H)
581#define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val)
582#define bfin_read_CAN1_AM05L() bfin_read16(CAN1_AM05L)
583#define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val)
584#define bfin_read_CAN1_AM05H() bfin_read16(CAN1_AM05H)
585#define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val)
586#define bfin_read_CAN1_AM06L() bfin_read16(CAN1_AM06L)
587#define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val)
588#define bfin_read_CAN1_AM06H() bfin_read16(CAN1_AM06H)
589#define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val)
590#define bfin_read_CAN1_AM07L() bfin_read16(CAN1_AM07L)
591#define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val)
592#define bfin_read_CAN1_AM07H() bfin_read16(CAN1_AM07H)
593#define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val)
594#define bfin_read_CAN1_AM08L() bfin_read16(CAN1_AM08L)
595#define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val)
596#define bfin_read_CAN1_AM08H() bfin_read16(CAN1_AM08H)
597#define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val)
598#define bfin_read_CAN1_AM09L() bfin_read16(CAN1_AM09L)
599#define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val)
600#define bfin_read_CAN1_AM09H() bfin_read16(CAN1_AM09H)
601#define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val)
602#define bfin_read_CAN1_AM10L() bfin_read16(CAN1_AM10L)
603#define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val)
604#define bfin_read_CAN1_AM10H() bfin_read16(CAN1_AM10H)
605#define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val)
606#define bfin_read_CAN1_AM11L() bfin_read16(CAN1_AM11L)
607#define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val)
608#define bfin_read_CAN1_AM11H() bfin_read16(CAN1_AM11H)
609#define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val)
610#define bfin_read_CAN1_AM12L() bfin_read16(CAN1_AM12L)
611#define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val)
612#define bfin_read_CAN1_AM12H() bfin_read16(CAN1_AM12H)
613#define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val)
614#define bfin_read_CAN1_AM13L() bfin_read16(CAN1_AM13L)
615#define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val)
616#define bfin_read_CAN1_AM13H() bfin_read16(CAN1_AM13H)
617#define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val)
618#define bfin_read_CAN1_AM14L() bfin_read16(CAN1_AM14L)
619#define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val)
620#define bfin_read_CAN1_AM14H() bfin_read16(CAN1_AM14H)
621#define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val)
622#define bfin_read_CAN1_AM15L() bfin_read16(CAN1_AM15L)
623#define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val)
624#define bfin_read_CAN1_AM15H() bfin_read16(CAN1_AM15H)
625#define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val)
626
627/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
628
629#define bfin_read_CAN1_AM16L() bfin_read16(CAN1_AM16L)
630#define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val)
631#define bfin_read_CAN1_AM16H() bfin_read16(CAN1_AM16H)
632#define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val)
633#define bfin_read_CAN1_AM17L() bfin_read16(CAN1_AM17L)
634#define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val)
635#define bfin_read_CAN1_AM17H() bfin_read16(CAN1_AM17H)
636#define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val)
637#define bfin_read_CAN1_AM18L() bfin_read16(CAN1_AM18L)
638#define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val)
639#define bfin_read_CAN1_AM18H() bfin_read16(CAN1_AM18H)
640#define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val)
641#define bfin_read_CAN1_AM19L() bfin_read16(CAN1_AM19L)
642#define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val)
643#define bfin_read_CAN1_AM19H() bfin_read16(CAN1_AM19H)
644#define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val)
645#define bfin_read_CAN1_AM20L() bfin_read16(CAN1_AM20L)
646#define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val)
647#define bfin_read_CAN1_AM20H() bfin_read16(CAN1_AM20H)
648#define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val)
649#define bfin_read_CAN1_AM21L() bfin_read16(CAN1_AM21L)
650#define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val)
651#define bfin_read_CAN1_AM21H() bfin_read16(CAN1_AM21H)
652#define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val)
653#define bfin_read_CAN1_AM22L() bfin_read16(CAN1_AM22L)
654#define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val)
655#define bfin_read_CAN1_AM22H() bfin_read16(CAN1_AM22H)
656#define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val)
657#define bfin_read_CAN1_AM23L() bfin_read16(CAN1_AM23L)
658#define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val)
659#define bfin_read_CAN1_AM23H() bfin_read16(CAN1_AM23H)
660#define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val)
661#define bfin_read_CAN1_AM24L() bfin_read16(CAN1_AM24L)
662#define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val)
663#define bfin_read_CAN1_AM24H() bfin_read16(CAN1_AM24H)
664#define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val)
665#define bfin_read_CAN1_AM25L() bfin_read16(CAN1_AM25L)
666#define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val)
667#define bfin_read_CAN1_AM25H() bfin_read16(CAN1_AM25H)
668#define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val)
669#define bfin_read_CAN1_AM26L() bfin_read16(CAN1_AM26L)
670#define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val)
671#define bfin_read_CAN1_AM26H() bfin_read16(CAN1_AM26H)
672#define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val)
673#define bfin_read_CAN1_AM27L() bfin_read16(CAN1_AM27L)
674#define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val)
675#define bfin_read_CAN1_AM27H() bfin_read16(CAN1_AM27H)
676#define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val)
677#define bfin_read_CAN1_AM28L() bfin_read16(CAN1_AM28L)
678#define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val)
679#define bfin_read_CAN1_AM28H() bfin_read16(CAN1_AM28H)
680#define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val)
681#define bfin_read_CAN1_AM29L() bfin_read16(CAN1_AM29L)
682#define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val)
683#define bfin_read_CAN1_AM29H() bfin_read16(CAN1_AM29H)
684#define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val)
685#define bfin_read_CAN1_AM30L() bfin_read16(CAN1_AM30L)
686#define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val)
687#define bfin_read_CAN1_AM30H() bfin_read16(CAN1_AM30H)
688#define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val)
689#define bfin_read_CAN1_AM31L() bfin_read16(CAN1_AM31L)
690#define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val)
691#define bfin_read_CAN1_AM31H() bfin_read16(CAN1_AM31H)
692#define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val)
693
694/* CAN Controller 1 Mailbox Data Registers */
695
696#define bfin_read_CAN1_MB00_DATA0() bfin_read16(CAN1_MB00_DATA0)
697#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
698#define bfin_read_CAN1_MB00_DATA1() bfin_read16(CAN1_MB00_DATA1)
699#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
700#define bfin_read_CAN1_MB00_DATA2() bfin_read16(CAN1_MB00_DATA2)
701#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
702#define bfin_read_CAN1_MB00_DATA3() bfin_read16(CAN1_MB00_DATA3)
703#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
704#define bfin_read_CAN1_MB00_LENGTH() bfin_read16(CAN1_MB00_LENGTH)
705#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
706#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP)
707#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
708#define bfin_read_CAN1_MB00_ID0() bfin_read16(CAN1_MB00_ID0)
709#define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val)
710#define bfin_read_CAN1_MB00_ID1() bfin_read16(CAN1_MB00_ID1)
711#define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val)
712#define bfin_read_CAN1_MB01_DATA0() bfin_read16(CAN1_MB01_DATA0)
713#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
714#define bfin_read_CAN1_MB01_DATA1() bfin_read16(CAN1_MB01_DATA1)
715#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
716#define bfin_read_CAN1_MB01_DATA2() bfin_read16(CAN1_MB01_DATA2)
717#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
718#define bfin_read_CAN1_MB01_DATA3() bfin_read16(CAN1_MB01_DATA3)
719#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
720#define bfin_read_CAN1_MB01_LENGTH() bfin_read16(CAN1_MB01_LENGTH)
721#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
722#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP)
723#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
724#define bfin_read_CAN1_MB01_ID0() bfin_read16(CAN1_MB01_ID0)
725#define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val)
726#define bfin_read_CAN1_MB01_ID1() bfin_read16(CAN1_MB01_ID1)
727#define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val)
728#define bfin_read_CAN1_MB02_DATA0() bfin_read16(CAN1_MB02_DATA0)
729#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
730#define bfin_read_CAN1_MB02_DATA1() bfin_read16(CAN1_MB02_DATA1)
731#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
732#define bfin_read_CAN1_MB02_DATA2() bfin_read16(CAN1_MB02_DATA2)
733#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
734#define bfin_read_CAN1_MB02_DATA3() bfin_read16(CAN1_MB02_DATA3)
735#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
736#define bfin_read_CAN1_MB02_LENGTH() bfin_read16(CAN1_MB02_LENGTH)
737#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
738#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP)
739#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
740#define bfin_read_CAN1_MB02_ID0() bfin_read16(CAN1_MB02_ID0)
741#define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val)
742#define bfin_read_CAN1_MB02_ID1() bfin_read16(CAN1_MB02_ID1)
743#define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val)
744#define bfin_read_CAN1_MB03_DATA0() bfin_read16(CAN1_MB03_DATA0)
745#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
746#define bfin_read_CAN1_MB03_DATA1() bfin_read16(CAN1_MB03_DATA1)
747#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
748#define bfin_read_CAN1_MB03_DATA2() bfin_read16(CAN1_MB03_DATA2)
749#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
750#define bfin_read_CAN1_MB03_DATA3() bfin_read16(CAN1_MB03_DATA3)
751#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
752#define bfin_read_CAN1_MB03_LENGTH() bfin_read16(CAN1_MB03_LENGTH)
753#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
754#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP)
755#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
756#define bfin_read_CAN1_MB03_ID0() bfin_read16(CAN1_MB03_ID0)
757#define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val)
758#define bfin_read_CAN1_MB03_ID1() bfin_read16(CAN1_MB03_ID1)
759#define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val)
760#define bfin_read_CAN1_MB04_DATA0() bfin_read16(CAN1_MB04_DATA0)
761#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
762#define bfin_read_CAN1_MB04_DATA1() bfin_read16(CAN1_MB04_DATA1)
763#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
764#define bfin_read_CAN1_MB04_DATA2() bfin_read16(CAN1_MB04_DATA2)
765#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
766#define bfin_read_CAN1_MB04_DATA3() bfin_read16(CAN1_MB04_DATA3)
767#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
768#define bfin_read_CAN1_MB04_LENGTH() bfin_read16(CAN1_MB04_LENGTH)
769#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
770#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP)
771#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
772#define bfin_read_CAN1_MB04_ID0() bfin_read16(CAN1_MB04_ID0)
773#define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val)
774#define bfin_read_CAN1_MB04_ID1() bfin_read16(CAN1_MB04_ID1)
775#define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val)
776#define bfin_read_CAN1_MB05_DATA0() bfin_read16(CAN1_MB05_DATA0)
777#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
778#define bfin_read_CAN1_MB05_DATA1() bfin_read16(CAN1_MB05_DATA1)
779#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
780#define bfin_read_CAN1_MB05_DATA2() bfin_read16(CAN1_MB05_DATA2)
781#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
782#define bfin_read_CAN1_MB05_DATA3() bfin_read16(CAN1_MB05_DATA3)
783#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
784#define bfin_read_CAN1_MB05_LENGTH() bfin_read16(CAN1_MB05_LENGTH)
785#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
786#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP)
787#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
788#define bfin_read_CAN1_MB05_ID0() bfin_read16(CAN1_MB05_ID0)
789#define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val)
790#define bfin_read_CAN1_MB05_ID1() bfin_read16(CAN1_MB05_ID1)
791#define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val)
792#define bfin_read_CAN1_MB06_DATA0() bfin_read16(CAN1_MB06_DATA0)
793#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
794#define bfin_read_CAN1_MB06_DATA1() bfin_read16(CAN1_MB06_DATA1)
795#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
796#define bfin_read_CAN1_MB06_DATA2() bfin_read16(CAN1_MB06_DATA2)
797#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
798#define bfin_read_CAN1_MB06_DATA3() bfin_read16(CAN1_MB06_DATA3)
799#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
800#define bfin_read_CAN1_MB06_LENGTH() bfin_read16(CAN1_MB06_LENGTH)
801#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
802#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP)
803#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
804#define bfin_read_CAN1_MB06_ID0() bfin_read16(CAN1_MB06_ID0)
805#define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val)
806#define bfin_read_CAN1_MB06_ID1() bfin_read16(CAN1_MB06_ID1)
807#define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val)
808#define bfin_read_CAN1_MB07_DATA0() bfin_read16(CAN1_MB07_DATA0)
809#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
810#define bfin_read_CAN1_MB07_DATA1() bfin_read16(CAN1_MB07_DATA1)
811#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
812#define bfin_read_CAN1_MB07_DATA2() bfin_read16(CAN1_MB07_DATA2)
813#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
814#define bfin_read_CAN1_MB07_DATA3() bfin_read16(CAN1_MB07_DATA3)
815#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
816#define bfin_read_CAN1_MB07_LENGTH() bfin_read16(CAN1_MB07_LENGTH)
817#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
818#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP)
819#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
820#define bfin_read_CAN1_MB07_ID0() bfin_read16(CAN1_MB07_ID0)
821#define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val)
822#define bfin_read_CAN1_MB07_ID1() bfin_read16(CAN1_MB07_ID1)
823#define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val)
824#define bfin_read_CAN1_MB08_DATA0() bfin_read16(CAN1_MB08_DATA0)
825#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
826#define bfin_read_CAN1_MB08_DATA1() bfin_read16(CAN1_MB08_DATA1)
827#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
828#define bfin_read_CAN1_MB08_DATA2() bfin_read16(CAN1_MB08_DATA2)
829#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
830#define bfin_read_CAN1_MB08_DATA3() bfin_read16(CAN1_MB08_DATA3)
831#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
832#define bfin_read_CAN1_MB08_LENGTH() bfin_read16(CAN1_MB08_LENGTH)
833#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
834#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP)
835#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
836#define bfin_read_CAN1_MB08_ID0() bfin_read16(CAN1_MB08_ID0)
837#define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val)
838#define bfin_read_CAN1_MB08_ID1() bfin_read16(CAN1_MB08_ID1)
839#define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val)
840#define bfin_read_CAN1_MB09_DATA0() bfin_read16(CAN1_MB09_DATA0)
841#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
842#define bfin_read_CAN1_MB09_DATA1() bfin_read16(CAN1_MB09_DATA1)
843#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
844#define bfin_read_CAN1_MB09_DATA2() bfin_read16(CAN1_MB09_DATA2)
845#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
846#define bfin_read_CAN1_MB09_DATA3() bfin_read16(CAN1_MB09_DATA3)
847#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
848#define bfin_read_CAN1_MB09_LENGTH() bfin_read16(CAN1_MB09_LENGTH)
849#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
850#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP)
851#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
852#define bfin_read_CAN1_MB09_ID0() bfin_read16(CAN1_MB09_ID0)
853#define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val)
854#define bfin_read_CAN1_MB09_ID1() bfin_read16(CAN1_MB09_ID1)
855#define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val)
856#define bfin_read_CAN1_MB10_DATA0() bfin_read16(CAN1_MB10_DATA0)
857#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
858#define bfin_read_CAN1_MB10_DATA1() bfin_read16(CAN1_MB10_DATA1)
859#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
860#define bfin_read_CAN1_MB10_DATA2() bfin_read16(CAN1_MB10_DATA2)
861#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
862#define bfin_read_CAN1_MB10_DATA3() bfin_read16(CAN1_MB10_DATA3)
863#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
864#define bfin_read_CAN1_MB10_LENGTH() bfin_read16(CAN1_MB10_LENGTH)
865#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
866#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP)
867#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
868#define bfin_read_CAN1_MB10_ID0() bfin_read16(CAN1_MB10_ID0)
869#define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val)
870#define bfin_read_CAN1_MB10_ID1() bfin_read16(CAN1_MB10_ID1)
871#define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val)
872#define bfin_read_CAN1_MB11_DATA0() bfin_read16(CAN1_MB11_DATA0)
873#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
874#define bfin_read_CAN1_MB11_DATA1() bfin_read16(CAN1_MB11_DATA1)
875#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
876#define bfin_read_CAN1_MB11_DATA2() bfin_read16(CAN1_MB11_DATA2)
877#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
878#define bfin_read_CAN1_MB11_DATA3() bfin_read16(CAN1_MB11_DATA3)
879#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
880#define bfin_read_CAN1_MB11_LENGTH() bfin_read16(CAN1_MB11_LENGTH)
881#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
882#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP)
883#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
884#define bfin_read_CAN1_MB11_ID0() bfin_read16(CAN1_MB11_ID0)
885#define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val)
886#define bfin_read_CAN1_MB11_ID1() bfin_read16(CAN1_MB11_ID1)
887#define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val)
888#define bfin_read_CAN1_MB12_DATA0() bfin_read16(CAN1_MB12_DATA0)
889#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
890#define bfin_read_CAN1_MB12_DATA1() bfin_read16(CAN1_MB12_DATA1)
891#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
892#define bfin_read_CAN1_MB12_DATA2() bfin_read16(CAN1_MB12_DATA2)
893#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
894#define bfin_read_CAN1_MB12_DATA3() bfin_read16(CAN1_MB12_DATA3)
895#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
896#define bfin_read_CAN1_MB12_LENGTH() bfin_read16(CAN1_MB12_LENGTH)
897#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
898#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP)
899#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
900#define bfin_read_CAN1_MB12_ID0() bfin_read16(CAN1_MB12_ID0)
901#define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val)
902#define bfin_read_CAN1_MB12_ID1() bfin_read16(CAN1_MB12_ID1)
903#define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val)
904#define bfin_read_CAN1_MB13_DATA0() bfin_read16(CAN1_MB13_DATA0)
905#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
906#define bfin_read_CAN1_MB13_DATA1() bfin_read16(CAN1_MB13_DATA1)
907#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
908#define bfin_read_CAN1_MB13_DATA2() bfin_read16(CAN1_MB13_DATA2)
909#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
910#define bfin_read_CAN1_MB13_DATA3() bfin_read16(CAN1_MB13_DATA3)
911#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
912#define bfin_read_CAN1_MB13_LENGTH() bfin_read16(CAN1_MB13_LENGTH)
913#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
914#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP)
915#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
916#define bfin_read_CAN1_MB13_ID0() bfin_read16(CAN1_MB13_ID0)
917#define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val)
918#define bfin_read_CAN1_MB13_ID1() bfin_read16(CAN1_MB13_ID1)
919#define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val)
920#define bfin_read_CAN1_MB14_DATA0() bfin_read16(CAN1_MB14_DATA0)
921#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
922#define bfin_read_CAN1_MB14_DATA1() bfin_read16(CAN1_MB14_DATA1)
923#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
924#define bfin_read_CAN1_MB14_DATA2() bfin_read16(CAN1_MB14_DATA2)
925#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
926#define bfin_read_CAN1_MB14_DATA3() bfin_read16(CAN1_MB14_DATA3)
927#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
928#define bfin_read_CAN1_MB14_LENGTH() bfin_read16(CAN1_MB14_LENGTH)
929#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
930#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP)
931#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
932#define bfin_read_CAN1_MB14_ID0() bfin_read16(CAN1_MB14_ID0)
933#define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val)
934#define bfin_read_CAN1_MB14_ID1() bfin_read16(CAN1_MB14_ID1)
935#define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val)
936#define bfin_read_CAN1_MB15_DATA0() bfin_read16(CAN1_MB15_DATA0)
937#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
938#define bfin_read_CAN1_MB15_DATA1() bfin_read16(CAN1_MB15_DATA1)
939#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
940#define bfin_read_CAN1_MB15_DATA2() bfin_read16(CAN1_MB15_DATA2)
941#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
942#define bfin_read_CAN1_MB15_DATA3() bfin_read16(CAN1_MB15_DATA3)
943#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
944#define bfin_read_CAN1_MB15_LENGTH() bfin_read16(CAN1_MB15_LENGTH)
945#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
946#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP)
947#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
948#define bfin_read_CAN1_MB15_ID0() bfin_read16(CAN1_MB15_ID0)
949#define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val)
950#define bfin_read_CAN1_MB15_ID1() bfin_read16(CAN1_MB15_ID1)
951#define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val)
952
953/* CAN Controller 1 Mailbox Data Registers */
954
955#define bfin_read_CAN1_MB16_DATA0() bfin_read16(CAN1_MB16_DATA0)
956#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
957#define bfin_read_CAN1_MB16_DATA1() bfin_read16(CAN1_MB16_DATA1)
958#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
959#define bfin_read_CAN1_MB16_DATA2() bfin_read16(CAN1_MB16_DATA2)
960#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
961#define bfin_read_CAN1_MB16_DATA3() bfin_read16(CAN1_MB16_DATA3)
962#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
963#define bfin_read_CAN1_MB16_LENGTH() bfin_read16(CAN1_MB16_LENGTH)
964#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
965#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP)
966#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
967#define bfin_read_CAN1_MB16_ID0() bfin_read16(CAN1_MB16_ID0)
968#define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val)
969#define bfin_read_CAN1_MB16_ID1() bfin_read16(CAN1_MB16_ID1)
970#define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val)
971#define bfin_read_CAN1_MB17_DATA0() bfin_read16(CAN1_MB17_DATA0)
972#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
973#define bfin_read_CAN1_MB17_DATA1() bfin_read16(CAN1_MB17_DATA1)
974#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
975#define bfin_read_CAN1_MB17_DATA2() bfin_read16(CAN1_MB17_DATA2)
976#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
977#define bfin_read_CAN1_MB17_DATA3() bfin_read16(CAN1_MB17_DATA3)
978#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
979#define bfin_read_CAN1_MB17_LENGTH() bfin_read16(CAN1_MB17_LENGTH)
980#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
981#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP)
982#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
983#define bfin_read_CAN1_MB17_ID0() bfin_read16(CAN1_MB17_ID0)
984#define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val)
985#define bfin_read_CAN1_MB17_ID1() bfin_read16(CAN1_MB17_ID1)
986#define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val)
987#define bfin_read_CAN1_MB18_DATA0() bfin_read16(CAN1_MB18_DATA0)
988#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
989#define bfin_read_CAN1_MB18_DATA1() bfin_read16(CAN1_MB18_DATA1)
990#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
991#define bfin_read_CAN1_MB18_DATA2() bfin_read16(CAN1_MB18_DATA2)
992#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
993#define bfin_read_CAN1_MB18_DATA3() bfin_read16(CAN1_MB18_DATA3)
994#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
995#define bfin_read_CAN1_MB18_LENGTH() bfin_read16(CAN1_MB18_LENGTH)
996#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
997#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP)
998#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
999#define bfin_read_CAN1_MB18_ID0() bfin_read16(CAN1_MB18_ID0)
1000#define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val)
1001#define bfin_read_CAN1_MB18_ID1() bfin_read16(CAN1_MB18_ID1)
1002#define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val)
1003#define bfin_read_CAN1_MB19_DATA0() bfin_read16(CAN1_MB19_DATA0)
1004#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
1005#define bfin_read_CAN1_MB19_DATA1() bfin_read16(CAN1_MB19_DATA1)
1006#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
1007#define bfin_read_CAN1_MB19_DATA2() bfin_read16(CAN1_MB19_DATA2)
1008#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
1009#define bfin_read_CAN1_MB19_DATA3() bfin_read16(CAN1_MB19_DATA3)
1010#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
1011#define bfin_read_CAN1_MB19_LENGTH() bfin_read16(CAN1_MB19_LENGTH)
1012#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
1013#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP)
1014#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
1015#define bfin_read_CAN1_MB19_ID0() bfin_read16(CAN1_MB19_ID0)
1016#define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val)
1017#define bfin_read_CAN1_MB19_ID1() bfin_read16(CAN1_MB19_ID1)
1018#define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val)
1019#define bfin_read_CAN1_MB20_DATA0() bfin_read16(CAN1_MB20_DATA0)
1020#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
1021#define bfin_read_CAN1_MB20_DATA1() bfin_read16(CAN1_MB20_DATA1)
1022#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
1023#define bfin_read_CAN1_MB20_DATA2() bfin_read16(CAN1_MB20_DATA2)
1024#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
1025#define bfin_read_CAN1_MB20_DATA3() bfin_read16(CAN1_MB20_DATA3)
1026#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
1027#define bfin_read_CAN1_MB20_LENGTH() bfin_read16(CAN1_MB20_LENGTH)
1028#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
1029#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP)
1030#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
1031#define bfin_read_CAN1_MB20_ID0() bfin_read16(CAN1_MB20_ID0)
1032#define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val)
1033#define bfin_read_CAN1_MB20_ID1() bfin_read16(CAN1_MB20_ID1)
1034#define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val)
1035#define bfin_read_CAN1_MB21_DATA0() bfin_read16(CAN1_MB21_DATA0)
1036#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
1037#define bfin_read_CAN1_MB21_DATA1() bfin_read16(CAN1_MB21_DATA1)
1038#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
1039#define bfin_read_CAN1_MB21_DATA2() bfin_read16(CAN1_MB21_DATA2)
1040#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
1041#define bfin_read_CAN1_MB21_DATA3() bfin_read16(CAN1_MB21_DATA3)
1042#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
1043#define bfin_read_CAN1_MB21_LENGTH() bfin_read16(CAN1_MB21_LENGTH)
1044#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
1045#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP)
1046#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
1047#define bfin_read_CAN1_MB21_ID0() bfin_read16(CAN1_MB21_ID0)
1048#define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val)
1049#define bfin_read_CAN1_MB21_ID1() bfin_read16(CAN1_MB21_ID1)
1050#define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val)
1051#define bfin_read_CAN1_MB22_DATA0() bfin_read16(CAN1_MB22_DATA0)
1052#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
1053#define bfin_read_CAN1_MB22_DATA1() bfin_read16(CAN1_MB22_DATA1)
1054#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
1055#define bfin_read_CAN1_MB22_DATA2() bfin_read16(CAN1_MB22_DATA2)
1056#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
1057#define bfin_read_CAN1_MB22_DATA3() bfin_read16(CAN1_MB22_DATA3)
1058#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
1059#define bfin_read_CAN1_MB22_LENGTH() bfin_read16(CAN1_MB22_LENGTH)
1060#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
1061#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP)
1062#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
1063#define bfin_read_CAN1_MB22_ID0() bfin_read16(CAN1_MB22_ID0)
1064#define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val)
1065#define bfin_read_CAN1_MB22_ID1() bfin_read16(CAN1_MB22_ID1)
1066#define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val)
1067#define bfin_read_CAN1_MB23_DATA0() bfin_read16(CAN1_MB23_DATA0)
1068#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
1069#define bfin_read_CAN1_MB23_DATA1() bfin_read16(CAN1_MB23_DATA1)
1070#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
1071#define bfin_read_CAN1_MB23_DATA2() bfin_read16(CAN1_MB23_DATA2)
1072#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
1073#define bfin_read_CAN1_MB23_DATA3() bfin_read16(CAN1_MB23_DATA3)
1074#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
1075#define bfin_read_CAN1_MB23_LENGTH() bfin_read16(CAN1_MB23_LENGTH)
1076#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
1077#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP)
1078#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
1079#define bfin_read_CAN1_MB23_ID0() bfin_read16(CAN1_MB23_ID0)
1080#define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val)
1081#define bfin_read_CAN1_MB23_ID1() bfin_read16(CAN1_MB23_ID1)
1082#define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val)
1083#define bfin_read_CAN1_MB24_DATA0() bfin_read16(CAN1_MB24_DATA0)
1084#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
1085#define bfin_read_CAN1_MB24_DATA1() bfin_read16(CAN1_MB24_DATA1)
1086#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
1087#define bfin_read_CAN1_MB24_DATA2() bfin_read16(CAN1_MB24_DATA2)
1088#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
1089#define bfin_read_CAN1_MB24_DATA3() bfin_read16(CAN1_MB24_DATA3)
1090#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
1091#define bfin_read_CAN1_MB24_LENGTH() bfin_read16(CAN1_MB24_LENGTH)
1092#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
1093#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP)
1094#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
1095#define bfin_read_CAN1_MB24_ID0() bfin_read16(CAN1_MB24_ID0)
1096#define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val)
1097#define bfin_read_CAN1_MB24_ID1() bfin_read16(CAN1_MB24_ID1)
1098#define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val)
1099#define bfin_read_CAN1_MB25_DATA0() bfin_read16(CAN1_MB25_DATA0)
1100#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
1101#define bfin_read_CAN1_MB25_DATA1() bfin_read16(CAN1_MB25_DATA1)
1102#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
1103#define bfin_read_CAN1_MB25_DATA2() bfin_read16(CAN1_MB25_DATA2)
1104#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
1105#define bfin_read_CAN1_MB25_DATA3() bfin_read16(CAN1_MB25_DATA3)
1106#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
1107#define bfin_read_CAN1_MB25_LENGTH() bfin_read16(CAN1_MB25_LENGTH)
1108#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
1109#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP)
1110#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
1111#define bfin_read_CAN1_MB25_ID0() bfin_read16(CAN1_MB25_ID0)
1112#define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val)
1113#define bfin_read_CAN1_MB25_ID1() bfin_read16(CAN1_MB25_ID1)
1114#define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val)
1115#define bfin_read_CAN1_MB26_DATA0() bfin_read16(CAN1_MB26_DATA0)
1116#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
1117#define bfin_read_CAN1_MB26_DATA1() bfin_read16(CAN1_MB26_DATA1)
1118#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
1119#define bfin_read_CAN1_MB26_DATA2() bfin_read16(CAN1_MB26_DATA2)
1120#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
1121#define bfin_read_CAN1_MB26_DATA3() bfin_read16(CAN1_MB26_DATA3)
1122#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
1123#define bfin_read_CAN1_MB26_LENGTH() bfin_read16(CAN1_MB26_LENGTH)
1124#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
1125#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP)
1126#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
1127#define bfin_read_CAN1_MB26_ID0() bfin_read16(CAN1_MB26_ID0)
1128#define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val)
1129#define bfin_read_CAN1_MB26_ID1() bfin_read16(CAN1_MB26_ID1)
1130#define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val)
1131#define bfin_read_CAN1_MB27_DATA0() bfin_read16(CAN1_MB27_DATA0)
1132#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
1133#define bfin_read_CAN1_MB27_DATA1() bfin_read16(CAN1_MB27_DATA1)
1134#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
1135#define bfin_read_CAN1_MB27_DATA2() bfin_read16(CAN1_MB27_DATA2)
1136#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
1137#define bfin_read_CAN1_MB27_DATA3() bfin_read16(CAN1_MB27_DATA3)
1138#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
1139#define bfin_read_CAN1_MB27_LENGTH() bfin_read16(CAN1_MB27_LENGTH)
1140#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
1141#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP)
1142#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
1143#define bfin_read_CAN1_MB27_ID0() bfin_read16(CAN1_MB27_ID0)
1144#define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val)
1145#define bfin_read_CAN1_MB27_ID1() bfin_read16(CAN1_MB27_ID1)
1146#define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val)
1147#define bfin_read_CAN1_MB28_DATA0() bfin_read16(CAN1_MB28_DATA0)
1148#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
1149#define bfin_read_CAN1_MB28_DATA1() bfin_read16(CAN1_MB28_DATA1)
1150#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
1151#define bfin_read_CAN1_MB28_DATA2() bfin_read16(CAN1_MB28_DATA2)
1152#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
1153#define bfin_read_CAN1_MB28_DATA3() bfin_read16(CAN1_MB28_DATA3)
1154#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
1155#define bfin_read_CAN1_MB28_LENGTH() bfin_read16(CAN1_MB28_LENGTH)
1156#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
1157#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP)
1158#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
1159#define bfin_read_CAN1_MB28_ID0() bfin_read16(CAN1_MB28_ID0)
1160#define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val)
1161#define bfin_read_CAN1_MB28_ID1() bfin_read16(CAN1_MB28_ID1)
1162#define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val)
1163#define bfin_read_CAN1_MB29_DATA0() bfin_read16(CAN1_MB29_DATA0)
1164#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
1165#define bfin_read_CAN1_MB29_DATA1() bfin_read16(CAN1_MB29_DATA1)
1166#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
1167#define bfin_read_CAN1_MB29_DATA2() bfin_read16(CAN1_MB29_DATA2)
1168#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
1169#define bfin_read_CAN1_MB29_DATA3() bfin_read16(CAN1_MB29_DATA3)
1170#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
1171#define bfin_read_CAN1_MB29_LENGTH() bfin_read16(CAN1_MB29_LENGTH)
1172#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
1173#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP)
1174#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
1175#define bfin_read_CAN1_MB29_ID0() bfin_read16(CAN1_MB29_ID0)
1176#define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val)
1177#define bfin_read_CAN1_MB29_ID1() bfin_read16(CAN1_MB29_ID1)
1178#define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val)
1179#define bfin_read_CAN1_MB30_DATA0() bfin_read16(CAN1_MB30_DATA0)
1180#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
1181#define bfin_read_CAN1_MB30_DATA1() bfin_read16(CAN1_MB30_DATA1)
1182#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
1183#define bfin_read_CAN1_MB30_DATA2() bfin_read16(CAN1_MB30_DATA2)
1184#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
1185#define bfin_read_CAN1_MB30_DATA3() bfin_read16(CAN1_MB30_DATA3)
1186#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
1187#define bfin_read_CAN1_MB30_LENGTH() bfin_read16(CAN1_MB30_LENGTH)
1188#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
1189#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP)
1190#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
1191#define bfin_read_CAN1_MB30_ID0() bfin_read16(CAN1_MB30_ID0)
1192#define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val)
1193#define bfin_read_CAN1_MB30_ID1() bfin_read16(CAN1_MB30_ID1)
1194#define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val)
1195#define bfin_read_CAN1_MB31_DATA0() bfin_read16(CAN1_MB31_DATA0)
1196#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
1197#define bfin_read_CAN1_MB31_DATA1() bfin_read16(CAN1_MB31_DATA1)
1198#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
1199#define bfin_read_CAN1_MB31_DATA2() bfin_read16(CAN1_MB31_DATA2)
1200#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
1201#define bfin_read_CAN1_MB31_DATA3() bfin_read16(CAN1_MB31_DATA3)
1202#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
1203#define bfin_read_CAN1_MB31_LENGTH() bfin_read16(CAN1_MB31_LENGTH)
1204#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
1205#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP)
1206#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
1207#define bfin_read_CAN1_MB31_ID0() bfin_read16(CAN1_MB31_ID0)
1208#define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val)
1209#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1)
1210#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val)
1211
1212/* ATAPI Registers */
1213
1214#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL)
1215#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val)
1216#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS)
1217#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
1218#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR)
1219#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
1220#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF)
1221#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
1222#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF)
1223#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
1224#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK)
1225#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
1226#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS)
1227#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
1228#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN)
1229#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
1230#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS)
1231#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
1232#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE)
1233#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
1234#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE)
1235#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
1236#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT)
1237#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
1238#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT)
1239#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
1240#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
1241#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
1242#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
1243#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
1244#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0)
1245#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
1246#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0)
1247#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
1248#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1)
1249#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
1250#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0)
1251#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
1252#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1)
1253#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
1254#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2)
1255#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
1256#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0)
1257#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
1258#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1)
1259#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
1260#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2)
1261#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
1262#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3)
1263#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
1264
1265/* SDH Registers */
1266
1267#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL)
1268#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val)
1269#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL)
1270#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val)
1271#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT)
1272#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val)
1273#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND)
1274#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val)
1275#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD)
1276#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val)
1277#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0)
1278#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val)
1279#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1)
1280#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val)
1281#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2)
1282#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val)
1283#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3)
1284#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val)
1285#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER)
1286#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
1287#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH)
1288#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val)
1289#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL)
1290#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val)
1291#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT)
1292#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val)
1293#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS)
1294#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val)
1295#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR)
1296#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
1297#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0)
1298#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val)
1299#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1)
1300#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val)
1301#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT)
1302#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val)
1303#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO)
1304#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val)
1305#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS)
1306#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val)
1307#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK)
1308#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val)
1309#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG)
1310#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val)
1311#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN)
1312#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
1313#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0)
1314#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val)
1315#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1)
1316#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val)
1317#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2)
1318#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val)
1319#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3)
1320#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val)
1321#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4)
1322#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val)
1323#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5)
1324#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val)
1325#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6)
1326#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val)
1327#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7)
1328#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val)
1329
1330/* HOST Port Registers */
1331
1332#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
1333#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
1334#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
1335#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
1336#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
1337#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
1338
1339/* USB Control Registers */
1340
1341#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
1342#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
1343#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
1344#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
1345#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
1346#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
1347#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
1348#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
1349#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
1350#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
1351#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
1352#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
1353#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
1354#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
1355#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
1356#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
1357#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
1358#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
1359#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
1360#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
1361#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
1362#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
1363#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
1364#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
1365#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
1366#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
1367
1368/* USB Packet Control Registers */
1369
1370#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
1371#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
1372#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
1373#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
1374#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
1375#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
1376#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
1377#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
1378#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
1379#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
1380#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
1381#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
1382#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
1383#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
1384#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
1385#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
1386#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
1387#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
1388#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
1389#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
1390#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
1391#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
1392#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
1393#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
1394#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
1395#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
1396
1397/* USB Endbfin_read_()oint FIFO Registers */
1398
1399#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
1400#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
1401#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
1402#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
1403#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
1404#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
1405#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
1406#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
1407#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
1408#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
1409#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
1410#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
1411#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
1412#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
1413#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
1414#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
1415
1416/* USB OTG Control Registers */
1417
1418#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
1419#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
1420#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
1421#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
1422#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
1423#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
1424
1425/* USB Phy Control Registers */
1426
1427#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
1428#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
1429#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
1430#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
1431#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
1432#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
1433#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
1434#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
1435#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
1436#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
1437
1438/* (APHY_CNTRL is for ADI usage only) */
1439
1440#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
1441#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
1442
1443/* (APHY_CALIB is for ADI usage only) */
1444
1445#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
1446#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
1447#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
1448#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
1449
1450/* (PHY_TEST is for ADI usage only) */
1451
1452#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
1453#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
1454#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
1455#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
1456#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
1457#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
1458
1459/* USB Endbfin_read_()oint 0 Control Registers */
1460
1461#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
1462#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
1463#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
1464#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
1465#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
1466#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
1467#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
1468#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
1469#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
1470#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
1471#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
1472#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
1473#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
1474#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
1475#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
1476#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
1477#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
1478#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
1479
1480/* USB Endbfin_read_()oint 1 Control Registers */
1481
1482#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
1483#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
1484#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
1485#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
1486#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
1487#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
1488#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
1489#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
1490#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
1491#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
1492#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
1493#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
1494#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
1495#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
1496#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
1497#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
1498#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
1499#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
1500#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
1501#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
1502
1503/* USB Endbfin_read_()oint 2 Control Registers */
1504
1505#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
1506#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
1507#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
1508#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
1509#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
1510#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
1511#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
1512#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
1513#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
1514#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
1515#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
1516#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
1517#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
1518#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
1519#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
1520#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
1521#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
1522#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
1523#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
1524#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
1525
1526/* USB Endbfin_read_()oint 3 Control Registers */
1527
1528#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
1529#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
1530#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
1531#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
1532#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
1533#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
1534#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
1535#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
1536#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
1537#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
1538#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
1539#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
1540#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
1541#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
1542#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
1543#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
1544#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
1545#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
1546#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
1547#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
1548
1549/* USB Endbfin_read_()oint 4 Control Registers */
1550
1551#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
1552#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
1553#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
1554#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
1555#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
1556#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
1557#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
1558#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
1559#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
1560#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
1561#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
1562#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
1563#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
1564#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
1565#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
1566#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
1567#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
1568#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
1569#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
1570#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
1571
1572/* USB Endbfin_read_()oint 5 Control Registers */
1573
1574#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
1575#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
1576#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
1577#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
1578#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
1579#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
1580#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
1581#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
1582#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
1583#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
1584#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
1585#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
1586#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
1587#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
1588#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
1589#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
1590#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
1591#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
1592#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
1593#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
1594
1595/* USB Endbfin_read_()oint 6 Control Registers */
1596
1597#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
1598#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
1599#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
1600#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
1601#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
1602#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
1603#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
1604#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
1605#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
1606#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
1607#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
1608#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
1609#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
1610#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
1611#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
1612#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
1613#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
1614#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
1615#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
1616#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
1617
1618/* USB Endbfin_read_()oint 7 Control Registers */
1619
1620#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
1621#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
1622#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
1623#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
1624#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
1625#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
1626#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
1627#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
1628#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
1629#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
1630#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
1631#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
1632#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
1633#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
1634#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
1635#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
1636#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
1637#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
1638#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
1639#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
1640#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
1641#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
1642#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
1643#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
1644
1645/* USB Channel 0 Config Registers */
1646
1647#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
1648#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
1649#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
1650#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
1651#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
1652#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
1653#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
1654#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
1655#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
1656#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
1657
1658/* USB Channel 1 Config Registers */
1659
1660#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
1661#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
1662#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
1663#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
1664#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
1665#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
1666#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
1667#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
1668#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
1669#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
1670
1671/* USB Channel 2 Config Registers */
1672
1673#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
1674#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
1675#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
1676#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
1677#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
1678#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
1679#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
1680#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
1681#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
1682#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
1683
1684/* USB Channel 3 Config Registers */
1685
1686#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
1687#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
1688#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
1689#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
1690#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
1691#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
1692#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
1693#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
1694#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
1695#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
1696
1697/* USB Channel 4 Config Registers */
1698
1699#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
1700#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
1701#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
1702#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
1703#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
1704#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
1705#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
1706#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
1707#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
1708#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
1709
1710/* USB Channel 5 Config Registers */
1711
1712#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
1713#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
1714#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
1715#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
1716#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
1717#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
1718#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
1719#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
1720#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
1721#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
1722
1723/* USB Channel 6 Config Registers */
1724
1725#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
1726#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
1727#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
1728#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
1729#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
1730#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
1731#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
1732#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
1733#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
1734#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
1735
1736/* USB Channel 7 Config Registers */
1737
1738#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
1739#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
1740#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
1741#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
1742#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
1743#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
1744#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
1745#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
1746#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
1747#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
1748
1749/* Keybfin_read_()ad Registers */
1750
1751#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL)
1752#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val)
1753#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE)
1754#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val)
1755#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL)
1756#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val)
1757#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL)
1758#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val)
1759#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT)
1760#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val)
1761#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL)
1762#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val)
1763
1764/* Pixel Combfin_read_()ositor (PIXC) Registers */
1765
1766#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL)
1767#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val)
1768#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL)
1769#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val)
1770#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF)
1771#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val)
1772#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART)
1773#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val)
1774#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND)
1775#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val)
1776#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART)
1777#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val)
1778#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND)
1779#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val)
1780#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP)
1781#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val)
1782#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART)
1783#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val)
1784#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND)
1785#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val)
1786#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART)
1787#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val)
1788#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND)
1789#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val)
1790#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP)
1791#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val)
1792#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT)
1793#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val)
1794#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON)
1795#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val)
1796#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON)
1797#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val)
1798#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON)
1799#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val)
1800#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS)
1801#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val)
1802#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC)
1803#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val)
1804
1805/* Handshake MDMA 0 Registers */
1806
1807#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
1808#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
1809#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
1810#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
1811#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
1812#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
1813#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
1814#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
1815#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
1816#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
1817#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
1818#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
1819#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
1820#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
1821
1822/* Handshake MDMA 1 Registers */
1823
1824#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
1825#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
1826#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
1827#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
1828#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
1829#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
1830#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
1831#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
1832#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
1833#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
1834#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
1835#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
1836#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
1837#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
1838
1839#endif /* _CDEF_BF549_H */ 310#endif /* _CDEF_BF549_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF548.h b/arch/blackfin/mach-bf548/include/mach/defBF548.h
index a5079980968..3fb33b040ab 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF548.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF548.h
@@ -15,115 +15,8 @@
15/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */ 15/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
16#include "defBF54x_base.h" 16#include "defBF54x_base.h"
17 17
18/* The following are the #defines needed by ADSP-BF548 that are not in the common header */ 18/* The BF548 is like the BF547, but has additional CANs */
19 19#include "defBF547.h"
20/* Timer Registers */
21
22#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */
23#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */
24#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */
25#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */
26#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */
27#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */
28#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */
29#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */
30#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */
31#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */
32#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */
33#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */
34
35/* Timer Group of 3 Registers */
36
37#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */
38#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */
39#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */
40
41/* SPORT0 Registers */
42
43#define SPORT0_TCR1 0xffc00800 /* SPORT0 Transmit Configuration 1 Register */
44#define SPORT0_TCR2 0xffc00804 /* SPORT0 Transmit Configuration 2 Register */
45#define SPORT0_TCLKDIV 0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */
46#define SPORT0_TFSDIV 0xffc0080c /* SPORT0 Transmit Frame Sync Divider Register */
47#define SPORT0_TX 0xffc00810 /* SPORT0 Transmit Data Register */
48#define SPORT0_RX 0xffc00818 /* SPORT0 Receive Data Register */
49#define SPORT0_RCR1 0xffc00820 /* SPORT0 Receive Configuration 1 Register */
50#define SPORT0_RCR2 0xffc00824 /* SPORT0 Receive Configuration 2 Register */
51#define SPORT0_RCLKDIV 0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */
52#define SPORT0_RFSDIV 0xffc0082c /* SPORT0 Receive Frame Sync Divider Register */
53#define SPORT0_STAT 0xffc00830 /* SPORT0 Status Register */
54#define SPORT0_CHNL 0xffc00834 /* SPORT0 Current Channel Register */
55#define SPORT0_MCMC1 0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */
56#define SPORT0_MCMC2 0xffc0083c /* SPORT0 Multi channel Configuration Register 2 */
57#define SPORT0_MTCS0 0xffc00840 /* SPORT0 Multi channel Transmit Select Register 0 */
58#define SPORT0_MTCS1 0xffc00844 /* SPORT0 Multi channel Transmit Select Register 1 */
59#define SPORT0_MTCS2 0xffc00848 /* SPORT0 Multi channel Transmit Select Register 2 */
60#define SPORT0_MTCS3 0xffc0084c /* SPORT0 Multi channel Transmit Select Register 3 */
61#define SPORT0_MRCS0 0xffc00850 /* SPORT0 Multi channel Receive Select Register 0 */
62#define SPORT0_MRCS1 0xffc00854 /* SPORT0 Multi channel Receive Select Register 1 */
63#define SPORT0_MRCS2 0xffc00858 /* SPORT0 Multi channel Receive Select Register 2 */
64#define SPORT0_MRCS3 0xffc0085c /* SPORT0 Multi channel Receive Select Register 3 */
65
66/* EPPI0 Registers */
67
68#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */
69#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */
70#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */
71#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */
72#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */
73#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */
74#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */
75#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */
76#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */
77#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
78#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
79#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
80#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
81#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */
82
83/* UART2 Registers */
84
85#define UART2_DLL 0xffc02100 /* Divisor Latch Low Byte */
86#define UART2_DLH 0xffc02104 /* Divisor Latch High Byte */
87#define UART2_GCTL 0xffc02108 /* Global Control Register */
88#define UART2_LCR 0xffc0210c /* Line Control Register */
89#define UART2_MCR 0xffc02110 /* Modem Control Register */
90#define UART2_LSR 0xffc02114 /* Line Status Register */
91#define UART2_MSR 0xffc02118 /* Modem Status Register */
92#define UART2_SCR 0xffc0211c /* Scratch Register */
93#define UART2_IER_SET 0xffc02120 /* Interrupt Enable Register Set */
94#define UART2_IER_CLEAR 0xffc02124 /* Interrupt Enable Register Clear */
95#define UART2_RBR 0xffc0212c /* Receive Buffer Register */
96
97/* Two Wire Interface Registers (TWI1) */
98
99#define TWI1_REGBASE 0xffc02200
100#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
101#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
102#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */
103#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
104#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
105#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */
106#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
107#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
108#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
109#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
110#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */
111#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
112#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
113#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
114#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */
115#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */
116
117/* SPI2 Registers */
118
119#define SPI2_REGBASE 0xffc02400
120#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */
121#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */
122#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */
123#define SPI2_TDBR 0xffc0240c /* SPI2 Transmit Data Buffer Register */
124#define SPI2_RDBR 0xffc02410 /* SPI2 Receive Data Buffer Register */
125#define SPI2_BAUD 0xffc02414 /* SPI2 Baud Rate Register */
126#define SPI2_SHADOW 0xffc02418 /* SPI2 Receive Data Buffer Shadow Register */
127 20
128/* CAN Controller 1 Config 1 Registers */ 21/* CAN Controller 1 Config 1 Registers */
129 22
@@ -508,1096 +401,4 @@
508#define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */ 401#define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */
509#define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */ 402#define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */
510 403
511/* ATAPI Registers */
512
513#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */
514#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */
515#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */
516#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */
517#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */
518#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */
519#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */
520#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */
521#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */
522#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */
523#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */
524#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */
525#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */
526#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */
527#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */
528#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */
529#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */
530#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */
531#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
532#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
533#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
534#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
535#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
536#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
537#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
538
539/* SDH Registers */
540
541#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */
542#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */
543#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */
544#define SDH_COMMAND 0xffc0390c /* SDH Command */
545#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */
546#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */
547#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */
548#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */
549#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */
550#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */
551#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */
552#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */
553#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */
554#define SDH_STATUS 0xffc03934 /* SDH Status */
555#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */
556#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */
557#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */
558#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */
559#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */
560#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */
561#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */
562#define SDH_CFG 0xffc039c8 /* SDH Configuration */
563#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */
564#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */
565#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */
566#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */
567#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */
568#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */
569#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */
570#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */
571#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */
572
573/* HOST Port Registers */
574
575#define HOST_CONTROL 0xffc03a00 /* HOST Control Register */
576#define HOST_STATUS 0xffc03a04 /* HOST Status Register */
577#define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */
578
579/* USB Control Registers */
580
581#define USB_FADDR 0xffc03c00 /* Function address register */
582#define USB_POWER 0xffc03c04 /* Power management register */
583#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
584#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */
585#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
586#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
587#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */
588#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
589#define USB_FRAME 0xffc03c20 /* USB frame number */
590#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */
591#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */
592#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
593#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
594
595/* USB Packet Control Registers */
596
597#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */
598#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
599#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
600#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */
601#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */
602#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
603#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
604#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
605#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
606#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
607#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
608#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
609#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
610
611/* USB Endpoint FIFO Registers */
612
613#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */
614#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */
615#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */
616#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */
617#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */
618#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */
619#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */
620#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */
621
622/* USB OTG Control Registers */
623
624#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */
625#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */
626#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */
627
628/* USB Phy Control Registers */
629
630#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */
631#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */
632#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
633#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
634#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
635
636/* (APHY_CNTRL is for ADI usage only) */
637
638#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */
639
640/* (APHY_CALIB is for ADI usage only) */
641
642#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */
643#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
644
645/* (PHY_TEST is for ADI usage only) */
646
647#define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */
648#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */
649#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
650
651/* USB Endpoint 0 Control Registers */
652
653#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */
654#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */
655#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */
656#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */
657#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */
658#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
659#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
660#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
661#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
662
663/* USB Endpoint 1 Control Registers */
664
665#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
666#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
667#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
668#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
669#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */
670#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */
671#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
672#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
673#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
674#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
675
676/* USB Endpoint 2 Control Registers */
677
678#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
679#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
680#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
681#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
682#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */
683#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */
684#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
685#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
686#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
687#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
688
689/* USB Endpoint 3 Control Registers */
690
691#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
692#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
693#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
694#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
695#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */
696#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */
697#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
698#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
699#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
700#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
701
702/* USB Endpoint 4 Control Registers */
703
704#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
705#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
706#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
707#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
708#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */
709#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */
710#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
711#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
712#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
713#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
714
715/* USB Endpoint 5 Control Registers */
716
717#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
718#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
719#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
720#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
721#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */
722#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */
723#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
724#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
725#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
726#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
727
728/* USB Endpoint 6 Control Registers */
729
730#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
731#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
732#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
733#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
734#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */
735#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */
736#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
737#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
738#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
739#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
740
741/* USB Endpoint 7 Control Registers */
742
743#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
744#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
745#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
746#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
747#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */
748#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */
749#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
750#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
751#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
752#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
753#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
754#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */
755
756/* USB Channel 0 Config Registers */
757
758#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */
759#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
760#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
761#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
762#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
763
764/* USB Channel 1 Config Registers */
765
766#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */
767#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
768#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
769#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
770#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
771
772/* USB Channel 2 Config Registers */
773
774#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */
775#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
776#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
777#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
778#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
779
780/* USB Channel 3 Config Registers */
781
782#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */
783#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
784#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
785#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
786#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
787
788/* USB Channel 4 Config Registers */
789
790#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */
791#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
792#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
793#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
794#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
795
796/* USB Channel 5 Config Registers */
797
798#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */
799#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
800#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
801#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
802#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
803
804/* USB Channel 6 Config Registers */
805
806#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */
807#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
808#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
809#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
810#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
811
812/* USB Channel 7 Config Registers */
813
814#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */
815#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
816#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
817#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
818#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
819
820/* Keypad Registers */
821
822#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */
823#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */
824#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */
825#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */
826#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */
827#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */
828
829/* Pixel Compositor (PIXC) Registers */
830
831#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
832#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */
833#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */
834#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */
835#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */
836#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */
837#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */
838#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */
839#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */
840#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */
841#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */
842#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */
843#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */
844#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */
845#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
846#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
847#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
848#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */
849#define PIXC_TC 0xffc04450 /* Holds the transparent color value */
850
851/* Handshake MDMA 0 Registers */
852
853#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */
854#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */
855#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */
856#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshold Register */
857#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
858#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */
859#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */
860
861/* Handshake MDMA 1 Registers */
862
863#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */
864#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */
865#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */
866#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshold Register */
867#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
868#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */
869#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */
870
871
872/* ********************************************************** */
873/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
874/* and MULTI BIT READ MACROS */
875/* ********************************************************** */
876
877/* Bit masks for PIXC_CTL */
878
879#define PIXC_EN 0x1 /* Pixel Compositor Enable */
880#define OVR_A_EN 0x2 /* Overlay A Enable */
881#define OVR_B_EN 0x4 /* Overlay B Enable */
882#define IMG_FORM 0x8 /* Image Data Format */
883#define OVR_FORM 0x10 /* Overlay Data Format */
884#define OUT_FORM 0x20 /* Output Data Format */
885#define UDS_MOD 0x40 /* Resampling Mode */
886#define TC_EN 0x80 /* Transparent Color Enable */
887#define IMG_STAT 0x300 /* Image FIFO Status */
888#define OVR_STAT 0xc00 /* Overlay FIFO Status */
889#define WM_LVL 0x3000 /* FIFO Watermark Level */
890
891/* Bit masks for PIXC_AHSTART */
892
893#define A_HSTART 0xfff /* Horizontal Start Coordinates */
894
895/* Bit masks for PIXC_AHEND */
896
897#define A_HEND 0xfff /* Horizontal End Coordinates */
898
899/* Bit masks for PIXC_AVSTART */
900
901#define A_VSTART 0x3ff /* Vertical Start Coordinates */
902
903/* Bit masks for PIXC_AVEND */
904
905#define A_VEND 0x3ff /* Vertical End Coordinates */
906
907/* Bit masks for PIXC_ATRANSP */
908
909#define A_TRANSP 0xf /* Transparency Value */
910
911/* Bit masks for PIXC_BHSTART */
912
913#define B_HSTART 0xfff /* Horizontal Start Coordinates */
914
915/* Bit masks for PIXC_BHEND */
916
917#define B_HEND 0xfff /* Horizontal End Coordinates */
918
919/* Bit masks for PIXC_BVSTART */
920
921#define B_VSTART 0x3ff /* Vertical Start Coordinates */
922
923/* Bit masks for PIXC_BVEND */
924
925#define B_VEND 0x3ff /* Vertical End Coordinates */
926
927/* Bit masks for PIXC_BTRANSP */
928
929#define B_TRANSP 0xf /* Transparency Value */
930
931/* Bit masks for PIXC_INTRSTAT */
932
933#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
934#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
935#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
936#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
937
938/* Bit masks for PIXC_RYCON */
939
940#define A11 0x3ff /* A11 in the Coefficient Matrix */
941#define A12 0xffc00 /* A12 in the Coefficient Matrix */
942#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
943#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
944
945/* Bit masks for PIXC_GUCON */
946
947#define A21 0x3ff /* A21 in the Coefficient Matrix */
948#define A22 0xffc00 /* A22 in the Coefficient Matrix */
949#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
950#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
951
952/* Bit masks for PIXC_BVCON */
953
954#define A31 0x3ff /* A31 in the Coefficient Matrix */
955#define A32 0xffc00 /* A32 in the Coefficient Matrix */
956#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
957#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
958
959/* Bit masks for PIXC_CCBIAS */
960
961#define A14 0x3ff /* A14 in the Bias Vector */
962#define A24 0xffc00 /* A24 in the Bias Vector */
963#define A34 0x3ff00000 /* A34 in the Bias Vector */
964
965/* Bit masks for PIXC_TC */
966
967#define RY_TRANS 0xff /* Transparent Color - R/Y Component */
968#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */
969#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */
970
971/* Bit masks for HOST_CONTROL */
972
973#define HOST_EN 0x1 /* Host Enable */
974#define HOST_END 0x2 /* Host Endianess */
975#define DATA_SIZE 0x4 /* Data Size */
976#define HOST_RST 0x8 /* Host Reset */
977#define HRDY_OVR 0x20 /* Host Ready Override */
978#define INT_MODE 0x40 /* Interrupt Mode */
979#define BT_EN 0x80 /* Bus Timeout Enable */
980#define EHW 0x100 /* Enable Host Write */
981#define EHR 0x200 /* Enable Host Read */
982#define BDR 0x400 /* Burst DMA Requests */
983
984/* Bit masks for HOST_STATUS */
985
986#define DMA_READY 0x1 /* DMA Ready */
987#define FIFOFULL 0x2 /* FIFO Full */
988#define FIFOEMPTY 0x4 /* FIFO Empty */
989#define DMA_COMPLETE 0x8 /* DMA Complete */
990#define HSHK 0x10 /* Host Handshake */
991#define HSTIMEOUT 0x20 /* Host Timeout */
992#define HIRQ 0x40 /* Host Interrupt Request */
993#define ALLOW_CNFG 0x80 /* Allow New Configuration */
994#define DMA_DIR 0x100 /* DMA Direction */
995#define BTE 0x200 /* Bus Timeout Enabled */
996
997/* Bit masks for HOST_TIMEOUT */
998
999#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */
1000
1001/* Bit masks for KPAD_CTL */
1002
1003#define KPAD_EN 0x1 /* Keypad Enable */
1004#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
1005#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
1006#define KPAD_COLEN 0xe000 /* Column Enable Width */
1007
1008/* Bit masks for KPAD_PRESCALE */
1009
1010#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
1011
1012/* Bit masks for KPAD_MSEL */
1013
1014#define DBON_SCALE 0xff /* Debounce Scale Value */
1015#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
1016
1017/* Bit masks for KPAD_ROWCOL */
1018
1019#define KPAD_ROW 0xff /* Rows Pressed */
1020#define KPAD_COL 0xff00 /* Columns Pressed */
1021
1022/* Bit masks for KPAD_STAT */
1023
1024#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
1025#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
1026#define KPAD_PRESSED 0x8 /* Key press current status */
1027
1028/* Bit masks for KPAD_SOFTEVAL */
1029
1030#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
1031
1032/* Bit masks for SDH_COMMAND */
1033
1034#define CMD_IDX 0x3f /* Command Index */
1035#define CMD_RSP 0x40 /* Response */
1036#define CMD_L_RSP 0x80 /* Long Response */
1037#define CMD_INT_E 0x100 /* Command Interrupt */
1038#define CMD_PEND_E 0x200 /* Command Pending */
1039#define CMD_E 0x400 /* Command Enable */
1040
1041/* Bit masks for SDH_PWR_CTL */
1042
1043#define PWR_ON 0x3 /* Power On */
1044#if 0
1045#define TBD 0x3c /* TBD */
1046#endif
1047#define SD_CMD_OD 0x40 /* Open Drain Output */
1048#define ROD_CTL 0x80 /* Rod Control */
1049
1050/* Bit masks for SDH_CLK_CTL */
1051
1052#define CLKDIV 0xff /* MC_CLK Divisor */
1053#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
1054#define PWR_SV_E 0x200 /* Power Save Enable */
1055#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
1056#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
1057
1058/* Bit masks for SDH_RESP_CMD */
1059
1060#define RESP_CMD 0x3f /* Response Command */
1061
1062/* Bit masks for SDH_DATA_CTL */
1063
1064#define DTX_E 0x1 /* Data Transfer Enable */
1065#define DTX_DIR 0x2 /* Data Transfer Direction */
1066#define DTX_MODE 0x4 /* Data Transfer Mode */
1067#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
1068#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
1069
1070/* Bit masks for SDH_STATUS */
1071
1072#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
1073#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
1074#define CMD_TIME_OUT 0x4 /* CMD Time Out */
1075#define DAT_TIME_OUT 0x8 /* Data Time Out */
1076#define TX_UNDERRUN 0x10 /* Transmit Underrun */
1077#define RX_OVERRUN 0x20 /* Receive Overrun */
1078#define CMD_RESP_END 0x40 /* CMD Response End */
1079#define CMD_SENT 0x80 /* CMD Sent */
1080#define DAT_END 0x100 /* Data End */
1081#define START_BIT_ERR 0x200 /* Start Bit Error */
1082#define DAT_BLK_END 0x400 /* Data Block End */
1083#define CMD_ACT 0x800 /* CMD Active */
1084#define TX_ACT 0x1000 /* Transmit Active */
1085#define RX_ACT 0x2000 /* Receive Active */
1086#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
1087#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
1088#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
1089#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
1090#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
1091#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
1092#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
1093#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
1094
1095/* Bit masks for SDH_STATUS_CLR */
1096
1097#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
1098#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
1099#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
1100#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
1101#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
1102#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
1103#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
1104#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
1105#define DAT_END_STAT 0x100 /* Data End Status */
1106#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
1107#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
1108
1109/* Bit masks for SDH_MASK0 */
1110
1111#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
1112#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
1113#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
1114#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
1115#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
1116#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
1117#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
1118#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
1119#define DAT_END_MASK 0x100 /* Data End Mask */
1120#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
1121#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
1122#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
1123#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
1124#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
1125#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
1126#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
1127#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
1128#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
1129#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
1130#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
1131#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
1132#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
1133
1134/* Bit masks for SDH_FIFO_CNT */
1135
1136#define FIFO_COUNT 0x7fff /* FIFO Count */
1137
1138/* Bit masks for SDH_E_STATUS */
1139
1140#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
1141#define SD_CARD_DET 0x10 /* SD Card Detect */
1142
1143/* Bit masks for SDH_E_MASK */
1144
1145#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
1146#define SCD_MSK 0x40 /* Mask Card Detect */
1147
1148/* Bit masks for SDH_CFG */
1149
1150#define CLKS_EN 0x1 /* Clocks Enable */
1151#define SD4E 0x4 /* SDIO 4-Bit Enable */
1152#define MWE 0x8 /* Moving Window Enable */
1153#define SD_RST 0x10 /* SDMMC Reset */
1154#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
1155#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
1156#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
1157
1158/* Bit masks for SDH_RD_WAIT_EN */
1159
1160#define RWR 0x1 /* Read Wait Request */
1161
1162/* Bit masks for ATAPI_CONTROL */
1163
1164#define PIO_START 0x1 /* Start PIO/Reg Op */
1165#define MULTI_START 0x2 /* Start Multi-DMA Op */
1166#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
1167#define XFER_DIR 0x8 /* Transfer Direction */
1168#define IORDY_EN 0x10 /* IORDY Enable */
1169#define FIFO_FLUSH 0x20 /* Flush FIFOs */
1170#define SOFT_RST 0x40 /* Soft Reset */
1171#define DEV_RST 0x80 /* Device Reset */
1172#define TFRCNT_RST 0x100 /* Trans Count Reset */
1173#define END_ON_TERM 0x200 /* End/Terminate Select */
1174#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
1175#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
1176
1177/* Bit masks for ATAPI_STATUS */
1178
1179#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
1180#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
1181#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
1182#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
1183
1184/* Bit masks for ATAPI_DEV_ADDR */
1185
1186#define DEV_ADDR 0x1f /* Device Address */
1187
1188/* Bit masks for ATAPI_INT_MASK */
1189
1190#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
1191#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
1192#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
1193#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
1194#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
1195#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
1196#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
1197#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
1198#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
1199
1200/* Bit masks for ATAPI_INT_STATUS */
1201
1202#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
1203#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
1204#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
1205#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
1206#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
1207#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
1208#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
1209#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
1210#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
1211
1212/* Bit masks for ATAPI_LINE_STATUS */
1213
1214#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
1215#define ATAPI_DASP 0x2 /* Device dasp to host line status */
1216#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
1217#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
1218#define ATAPI_ADDR 0x70 /* ATAPI address line status */
1219#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
1220#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
1221#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
1222#define ATAPI_DIORN 0x400 /* ATAPI read line status */
1223#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
1224
1225/* Bit masks for ATAPI_SM_STATE */
1226
1227#define PIO_CSTATE 0xf /* PIO mode state machine current state */
1228#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */
1229#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
1230#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
1231
1232/* Bit masks for ATAPI_TERMINATE */
1233
1234#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
1235
1236/* Bit masks for ATAPI_REG_TIM_0 */
1237
1238#define T2_REG 0xff /* End of cycle time for register access transfers */
1239#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */
1240
1241/* Bit masks for ATAPI_PIO_TIM_0 */
1242
1243#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */
1244#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */
1245#define T4_REG 0xf000 /* DIOW data hold */
1246
1247/* Bit masks for ATAPI_PIO_TIM_1 */
1248
1249#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
1250
1251/* Bit masks for ATAPI_MULTI_TIM_0 */
1252
1253#define TD 0xff /* DIOR/DIOW asserted pulsewidth */
1254#define TM 0xff00 /* Time from address valid to DIOR/DIOW */
1255
1256/* Bit masks for ATAPI_MULTI_TIM_1 */
1257
1258#define TKW 0xff /* Selects DIOW negated pulsewidth */
1259#define TKR 0xff00 /* Selects DIOR negated pulsewidth */
1260
1261/* Bit masks for ATAPI_MULTI_TIM_2 */
1262
1263#define TH 0xff /* Selects DIOW data hold */
1264#define TEOC 0xff00 /* Selects end of cycle for DMA */
1265
1266/* Bit masks for ATAPI_ULTRA_TIM_0 */
1267
1268#define TACK 0xff /* Selects setup and hold times for TACK */
1269#define TENV 0xff00 /* Selects envelope time */
1270
1271/* Bit masks for ATAPI_ULTRA_TIM_1 */
1272
1273#define TDVS 0xff /* Selects data valid setup time */
1274#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
1275
1276/* Bit masks for ATAPI_ULTRA_TIM_2 */
1277
1278#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
1279#define TMLI 0xff00 /* Selects interlock time */
1280
1281/* Bit masks for ATAPI_ULTRA_TIM_3 */
1282
1283#define TZAH 0xff /* Selects minimum delay required for output */
1284#define READY_PAUSE 0xff00 /* Selects ready to pause */
1285
1286/* Bit masks for TIMER_ENABLE1 */
1287
1288#define TIMEN8 0x1 /* Timer 8 Enable */
1289#define TIMEN9 0x2 /* Timer 9 Enable */
1290#define TIMEN10 0x4 /* Timer 10 Enable */
1291
1292/* Bit masks for TIMER_DISABLE1 */
1293
1294#define TIMDIS8 0x1 /* Timer 8 Disable */
1295#define TIMDIS9 0x2 /* Timer 9 Disable */
1296#define TIMDIS10 0x4 /* Timer 10 Disable */
1297
1298/* Bit masks for TIMER_STATUS1 */
1299
1300#define TIMIL8 0x1 /* Timer 8 Interrupt */
1301#define TIMIL9 0x2 /* Timer 9 Interrupt */
1302#define TIMIL10 0x4 /* Timer 10 Interrupt */
1303#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
1304#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
1305#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
1306#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
1307#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
1308#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
1309
1310/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
1311
1312/* Bit masks for USB_FADDR */
1313
1314#define FUNCTION_ADDRESS 0x7f /* Function address */
1315
1316/* Bit masks for USB_POWER */
1317
1318#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
1319#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
1320#define RESUME_MODE 0x4 /* DMA Mode */
1321#define RESET 0x8 /* Reset indicator */
1322#define HS_MODE 0x10 /* High Speed mode indicator */
1323#define HS_ENABLE 0x20 /* high Speed Enable */
1324#define SOFT_CONN 0x40 /* Soft connect */
1325#define ISO_UPDATE 0x80 /* Isochronous update */
1326
1327/* Bit masks for USB_INTRTX */
1328
1329#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
1330#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
1331#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
1332#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
1333#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
1334#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
1335#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
1336#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
1337
1338/* Bit masks for USB_INTRRX */
1339
1340#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
1341#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
1342#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
1343#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
1344#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
1345#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
1346#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
1347
1348/* Bit masks for USB_INTRTXE */
1349
1350#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
1351#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
1352#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
1353#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
1354#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
1355#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
1356#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
1357#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
1358
1359/* Bit masks for USB_INTRRXE */
1360
1361#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
1362#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
1363#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
1364#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
1365#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
1366#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
1367#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
1368
1369/* Bit masks for USB_INTRUSB */
1370
1371#define SUSPEND_B 0x1 /* Suspend indicator */
1372#define RESUME_B 0x2 /* Resume indicator */
1373#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
1374#define SOF_B 0x8 /* Start of frame */
1375#define CONN_B 0x10 /* Connection indicator */
1376#define DISCON_B 0x20 /* Disconnect indicator */
1377#define SESSION_REQ_B 0x40 /* Session Request */
1378#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
1379
1380/* Bit masks for USB_INTRUSBE */
1381
1382#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
1383#define RESUME_BE 0x2 /* Resume indicator int enable */
1384#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
1385#define SOF_BE 0x8 /* Start of frame int enable */
1386#define CONN_BE 0x10 /* Connection indicator int enable */
1387#define DISCON_BE 0x20 /* Disconnect indicator int enable */
1388#define SESSION_REQ_BE 0x40 /* Session Request int enable */
1389#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
1390
1391/* Bit masks for USB_FRAME */
1392
1393#define FRAME_NUMBER 0x7ff /* Frame number */
1394
1395/* Bit masks for USB_INDEX */
1396
1397#define SELECTED_ENDPOINT 0xf /* selected endpoint */
1398
1399/* Bit masks for USB_GLOBAL_CTL */
1400
1401#define GLOBAL_ENA 0x1 /* enables USB module */
1402#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
1403#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
1404#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
1405#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
1406#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
1407#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
1408#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
1409#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
1410#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
1411#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
1412#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
1413#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
1414#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
1415#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
1416
1417/* Bit masks for USB_OTG_DEV_CTL */
1418
1419#define SESSION 0x1 /* session indicator */
1420#define HOST_REQ 0x2 /* Host negotiation request */
1421#define HOST_MODE 0x4 /* indicates USBDRC is a host */
1422#define VBUS0 0x8 /* Vbus level indicator[0] */
1423#define VBUS1 0x10 /* Vbus level indicator[1] */
1424#define LSDEV 0x20 /* Low-speed indicator */
1425#define FSDEV 0x40 /* Full or High-speed indicator */
1426#define B_DEVICE 0x80 /* A' or 'B' device indicator */
1427
1428/* Bit masks for USB_OTG_VBUS_IRQ */
1429
1430#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
1431#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
1432#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
1433#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
1434#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
1435#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
1436
1437/* Bit masks for USB_OTG_VBUS_MASK */
1438
1439#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
1440#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
1441#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
1442#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
1443#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
1444#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
1445
1446/* Bit masks for USB_CSR0 */
1447
1448#define RXPKTRDY 0x1 /* data packet receive indicator */
1449#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
1450#define STALL_SENT 0x4 /* STALL handshake sent */
1451#define DATAEND 0x8 /* Data end indicator */
1452#define SETUPEND 0x10 /* Setup end */
1453#define SENDSTALL 0x20 /* Send STALL handshake */
1454#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
1455#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
1456#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
1457#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
1458#define SETUPPKT_H 0x8 /* send Setup token host mode */
1459#define ERROR_H 0x10 /* timeout error indicator host mode */
1460#define REQPKT_H 0x20 /* Request an IN transaction host mode */
1461#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
1462#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
1463
1464/* Bit masks for USB_COUNT0 */
1465
1466#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
1467
1468/* Bit masks for USB_NAKLIMIT0 */
1469
1470#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
1471
1472/* Bit masks for USB_TX_MAX_PACKET */
1473
1474#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
1475
1476/* Bit masks for USB_RX_MAX_PACKET */
1477
1478#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
1479
1480/* Bit masks for USB_TXCSR */
1481
1482#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
1483#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
1484#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
1485#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
1486#define STALL_SEND_T 0x10 /* issue a Stall handshake */
1487#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
1488#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
1489#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
1490#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
1491#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
1492#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
1493#define ISO_T 0x4000 /* enable Isochronous transfers */
1494#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
1495#define ERROR_TH 0x4 /* error condition host mode */
1496#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
1497#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
1498
1499/* Bit masks for USB_TXCOUNT */
1500
1501#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
1502
1503/* Bit masks for USB_RXCSR */
1504
1505#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
1506#define FIFO_FULL_R 0x2 /* FIFO not empty */
1507#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
1508#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
1509#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
1510#define STALL_SEND_R 0x20 /* issue a Stall handshake */
1511#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
1512#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
1513#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
1514#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
1515#define DISNYET_R 0x1000 /* disable Nyet handshakes */
1516#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
1517#define ISO_R 0x4000 /* enable Isochronous transfers */
1518#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
1519#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
1520#define REQPKT_RH 0x20 /* request an IN transaction host mode */
1521#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
1522#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
1523#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
1524#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
1525
1526/* Bit masks for USB_RXCOUNT */
1527
1528#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
1529
1530/* Bit masks for USB_TXTYPE */
1531
1532#define TARGET_EP_NO_T 0xf /* EP number */
1533#define PROTOCOL_T 0xc /* transfer type */
1534
1535/* Bit masks for USB_TXINTERVAL */
1536
1537#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
1538
1539/* Bit masks for USB_RXTYPE */
1540
1541#define TARGET_EP_NO_R 0xf /* EP number */
1542#define PROTOCOL_R 0xc /* transfer type */
1543
1544/* Bit masks for USB_RXINTERVAL */
1545
1546#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
1547
1548/* Bit masks for USB_DMA_INTERRUPT */
1549
1550#define DMA0_INT 0x1 /* DMA0 pending interrupt */
1551#define DMA1_INT 0x2 /* DMA1 pending interrupt */
1552#define DMA2_INT 0x4 /* DMA2 pending interrupt */
1553#define DMA3_INT 0x8 /* DMA3 pending interrupt */
1554#define DMA4_INT 0x10 /* DMA4 pending interrupt */
1555#define DMA5_INT 0x20 /* DMA5 pending interrupt */
1556#define DMA6_INT 0x40 /* DMA6 pending interrupt */
1557#define DMA7_INT 0x80 /* DMA7 pending interrupt */
1558
1559/* Bit masks for USB_DMAxCONTROL */
1560
1561#define DMA_ENA 0x1 /* DMA enable */
1562#define DIRECTION 0x2 /* direction of DMA transfer */
1563#define MODE 0x4 /* DMA Bus error */
1564#define INT_ENA 0x8 /* Interrupt enable */
1565#define EPNUM 0xf0 /* EP number */
1566#define BUSERROR 0x100 /* DMA Bus error */
1567
1568/* Bit masks for USB_DMAxADDRHIGH */
1569
1570#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
1571
1572/* Bit masks for USB_DMAxADDRLOW */
1573
1574#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
1575
1576/* Bit masks for USB_DMAxCOUNTHIGH */
1577
1578#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
1579
1580/* Bit masks for USB_DMAxCOUNTLOW */
1581
1582#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
1583
1584/* Bit masks for HMDMAx_CONTROL */
1585
1586#define HMDMAEN 0x1 /* Handshake MDMA Enable */
1587#define REP 0x2 /* Handshake MDMA Request Polarity */
1588#define UTE 0x8 /* Urgency Threshold Enable */
1589#define OIE 0x10 /* Overflow Interrupt Enable */
1590#define BDIE 0x20 /* Block Done Interrupt Enable */
1591#define MBDI 0x40 /* Mask Block Done Interrupt */
1592#define DRQ 0x300 /* Handshake MDMA Request Type */
1593#define RBC 0x1000 /* Force Reload of BCOUNT */
1594#define PS 0x2000 /* Pin Status */
1595#define OI 0x4000 /* Overflow Interrupt Generated */
1596#define BDI 0x8000 /* Block Done Interrupt Generated */
1597
1598/* ******************************************* */
1599/* MULTI BIT MACRO ENUMERATIONS */
1600/* ******************************************* */
1601
1602
1603#endif /* _DEF_BF548_H */ 404#endif /* _DEF_BF548_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF549.h b/arch/blackfin/mach-bf548/include/mach/defBF549.h
index f7f043560c6..d84dbe9a8f2 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF549.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF549.h
@@ -10,121 +10,13 @@
10/* Include all Core registers and bit definitions */ 10/* Include all Core registers and bit definitions */
11#include <asm/def_LPBlackfin.h> 11#include <asm/def_LPBlackfin.h>
12 12
13
14/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF549 */ 13/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF549 */
15 14
16/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */ 15/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
17#include "defBF54x_base.h" 16#include "defBF54x_base.h"
18 17
19/* The following are the #defines needed by ADSP-BF549 that are not in the common header */ 18/* The BF549 is like the BF544, but has MXVR */
20 19#include "defBF547.h"
21/* Timer Registers */
22
23#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */
24#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */
25#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */
26#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */
27#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */
28#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */
29#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */
30#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */
31#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */
32#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */
33#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */
34#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */
35
36/* Timer Group of 3 Registers */
37
38#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */
39#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */
40#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */
41
42/* SPORT0 Registers */
43
44#define SPORT0_TCR1 0xffc00800 /* SPORT0 Transmit Configuration 1 Register */
45#define SPORT0_TCR2 0xffc00804 /* SPORT0 Transmit Configuration 2 Register */
46#define SPORT0_TCLKDIV 0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */
47#define SPORT0_TFSDIV 0xffc0080c /* SPORT0 Transmit Frame Sync Divider Register */
48#define SPORT0_TX 0xffc00810 /* SPORT0 Transmit Data Register */
49#define SPORT0_RX 0xffc00818 /* SPORT0 Receive Data Register */
50#define SPORT0_RCR1 0xffc00820 /* SPORT0 Receive Configuration 1 Register */
51#define SPORT0_RCR2 0xffc00824 /* SPORT0 Receive Configuration 2 Register */
52#define SPORT0_RCLKDIV 0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */
53#define SPORT0_RFSDIV 0xffc0082c /* SPORT0 Receive Frame Sync Divider Register */
54#define SPORT0_STAT 0xffc00830 /* SPORT0 Status Register */
55#define SPORT0_CHNL 0xffc00834 /* SPORT0 Current Channel Register */
56#define SPORT0_MCMC1 0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */
57#define SPORT0_MCMC2 0xffc0083c /* SPORT0 Multi channel Configuration Register 2 */
58#define SPORT0_MTCS0 0xffc00840 /* SPORT0 Multi channel Transmit Select Register 0 */
59#define SPORT0_MTCS1 0xffc00844 /* SPORT0 Multi channel Transmit Select Register 1 */
60#define SPORT0_MTCS2 0xffc00848 /* SPORT0 Multi channel Transmit Select Register 2 */
61#define SPORT0_MTCS3 0xffc0084c /* SPORT0 Multi channel Transmit Select Register 3 */
62#define SPORT0_MRCS0 0xffc00850 /* SPORT0 Multi channel Receive Select Register 0 */
63#define SPORT0_MRCS1 0xffc00854 /* SPORT0 Multi channel Receive Select Register 1 */
64#define SPORT0_MRCS2 0xffc00858 /* SPORT0 Multi channel Receive Select Register 2 */
65#define SPORT0_MRCS3 0xffc0085c /* SPORT0 Multi channel Receive Select Register 3 */
66
67/* EPPI0 Registers */
68
69#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */
70#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */
71#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */
72#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */
73#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */
74#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */
75#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */
76#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */
77#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */
78#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
79#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
80#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
81#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
82#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */
83
84/* UART2 Registers */
85
86#define UART2_DLL 0xffc02100 /* Divisor Latch Low Byte */
87#define UART2_DLH 0xffc02104 /* Divisor Latch High Byte */
88#define UART2_GCTL 0xffc02108 /* Global Control Register */
89#define UART2_LCR 0xffc0210c /* Line Control Register */
90#define UART2_MCR 0xffc02110 /* Modem Control Register */
91#define UART2_LSR 0xffc02114 /* Line Status Register */
92#define UART2_MSR 0xffc02118 /* Modem Status Register */
93#define UART2_SCR 0xffc0211c /* Scratch Register */
94#define UART2_IER_SET 0xffc02120 /* Interrupt Enable Register Set */
95#define UART2_IER_CLEAR 0xffc02124 /* Interrupt Enable Register Clear */
96#define UART2_RBR 0xffc0212c /* Receive Buffer Register */
97
98/* Two Wire Interface Registers (TWI1) */
99
100#define TWI1_REGBASE 0xffc02200
101#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
102#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
103#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */
104#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
105#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
106#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */
107#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
108#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
109#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
110#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
111#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */
112#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
113#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
114#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
115#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */
116#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */
117
118/* SPI2 Registers */
119
120#define SPI2_REGBASE 0xffc02400
121#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */
122#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */
123#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */
124#define SPI2_TDBR 0xffc0240c /* SPI2 Transmit Data Buffer Register */
125#define SPI2_RDBR 0xffc02410 /* SPI2 Receive Data Buffer Register */
126#define SPI2_BAUD 0xffc02414 /* SPI2 Baud Rate Register */
127#define SPI2_SHADOW 0xffc02418 /* SPI2 Receive Data Buffer Shadow Register */
128 20
129/* MXVR Registers */ 21/* MXVR Registers */
130 22
@@ -296,879 +188,6 @@
296#define MXVR_PIN_CTL 0xffc028dc /* MXVR Pin Control Register */ 188#define MXVR_PIN_CTL 0xffc028dc /* MXVR Pin Control Register */
297#define MXVR_SCLK_CNT 0xffc028e0 /* MXVR System Clock Counter Register */ 189#define MXVR_SCLK_CNT 0xffc028e0 /* MXVR System Clock Counter Register */
298 190
299/* CAN Controller 1 Config 1 Registers */
300
301#define CAN1_MC1 0xffc03200 /* CAN Controller 1 Mailbox Configuration Register 1 */
302#define CAN1_MD1 0xffc03204 /* CAN Controller 1 Mailbox Direction Register 1 */
303#define CAN1_TRS1 0xffc03208 /* CAN Controller 1 Transmit Request Set Register 1 */
304#define CAN1_TRR1 0xffc0320c /* CAN Controller 1 Transmit Request Reset Register 1 */
305#define CAN1_TA1 0xffc03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */
306#define CAN1_AA1 0xffc03214 /* CAN Controller 1 Abort Acknowledge Register 1 */
307#define CAN1_RMP1 0xffc03218 /* CAN Controller 1 Receive Message Pending Register 1 */
308#define CAN1_RML1 0xffc0321c /* CAN Controller 1 Receive Message Lost Register 1 */
309#define CAN1_MBTIF1 0xffc03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
310#define CAN1_MBRIF1 0xffc03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
311#define CAN1_MBIM1 0xffc03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
312#define CAN1_RFH1 0xffc0322c /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
313#define CAN1_OPSS1 0xffc03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
314
315/* CAN Controller 1 Config 2 Registers */
316
317#define CAN1_MC2 0xffc03240 /* CAN Controller 1 Mailbox Configuration Register 2 */
318#define CAN1_MD2 0xffc03244 /* CAN Controller 1 Mailbox Direction Register 2 */
319#define CAN1_TRS2 0xffc03248 /* CAN Controller 1 Transmit Request Set Register 2 */
320#define CAN1_TRR2 0xffc0324c /* CAN Controller 1 Transmit Request Reset Register 2 */
321#define CAN1_TA2 0xffc03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */
322#define CAN1_AA2 0xffc03254 /* CAN Controller 1 Abort Acknowledge Register 2 */
323#define CAN1_RMP2 0xffc03258 /* CAN Controller 1 Receive Message Pending Register 2 */
324#define CAN1_RML2 0xffc0325c /* CAN Controller 1 Receive Message Lost Register 2 */
325#define CAN1_MBTIF2 0xffc03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
326#define CAN1_MBRIF2 0xffc03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
327#define CAN1_MBIM2 0xffc03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
328#define CAN1_RFH2 0xffc0326c /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
329#define CAN1_OPSS2 0xffc03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
330
331/* CAN Controller 1 Clock/Interrupt/Counter Registers */
332
333#define CAN1_CLOCK 0xffc03280 /* CAN Controller 1 Clock Register */
334#define CAN1_TIMING 0xffc03284 /* CAN Controller 1 Timing Register */
335#define CAN1_DEBUG 0xffc03288 /* CAN Controller 1 Debug Register */
336#define CAN1_STATUS 0xffc0328c /* CAN Controller 1 Global Status Register */
337#define CAN1_CEC 0xffc03290 /* CAN Controller 1 Error Counter Register */
338#define CAN1_GIS 0xffc03294 /* CAN Controller 1 Global Interrupt Status Register */
339#define CAN1_GIM 0xffc03298 /* CAN Controller 1 Global Interrupt Mask Register */
340#define CAN1_GIF 0xffc0329c /* CAN Controller 1 Global Interrupt Flag Register */
341#define CAN1_CONTROL 0xffc032a0 /* CAN Controller 1 Master Control Register */
342#define CAN1_INTR 0xffc032a4 /* CAN Controller 1 Interrupt Pending Register */
343#define CAN1_MBTD 0xffc032ac /* CAN Controller 1 Mailbox Temporary Disable Register */
344#define CAN1_EWR 0xffc032b0 /* CAN Controller 1 Programmable Warning Level Register */
345#define CAN1_ESR 0xffc032b4 /* CAN Controller 1 Error Status Register */
346#define CAN1_UCCNT 0xffc032c4 /* CAN Controller 1 Universal Counter Register */
347#define CAN1_UCRC 0xffc032c8 /* CAN Controller 1 Universal Counter Force Reload Register */
348#define CAN1_UCCNF 0xffc032cc /* CAN Controller 1 Universal Counter Configuration Register */
349
350/* CAN Controller 1 Mailbox Acceptance Registers */
351
352#define CAN1_AM00L 0xffc03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
353#define CAN1_AM00H 0xffc03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
354#define CAN1_AM01L 0xffc03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
355#define CAN1_AM01H 0xffc0330c /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
356#define CAN1_AM02L 0xffc03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
357#define CAN1_AM02H 0xffc03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
358#define CAN1_AM03L 0xffc03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
359#define CAN1_AM03H 0xffc0331c /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
360#define CAN1_AM04L 0xffc03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
361#define CAN1_AM04H 0xffc03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
362#define CAN1_AM05L 0xffc03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
363#define CAN1_AM05H 0xffc0332c /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
364#define CAN1_AM06L 0xffc03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
365#define CAN1_AM06H 0xffc03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
366#define CAN1_AM07L 0xffc03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
367#define CAN1_AM07H 0xffc0333c /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
368#define CAN1_AM08L 0xffc03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
369#define CAN1_AM08H 0xffc03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
370#define CAN1_AM09L 0xffc03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
371#define CAN1_AM09H 0xffc0334c /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
372#define CAN1_AM10L 0xffc03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
373#define CAN1_AM10H 0xffc03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
374#define CAN1_AM11L 0xffc03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
375#define CAN1_AM11H 0xffc0335c /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
376#define CAN1_AM12L 0xffc03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
377#define CAN1_AM12H 0xffc03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
378#define CAN1_AM13L 0xffc03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
379#define CAN1_AM13H 0xffc0336c /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
380#define CAN1_AM14L 0xffc03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
381#define CAN1_AM14H 0xffc03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
382#define CAN1_AM15L 0xffc03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
383#define CAN1_AM15H 0xffc0337c /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
384
385/* CAN Controller 1 Mailbox Acceptance Registers */
386
387#define CAN1_AM16L 0xffc03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
388#define CAN1_AM16H 0xffc03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
389#define CAN1_AM17L 0xffc03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
390#define CAN1_AM17H 0xffc0338c /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
391#define CAN1_AM18L 0xffc03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
392#define CAN1_AM18H 0xffc03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
393#define CAN1_AM19L 0xffc03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
394#define CAN1_AM19H 0xffc0339c /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
395#define CAN1_AM20L 0xffc033a0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
396#define CAN1_AM20H 0xffc033a4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
397#define CAN1_AM21L 0xffc033a8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
398#define CAN1_AM21H 0xffc033ac /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
399#define CAN1_AM22L 0xffc033b0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
400#define CAN1_AM22H 0xffc033b4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
401#define CAN1_AM23L 0xffc033b8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
402#define CAN1_AM23H 0xffc033bc /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
403#define CAN1_AM24L 0xffc033c0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
404#define CAN1_AM24H 0xffc033c4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
405#define CAN1_AM25L 0xffc033c8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
406#define CAN1_AM25H 0xffc033cc /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
407#define CAN1_AM26L 0xffc033d0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
408#define CAN1_AM26H 0xffc033d4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
409#define CAN1_AM27L 0xffc033d8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
410#define CAN1_AM27H 0xffc033dc /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
411#define CAN1_AM28L 0xffc033e0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
412#define CAN1_AM28H 0xffc033e4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
413#define CAN1_AM29L 0xffc033e8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
414#define CAN1_AM29H 0xffc033ec /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
415#define CAN1_AM30L 0xffc033f0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
416#define CAN1_AM30H 0xffc033f4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
417#define CAN1_AM31L 0xffc033f8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
418#define CAN1_AM31H 0xffc033fc /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
419
420/* CAN Controller 1 Mailbox Data Registers */
421
422#define CAN1_MB00_DATA0 0xffc03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */
423#define CAN1_MB00_DATA1 0xffc03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */
424#define CAN1_MB00_DATA2 0xffc03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */
425#define CAN1_MB00_DATA3 0xffc0340c /* CAN Controller 1 Mailbox 0 Data 3 Register */
426#define CAN1_MB00_LENGTH 0xffc03410 /* CAN Controller 1 Mailbox 0 Length Register */
427#define CAN1_MB00_TIMESTAMP 0xffc03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */
428#define CAN1_MB00_ID0 0xffc03418 /* CAN Controller 1 Mailbox 0 ID0 Register */
429#define CAN1_MB00_ID1 0xffc0341c /* CAN Controller 1 Mailbox 0 ID1 Register */
430#define CAN1_MB01_DATA0 0xffc03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */
431#define CAN1_MB01_DATA1 0xffc03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */
432#define CAN1_MB01_DATA2 0xffc03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */
433#define CAN1_MB01_DATA3 0xffc0342c /* CAN Controller 1 Mailbox 1 Data 3 Register */
434#define CAN1_MB01_LENGTH 0xffc03430 /* CAN Controller 1 Mailbox 1 Length Register */
435#define CAN1_MB01_TIMESTAMP 0xffc03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */
436#define CAN1_MB01_ID0 0xffc03438 /* CAN Controller 1 Mailbox 1 ID0 Register */
437#define CAN1_MB01_ID1 0xffc0343c /* CAN Controller 1 Mailbox 1 ID1 Register */
438#define CAN1_MB02_DATA0 0xffc03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */
439#define CAN1_MB02_DATA1 0xffc03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */
440#define CAN1_MB02_DATA2 0xffc03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */
441#define CAN1_MB02_DATA3 0xffc0344c /* CAN Controller 1 Mailbox 2 Data 3 Register */
442#define CAN1_MB02_LENGTH 0xffc03450 /* CAN Controller 1 Mailbox 2 Length Register */
443#define CAN1_MB02_TIMESTAMP 0xffc03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */
444#define CAN1_MB02_ID0 0xffc03458 /* CAN Controller 1 Mailbox 2 ID0 Register */
445#define CAN1_MB02_ID1 0xffc0345c /* CAN Controller 1 Mailbox 2 ID1 Register */
446#define CAN1_MB03_DATA0 0xffc03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */
447#define CAN1_MB03_DATA1 0xffc03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */
448#define CAN1_MB03_DATA2 0xffc03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */
449#define CAN1_MB03_DATA3 0xffc0346c /* CAN Controller 1 Mailbox 3 Data 3 Register */
450#define CAN1_MB03_LENGTH 0xffc03470 /* CAN Controller 1 Mailbox 3 Length Register */
451#define CAN1_MB03_TIMESTAMP 0xffc03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */
452#define CAN1_MB03_ID0 0xffc03478 /* CAN Controller 1 Mailbox 3 ID0 Register */
453#define CAN1_MB03_ID1 0xffc0347c /* CAN Controller 1 Mailbox 3 ID1 Register */
454#define CAN1_MB04_DATA0 0xffc03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */
455#define CAN1_MB04_DATA1 0xffc03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */
456#define CAN1_MB04_DATA2 0xffc03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */
457#define CAN1_MB04_DATA3 0xffc0348c /* CAN Controller 1 Mailbox 4 Data 3 Register */
458#define CAN1_MB04_LENGTH 0xffc03490 /* CAN Controller 1 Mailbox 4 Length Register */
459#define CAN1_MB04_TIMESTAMP 0xffc03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */
460#define CAN1_MB04_ID0 0xffc03498 /* CAN Controller 1 Mailbox 4 ID0 Register */
461#define CAN1_MB04_ID1 0xffc0349c /* CAN Controller 1 Mailbox 4 ID1 Register */
462#define CAN1_MB05_DATA0 0xffc034a0 /* CAN Controller 1 Mailbox 5 Data 0 Register */
463#define CAN1_MB05_DATA1 0xffc034a4 /* CAN Controller 1 Mailbox 5 Data 1 Register */
464#define CAN1_MB05_DATA2 0xffc034a8 /* CAN Controller 1 Mailbox 5 Data 2 Register */
465#define CAN1_MB05_DATA3 0xffc034ac /* CAN Controller 1 Mailbox 5 Data 3 Register */
466#define CAN1_MB05_LENGTH 0xffc034b0 /* CAN Controller 1 Mailbox 5 Length Register */
467#define CAN1_MB05_TIMESTAMP 0xffc034b4 /* CAN Controller 1 Mailbox 5 Timestamp Register */
468#define CAN1_MB05_ID0 0xffc034b8 /* CAN Controller 1 Mailbox 5 ID0 Register */
469#define CAN1_MB05_ID1 0xffc034bc /* CAN Controller 1 Mailbox 5 ID1 Register */
470#define CAN1_MB06_DATA0 0xffc034c0 /* CAN Controller 1 Mailbox 6 Data 0 Register */
471#define CAN1_MB06_DATA1 0xffc034c4 /* CAN Controller 1 Mailbox 6 Data 1 Register */
472#define CAN1_MB06_DATA2 0xffc034c8 /* CAN Controller 1 Mailbox 6 Data 2 Register */
473#define CAN1_MB06_DATA3 0xffc034cc /* CAN Controller 1 Mailbox 6 Data 3 Register */
474#define CAN1_MB06_LENGTH 0xffc034d0 /* CAN Controller 1 Mailbox 6 Length Register */
475#define CAN1_MB06_TIMESTAMP 0xffc034d4 /* CAN Controller 1 Mailbox 6 Timestamp Register */
476#define CAN1_MB06_ID0 0xffc034d8 /* CAN Controller 1 Mailbox 6 ID0 Register */
477#define CAN1_MB06_ID1 0xffc034dc /* CAN Controller 1 Mailbox 6 ID1 Register */
478#define CAN1_MB07_DATA0 0xffc034e0 /* CAN Controller 1 Mailbox 7 Data 0 Register */
479#define CAN1_MB07_DATA1 0xffc034e4 /* CAN Controller 1 Mailbox 7 Data 1 Register */
480#define CAN1_MB07_DATA2 0xffc034e8 /* CAN Controller 1 Mailbox 7 Data 2 Register */
481#define CAN1_MB07_DATA3 0xffc034ec /* CAN Controller 1 Mailbox 7 Data 3 Register */
482#define CAN1_MB07_LENGTH 0xffc034f0 /* CAN Controller 1 Mailbox 7 Length Register */
483#define CAN1_MB07_TIMESTAMP 0xffc034f4 /* CAN Controller 1 Mailbox 7 Timestamp Register */
484#define CAN1_MB07_ID0 0xffc034f8 /* CAN Controller 1 Mailbox 7 ID0 Register */
485#define CAN1_MB07_ID1 0xffc034fc /* CAN Controller 1 Mailbox 7 ID1 Register */
486#define CAN1_MB08_DATA0 0xffc03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */
487#define CAN1_MB08_DATA1 0xffc03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */
488#define CAN1_MB08_DATA2 0xffc03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */
489#define CAN1_MB08_DATA3 0xffc0350c /* CAN Controller 1 Mailbox 8 Data 3 Register */
490#define CAN1_MB08_LENGTH 0xffc03510 /* CAN Controller 1 Mailbox 8 Length Register */
491#define CAN1_MB08_TIMESTAMP 0xffc03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */
492#define CAN1_MB08_ID0 0xffc03518 /* CAN Controller 1 Mailbox 8 ID0 Register */
493#define CAN1_MB08_ID1 0xffc0351c /* CAN Controller 1 Mailbox 8 ID1 Register */
494#define CAN1_MB09_DATA0 0xffc03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */
495#define CAN1_MB09_DATA1 0xffc03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */
496#define CAN1_MB09_DATA2 0xffc03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */
497#define CAN1_MB09_DATA3 0xffc0352c /* CAN Controller 1 Mailbox 9 Data 3 Register */
498#define CAN1_MB09_LENGTH 0xffc03530 /* CAN Controller 1 Mailbox 9 Length Register */
499#define CAN1_MB09_TIMESTAMP 0xffc03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */
500#define CAN1_MB09_ID0 0xffc03538 /* CAN Controller 1 Mailbox 9 ID0 Register */
501#define CAN1_MB09_ID1 0xffc0353c /* CAN Controller 1 Mailbox 9 ID1 Register */
502#define CAN1_MB10_DATA0 0xffc03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */
503#define CAN1_MB10_DATA1 0xffc03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */
504#define CAN1_MB10_DATA2 0xffc03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */
505#define CAN1_MB10_DATA3 0xffc0354c /* CAN Controller 1 Mailbox 10 Data 3 Register */
506#define CAN1_MB10_LENGTH 0xffc03550 /* CAN Controller 1 Mailbox 10 Length Register */
507#define CAN1_MB10_TIMESTAMP 0xffc03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */
508#define CAN1_MB10_ID0 0xffc03558 /* CAN Controller 1 Mailbox 10 ID0 Register */
509#define CAN1_MB10_ID1 0xffc0355c /* CAN Controller 1 Mailbox 10 ID1 Register */
510#define CAN1_MB11_DATA0 0xffc03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */
511#define CAN1_MB11_DATA1 0xffc03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */
512#define CAN1_MB11_DATA2 0xffc03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */
513#define CAN1_MB11_DATA3 0xffc0356c /* CAN Controller 1 Mailbox 11 Data 3 Register */
514#define CAN1_MB11_LENGTH 0xffc03570 /* CAN Controller 1 Mailbox 11 Length Register */
515#define CAN1_MB11_TIMESTAMP 0xffc03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */
516#define CAN1_MB11_ID0 0xffc03578 /* CAN Controller 1 Mailbox 11 ID0 Register */
517#define CAN1_MB11_ID1 0xffc0357c /* CAN Controller 1 Mailbox 11 ID1 Register */
518#define CAN1_MB12_DATA0 0xffc03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */
519#define CAN1_MB12_DATA1 0xffc03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */
520#define CAN1_MB12_DATA2 0xffc03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */
521#define CAN1_MB12_DATA3 0xffc0358c /* CAN Controller 1 Mailbox 12 Data 3 Register */
522#define CAN1_MB12_LENGTH 0xffc03590 /* CAN Controller 1 Mailbox 12 Length Register */
523#define CAN1_MB12_TIMESTAMP 0xffc03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */
524#define CAN1_MB12_ID0 0xffc03598 /* CAN Controller 1 Mailbox 12 ID0 Register */
525#define CAN1_MB12_ID1 0xffc0359c /* CAN Controller 1 Mailbox 12 ID1 Register */
526#define CAN1_MB13_DATA0 0xffc035a0 /* CAN Controller 1 Mailbox 13 Data 0 Register */
527#define CAN1_MB13_DATA1 0xffc035a4 /* CAN Controller 1 Mailbox 13 Data 1 Register */
528#define CAN1_MB13_DATA2 0xffc035a8 /* CAN Controller 1 Mailbox 13 Data 2 Register */
529#define CAN1_MB13_DATA3 0xffc035ac /* CAN Controller 1 Mailbox 13 Data 3 Register */
530#define CAN1_MB13_LENGTH 0xffc035b0 /* CAN Controller 1 Mailbox 13 Length Register */
531#define CAN1_MB13_TIMESTAMP 0xffc035b4 /* CAN Controller 1 Mailbox 13 Timestamp Register */
532#define CAN1_MB13_ID0 0xffc035b8 /* CAN Controller 1 Mailbox 13 ID0 Register */
533#define CAN1_MB13_ID1 0xffc035bc /* CAN Controller 1 Mailbox 13 ID1 Register */
534#define CAN1_MB14_DATA0 0xffc035c0 /* CAN Controller 1 Mailbox 14 Data 0 Register */
535#define CAN1_MB14_DATA1 0xffc035c4 /* CAN Controller 1 Mailbox 14 Data 1 Register */
536#define CAN1_MB14_DATA2 0xffc035c8 /* CAN Controller 1 Mailbox 14 Data 2 Register */
537#define CAN1_MB14_DATA3 0xffc035cc /* CAN Controller 1 Mailbox 14 Data 3 Register */
538#define CAN1_MB14_LENGTH 0xffc035d0 /* CAN Controller 1 Mailbox 14 Length Register */
539#define CAN1_MB14_TIMESTAMP 0xffc035d4 /* CAN Controller 1 Mailbox 14 Timestamp Register */
540#define CAN1_MB14_ID0 0xffc035d8 /* CAN Controller 1 Mailbox 14 ID0 Register */
541#define CAN1_MB14_ID1 0xffc035dc /* CAN Controller 1 Mailbox 14 ID1 Register */
542#define CAN1_MB15_DATA0 0xffc035e0 /* CAN Controller 1 Mailbox 15 Data 0 Register */
543#define CAN1_MB15_DATA1 0xffc035e4 /* CAN Controller 1 Mailbox 15 Data 1 Register */
544#define CAN1_MB15_DATA2 0xffc035e8 /* CAN Controller 1 Mailbox 15 Data 2 Register */
545#define CAN1_MB15_DATA3 0xffc035ec /* CAN Controller 1 Mailbox 15 Data 3 Register */
546#define CAN1_MB15_LENGTH 0xffc035f0 /* CAN Controller 1 Mailbox 15 Length Register */
547#define CAN1_MB15_TIMESTAMP 0xffc035f4 /* CAN Controller 1 Mailbox 15 Timestamp Register */
548#define CAN1_MB15_ID0 0xffc035f8 /* CAN Controller 1 Mailbox 15 ID0 Register */
549#define CAN1_MB15_ID1 0xffc035fc /* CAN Controller 1 Mailbox 15 ID1 Register */
550
551/* CAN Controller 1 Mailbox Data Registers */
552
553#define CAN1_MB16_DATA0 0xffc03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */
554#define CAN1_MB16_DATA1 0xffc03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */
555#define CAN1_MB16_DATA2 0xffc03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */
556#define CAN1_MB16_DATA3 0xffc0360c /* CAN Controller 1 Mailbox 16 Data 3 Register */
557#define CAN1_MB16_LENGTH 0xffc03610 /* CAN Controller 1 Mailbox 16 Length Register */
558#define CAN1_MB16_TIMESTAMP 0xffc03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */
559#define CAN1_MB16_ID0 0xffc03618 /* CAN Controller 1 Mailbox 16 ID0 Register */
560#define CAN1_MB16_ID1 0xffc0361c /* CAN Controller 1 Mailbox 16 ID1 Register */
561#define CAN1_MB17_DATA0 0xffc03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */
562#define CAN1_MB17_DATA1 0xffc03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */
563#define CAN1_MB17_DATA2 0xffc03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */
564#define CAN1_MB17_DATA3 0xffc0362c /* CAN Controller 1 Mailbox 17 Data 3 Register */
565#define CAN1_MB17_LENGTH 0xffc03630 /* CAN Controller 1 Mailbox 17 Length Register */
566#define CAN1_MB17_TIMESTAMP 0xffc03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */
567#define CAN1_MB17_ID0 0xffc03638 /* CAN Controller 1 Mailbox 17 ID0 Register */
568#define CAN1_MB17_ID1 0xffc0363c /* CAN Controller 1 Mailbox 17 ID1 Register */
569#define CAN1_MB18_DATA0 0xffc03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */
570#define CAN1_MB18_DATA1 0xffc03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */
571#define CAN1_MB18_DATA2 0xffc03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */
572#define CAN1_MB18_DATA3 0xffc0364c /* CAN Controller 1 Mailbox 18 Data 3 Register */
573#define CAN1_MB18_LENGTH 0xffc03650 /* CAN Controller 1 Mailbox 18 Length Register */
574#define CAN1_MB18_TIMESTAMP 0xffc03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */
575#define CAN1_MB18_ID0 0xffc03658 /* CAN Controller 1 Mailbox 18 ID0 Register */
576#define CAN1_MB18_ID1 0xffc0365c /* CAN Controller 1 Mailbox 18 ID1 Register */
577#define CAN1_MB19_DATA0 0xffc03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */
578#define CAN1_MB19_DATA1 0xffc03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */
579#define CAN1_MB19_DATA2 0xffc03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */
580#define CAN1_MB19_DATA3 0xffc0366c /* CAN Controller 1 Mailbox 19 Data 3 Register */
581#define CAN1_MB19_LENGTH 0xffc03670 /* CAN Controller 1 Mailbox 19 Length Register */
582#define CAN1_MB19_TIMESTAMP 0xffc03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */
583#define CAN1_MB19_ID0 0xffc03678 /* CAN Controller 1 Mailbox 19 ID0 Register */
584#define CAN1_MB19_ID1 0xffc0367c /* CAN Controller 1 Mailbox 19 ID1 Register */
585#define CAN1_MB20_DATA0 0xffc03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */
586#define CAN1_MB20_DATA1 0xffc03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */
587#define CAN1_MB20_DATA2 0xffc03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */
588#define CAN1_MB20_DATA3 0xffc0368c /* CAN Controller 1 Mailbox 20 Data 3 Register */
589#define CAN1_MB20_LENGTH 0xffc03690 /* CAN Controller 1 Mailbox 20 Length Register */
590#define CAN1_MB20_TIMESTAMP 0xffc03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */
591#define CAN1_MB20_ID0 0xffc03698 /* CAN Controller 1 Mailbox 20 ID0 Register */
592#define CAN1_MB20_ID1 0xffc0369c /* CAN Controller 1 Mailbox 20 ID1 Register */
593#define CAN1_MB21_DATA0 0xffc036a0 /* CAN Controller 1 Mailbox 21 Data 0 Register */
594#define CAN1_MB21_DATA1 0xffc036a4 /* CAN Controller 1 Mailbox 21 Data 1 Register */
595#define CAN1_MB21_DATA2 0xffc036a8 /* CAN Controller 1 Mailbox 21 Data 2 Register */
596#define CAN1_MB21_DATA3 0xffc036ac /* CAN Controller 1 Mailbox 21 Data 3 Register */
597#define CAN1_MB21_LENGTH 0xffc036b0 /* CAN Controller 1 Mailbox 21 Length Register */
598#define CAN1_MB21_TIMESTAMP 0xffc036b4 /* CAN Controller 1 Mailbox 21 Timestamp Register */
599#define CAN1_MB21_ID0 0xffc036b8 /* CAN Controller 1 Mailbox 21 ID0 Register */
600#define CAN1_MB21_ID1 0xffc036bc /* CAN Controller 1 Mailbox 21 ID1 Register */
601#define CAN1_MB22_DATA0 0xffc036c0 /* CAN Controller 1 Mailbox 22 Data 0 Register */
602#define CAN1_MB22_DATA1 0xffc036c4 /* CAN Controller 1 Mailbox 22 Data 1 Register */
603#define CAN1_MB22_DATA2 0xffc036c8 /* CAN Controller 1 Mailbox 22 Data 2 Register */
604#define CAN1_MB22_DATA3 0xffc036cc /* CAN Controller 1 Mailbox 22 Data 3 Register */
605#define CAN1_MB22_LENGTH 0xffc036d0 /* CAN Controller 1 Mailbox 22 Length Register */
606#define CAN1_MB22_TIMESTAMP 0xffc036d4 /* CAN Controller 1 Mailbox 22 Timestamp Register */
607#define CAN1_MB22_ID0 0xffc036d8 /* CAN Controller 1 Mailbox 22 ID0 Register */
608#define CAN1_MB22_ID1 0xffc036dc /* CAN Controller 1 Mailbox 22 ID1 Register */
609#define CAN1_MB23_DATA0 0xffc036e0 /* CAN Controller 1 Mailbox 23 Data 0 Register */
610#define CAN1_MB23_DATA1 0xffc036e4 /* CAN Controller 1 Mailbox 23 Data 1 Register */
611#define CAN1_MB23_DATA2 0xffc036e8 /* CAN Controller 1 Mailbox 23 Data 2 Register */
612#define CAN1_MB23_DATA3 0xffc036ec /* CAN Controller 1 Mailbox 23 Data 3 Register */
613#define CAN1_MB23_LENGTH 0xffc036f0 /* CAN Controller 1 Mailbox 23 Length Register */
614#define CAN1_MB23_TIMESTAMP 0xffc036f4 /* CAN Controller 1 Mailbox 23 Timestamp Register */
615#define CAN1_MB23_ID0 0xffc036f8 /* CAN Controller 1 Mailbox 23 ID0 Register */
616#define CAN1_MB23_ID1 0xffc036fc /* CAN Controller 1 Mailbox 23 ID1 Register */
617#define CAN1_MB24_DATA0 0xffc03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */
618#define CAN1_MB24_DATA1 0xffc03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */
619#define CAN1_MB24_DATA2 0xffc03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */
620#define CAN1_MB24_DATA3 0xffc0370c /* CAN Controller 1 Mailbox 24 Data 3 Register */
621#define CAN1_MB24_LENGTH 0xffc03710 /* CAN Controller 1 Mailbox 24 Length Register */
622#define CAN1_MB24_TIMESTAMP 0xffc03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */
623#define CAN1_MB24_ID0 0xffc03718 /* CAN Controller 1 Mailbox 24 ID0 Register */
624#define CAN1_MB24_ID1 0xffc0371c /* CAN Controller 1 Mailbox 24 ID1 Register */
625#define CAN1_MB25_DATA0 0xffc03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */
626#define CAN1_MB25_DATA1 0xffc03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */
627#define CAN1_MB25_DATA2 0xffc03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */
628#define CAN1_MB25_DATA3 0xffc0372c /* CAN Controller 1 Mailbox 25 Data 3 Register */
629#define CAN1_MB25_LENGTH 0xffc03730 /* CAN Controller 1 Mailbox 25 Length Register */
630#define CAN1_MB25_TIMESTAMP 0xffc03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */
631#define CAN1_MB25_ID0 0xffc03738 /* CAN Controller 1 Mailbox 25 ID0 Register */
632#define CAN1_MB25_ID1 0xffc0373c /* CAN Controller 1 Mailbox 25 ID1 Register */
633#define CAN1_MB26_DATA0 0xffc03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */
634#define CAN1_MB26_DATA1 0xffc03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */
635#define CAN1_MB26_DATA2 0xffc03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */
636#define CAN1_MB26_DATA3 0xffc0374c /* CAN Controller 1 Mailbox 26 Data 3 Register */
637#define CAN1_MB26_LENGTH 0xffc03750 /* CAN Controller 1 Mailbox 26 Length Register */
638#define CAN1_MB26_TIMESTAMP 0xffc03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */
639#define CAN1_MB26_ID0 0xffc03758 /* CAN Controller 1 Mailbox 26 ID0 Register */
640#define CAN1_MB26_ID1 0xffc0375c /* CAN Controller 1 Mailbox 26 ID1 Register */
641#define CAN1_MB27_DATA0 0xffc03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */
642#define CAN1_MB27_DATA1 0xffc03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */
643#define CAN1_MB27_DATA2 0xffc03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */
644#define CAN1_MB27_DATA3 0xffc0376c /* CAN Controller 1 Mailbox 27 Data 3 Register */
645#define CAN1_MB27_LENGTH 0xffc03770 /* CAN Controller 1 Mailbox 27 Length Register */
646#define CAN1_MB27_TIMESTAMP 0xffc03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */
647#define CAN1_MB27_ID0 0xffc03778 /* CAN Controller 1 Mailbox 27 ID0 Register */
648#define CAN1_MB27_ID1 0xffc0377c /* CAN Controller 1 Mailbox 27 ID1 Register */
649#define CAN1_MB28_DATA0 0xffc03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */
650#define CAN1_MB28_DATA1 0xffc03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */
651#define CAN1_MB28_DATA2 0xffc03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */
652#define CAN1_MB28_DATA3 0xffc0378c /* CAN Controller 1 Mailbox 28 Data 3 Register */
653#define CAN1_MB28_LENGTH 0xffc03790 /* CAN Controller 1 Mailbox 28 Length Register */
654#define CAN1_MB28_TIMESTAMP 0xffc03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */
655#define CAN1_MB28_ID0 0xffc03798 /* CAN Controller 1 Mailbox 28 ID0 Register */
656#define CAN1_MB28_ID1 0xffc0379c /* CAN Controller 1 Mailbox 28 ID1 Register */
657#define CAN1_MB29_DATA0 0xffc037a0 /* CAN Controller 1 Mailbox 29 Data 0 Register */
658#define CAN1_MB29_DATA1 0xffc037a4 /* CAN Controller 1 Mailbox 29 Data 1 Register */
659#define CAN1_MB29_DATA2 0xffc037a8 /* CAN Controller 1 Mailbox 29 Data 2 Register */
660#define CAN1_MB29_DATA3 0xffc037ac /* CAN Controller 1 Mailbox 29 Data 3 Register */
661#define CAN1_MB29_LENGTH 0xffc037b0 /* CAN Controller 1 Mailbox 29 Length Register */
662#define CAN1_MB29_TIMESTAMP 0xffc037b4 /* CAN Controller 1 Mailbox 29 Timestamp Register */
663#define CAN1_MB29_ID0 0xffc037b8 /* CAN Controller 1 Mailbox 29 ID0 Register */
664#define CAN1_MB29_ID1 0xffc037bc /* CAN Controller 1 Mailbox 29 ID1 Register */
665#define CAN1_MB30_DATA0 0xffc037c0 /* CAN Controller 1 Mailbox 30 Data 0 Register */
666#define CAN1_MB30_DATA1 0xffc037c4 /* CAN Controller 1 Mailbox 30 Data 1 Register */
667#define CAN1_MB30_DATA2 0xffc037c8 /* CAN Controller 1 Mailbox 30 Data 2 Register */
668#define CAN1_MB30_DATA3 0xffc037cc /* CAN Controller 1 Mailbox 30 Data 3 Register */
669#define CAN1_MB30_LENGTH 0xffc037d0 /* CAN Controller 1 Mailbox 30 Length Register */
670#define CAN1_MB30_TIMESTAMP 0xffc037d4 /* CAN Controller 1 Mailbox 30 Timestamp Register */
671#define CAN1_MB30_ID0 0xffc037d8 /* CAN Controller 1 Mailbox 30 ID0 Register */
672#define CAN1_MB30_ID1 0xffc037dc /* CAN Controller 1 Mailbox 30 ID1 Register */
673#define CAN1_MB31_DATA0 0xffc037e0 /* CAN Controller 1 Mailbox 31 Data 0 Register */
674#define CAN1_MB31_DATA1 0xffc037e4 /* CAN Controller 1 Mailbox 31 Data 1 Register */
675#define CAN1_MB31_DATA2 0xffc037e8 /* CAN Controller 1 Mailbox 31 Data 2 Register */
676#define CAN1_MB31_DATA3 0xffc037ec /* CAN Controller 1 Mailbox 31 Data 3 Register */
677#define CAN1_MB31_LENGTH 0xffc037f0 /* CAN Controller 1 Mailbox 31 Length Register */
678#define CAN1_MB31_TIMESTAMP 0xffc037f4 /* CAN Controller 1 Mailbox 31 Timestamp Register */
679#define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */
680#define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */
681
682/* ATAPI Registers */
683
684#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */
685#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */
686#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */
687#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */
688#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */
689#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */
690#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */
691#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */
692#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */
693#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */
694#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */
695#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */
696#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */
697#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */
698#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */
699#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */
700#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */
701#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */
702#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
703#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
704#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
705#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
706#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
707#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
708#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
709
710/* SDH Registers */
711
712#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */
713#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */
714#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */
715#define SDH_COMMAND 0xffc0390c /* SDH Command */
716#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */
717#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */
718#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */
719#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */
720#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */
721#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */
722#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */
723#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */
724#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */
725#define SDH_STATUS 0xffc03934 /* SDH Status */
726#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */
727#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */
728#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */
729#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */
730#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */
731#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */
732#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */
733#define SDH_CFG 0xffc039c8 /* SDH Configuration */
734#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */
735#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */
736#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */
737#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */
738#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */
739#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */
740#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */
741#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */
742#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */
743
744/* HOST Port Registers */
745
746#define HOST_CONTROL 0xffc03a00 /* HOST Control Register */
747#define HOST_STATUS 0xffc03a04 /* HOST Status Register */
748#define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */
749
750/* USB Control Registers */
751
752#define USB_FADDR 0xffc03c00 /* Function address register */
753#define USB_POWER 0xffc03c04 /* Power management register */
754#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
755#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */
756#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
757#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
758#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */
759#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
760#define USB_FRAME 0xffc03c20 /* USB frame number */
761#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */
762#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */
763#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
764#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
765
766/* USB Packet Control Registers */
767
768#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */
769#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
770#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
771#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */
772#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */
773#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
774#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
775#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
776#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
777#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
778#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
779#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
780#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
781
782/* USB Endpoint FIFO Registers */
783
784#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */
785#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */
786#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */
787#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */
788#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */
789#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */
790#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */
791#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */
792
793/* USB OTG Control Registers */
794
795#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */
796#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */
797#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */
798
799/* USB Phy Control Registers */
800
801#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */
802#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */
803#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
804#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
805#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
806
807/* (APHY_CNTRL is for ADI usage only) */
808
809#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */
810
811/* (APHY_CALIB is for ADI usage only) */
812
813#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */
814#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
815
816/* (PHY_TEST is for ADI usage only) */
817
818#define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */
819#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */
820#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
821
822/* USB Endpoint 0 Control Registers */
823
824#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */
825#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */
826#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */
827#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */
828#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */
829#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
830#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
831#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
832#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
833
834/* USB Endpoint 1 Control Registers */
835
836#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
837#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
838#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
839#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
840#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */
841#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */
842#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
843#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
844#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
845#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
846
847/* USB Endpoint 2 Control Registers */
848
849#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
850#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
851#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
852#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
853#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */
854#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */
855#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
856#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
857#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
858#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
859
860/* USB Endpoint 3 Control Registers */
861
862#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
863#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
864#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
865#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
866#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */
867#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */
868#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
869#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
870#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
871#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
872
873/* USB Endpoint 4 Control Registers */
874
875#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
876#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
877#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
878#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
879#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */
880#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */
881#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
882#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
883#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
884#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
885
886/* USB Endpoint 5 Control Registers */
887
888#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
889#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
890#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
891#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
892#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */
893#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */
894#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
895#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
896#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
897#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
898
899/* USB Endpoint 6 Control Registers */
900
901#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
902#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
903#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
904#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
905#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */
906#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */
907#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
908#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
909#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
910#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
911
912/* USB Endpoint 7 Control Registers */
913
914#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
915#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
916#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
917#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
918#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */
919#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */
920#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
921#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
922#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
923#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
924#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
925#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */
926
927/* USB Channel 0 Config Registers */
928
929#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */
930#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
931#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
932#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
933#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
934
935/* USB Channel 1 Config Registers */
936
937#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */
938#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
939#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
940#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
941#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
942
943/* USB Channel 2 Config Registers */
944
945#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */
946#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
947#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
948#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
949#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
950
951/* USB Channel 3 Config Registers */
952
953#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */
954#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
955#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
956#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
957#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
958
959/* USB Channel 4 Config Registers */
960
961#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */
962#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
963#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
964#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
965#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
966
967/* USB Channel 5 Config Registers */
968
969#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */
970#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
971#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
972#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
973#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
974
975/* USB Channel 6 Config Registers */
976
977#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */
978#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
979#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
980#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
981#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
982
983/* USB Channel 7 Config Registers */
984
985#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */
986#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
987#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
988#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
989#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
990
991/* Keypad Registers */
992
993#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */
994#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */
995#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */
996#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */
997#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */
998#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */
999
1000/* Pixel Compositor (PIXC) Registers */
1001
1002#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
1003#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */
1004#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */
1005#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */
1006#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */
1007#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */
1008#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */
1009#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */
1010#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */
1011#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */
1012#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */
1013#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */
1014#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */
1015#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */
1016#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
1017#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
1018#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
1019#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */
1020#define PIXC_TC 0xffc04450 /* Holds the transparent color value */
1021
1022/* Handshake MDMA 0 Registers */
1023
1024#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */
1025#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */
1026#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */
1027#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshold Register */
1028#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
1029#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */
1030#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */
1031
1032/* Handshake MDMA 1 Registers */
1033
1034#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */
1035#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */
1036#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */
1037#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshold Register */
1038#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
1039#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */
1040#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */
1041
1042
1043/* ********************************************************** */
1044/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
1045/* and MULTI BIT READ MACROS */
1046/* ********************************************************** */
1047
1048/* Bit masks for PIXC_CTL */
1049
1050#define PIXC_EN 0x1 /* Pixel Compositor Enable */
1051#define OVR_A_EN 0x2 /* Overlay A Enable */
1052#define OVR_B_EN 0x4 /* Overlay B Enable */
1053#define IMG_FORM 0x8 /* Image Data Format */
1054#define OVR_FORM 0x10 /* Overlay Data Format */
1055#define OUT_FORM 0x20 /* Output Data Format */
1056#define UDS_MOD 0x40 /* Resampling Mode */
1057#define TC_EN 0x80 /* Transparent Color Enable */
1058#define IMG_STAT 0x300 /* Image FIFO Status */
1059#define OVR_STAT 0xc00 /* Overlay FIFO Status */
1060#define WM_LVL 0x3000 /* FIFO Watermark Level */
1061
1062/* Bit masks for PIXC_AHSTART */
1063
1064#define A_HSTART 0xfff /* Horizontal Start Coordinates */
1065
1066/* Bit masks for PIXC_AHEND */
1067
1068#define A_HEND 0xfff /* Horizontal End Coordinates */
1069
1070/* Bit masks for PIXC_AVSTART */
1071
1072#define A_VSTART 0x3ff /* Vertical Start Coordinates */
1073
1074/* Bit masks for PIXC_AVEND */
1075
1076#define A_VEND 0x3ff /* Vertical End Coordinates */
1077
1078/* Bit masks for PIXC_ATRANSP */
1079
1080#define A_TRANSP 0xf /* Transparency Value */
1081
1082/* Bit masks for PIXC_BHSTART */
1083
1084#define B_HSTART 0xfff /* Horizontal Start Coordinates */
1085
1086/* Bit masks for PIXC_BHEND */
1087
1088#define B_HEND 0xfff /* Horizontal End Coordinates */
1089
1090/* Bit masks for PIXC_BVSTART */
1091
1092#define B_VSTART 0x3ff /* Vertical Start Coordinates */
1093
1094/* Bit masks for PIXC_BVEND */
1095
1096#define B_VEND 0x3ff /* Vertical End Coordinates */
1097
1098/* Bit masks for PIXC_BTRANSP */
1099
1100#define B_TRANSP 0xf /* Transparency Value */
1101
1102/* Bit masks for PIXC_INTRSTAT */
1103
1104#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
1105#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
1106#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
1107#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
1108
1109/* Bit masks for PIXC_RYCON */
1110
1111#define A11 0x3ff /* A11 in the Coefficient Matrix */
1112#define A12 0xffc00 /* A12 in the Coefficient Matrix */
1113#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
1114#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
1115
1116/* Bit masks for PIXC_GUCON */
1117
1118#define A21 0x3ff /* A21 in the Coefficient Matrix */
1119#define A22 0xffc00 /* A22 in the Coefficient Matrix */
1120#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
1121#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
1122
1123/* Bit masks for PIXC_BVCON */
1124
1125#define A31 0x3ff /* A31 in the Coefficient Matrix */
1126#define A32 0xffc00 /* A32 in the Coefficient Matrix */
1127#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
1128#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
1129
1130/* Bit masks for PIXC_CCBIAS */
1131
1132#define A14 0x3ff /* A14 in the Bias Vector */
1133#define A24 0xffc00 /* A24 in the Bias Vector */
1134#define A34 0x3ff00000 /* A34 in the Bias Vector */
1135
1136/* Bit masks for PIXC_TC */
1137
1138#define RY_TRANS 0xff /* Transparent Color - R/Y Component */
1139#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */
1140#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */
1141
1142/* Bit masks for HOST_CONTROL */
1143
1144#define HOST_EN 0x1 /* Host Enable */
1145#define HOST_END 0x2 /* Host Endianess */
1146#define DATA_SIZE 0x4 /* Data Size */
1147#define HOST_RST 0x8 /* Host Reset */
1148#define HRDY_OVR 0x20 /* Host Ready Override */
1149#define INT_MODE 0x40 /* Interrupt Mode */
1150#define BT_EN 0x80 /* Bus Timeout Enable */
1151#define EHW 0x100 /* Enable Host Write */
1152#define EHR 0x200 /* Enable Host Read */
1153#define BDR 0x400 /* Burst DMA Requests */
1154
1155/* Bit masks for HOST_STATUS */
1156
1157#define DMA_READY 0x1 /* DMA Ready */
1158#define FIFOFULL 0x2 /* FIFO Full */
1159#define FIFOEMPTY 0x4 /* FIFO Empty */
1160#define DMA_COMPLETE 0x8 /* DMA Complete */
1161#define HSHK 0x10 /* Host Handshake */
1162#define TIMEOUT 0x20 /* Host Timeout */
1163#define HIRQ 0x40 /* Host Interrupt Request */
1164#define ALLOW_CNFG 0x80 /* Allow New Configuration */
1165#define DMA_DIR 0x100 /* DMA Direction */
1166#define BTE 0x200 /* Bus Timeout Enabled */
1167
1168/* Bit masks for HOST_TIMEOUT */
1169
1170#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */
1171
1172/* Bit masks for MXVR_CONFIG */ 191/* Bit masks for MXVR_CONFIG */
1173 192
1174#define MXVREN 0x1 /* MXVR Enable */ 193#define MXVREN 0x1 /* MXVR Enable */
@@ -2031,603 +1050,6 @@
2031 1050
2032#define SCNT 0xffff /* System Clock Count */ 1051#define SCNT 0xffff /* System Clock Count */
2033 1052
2034/* Bit masks for KPAD_CTL */
2035
2036#define KPAD_EN 0x1 /* Keypad Enable */
2037#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
2038#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
2039#define KPAD_COLEN 0xe000 /* Column Enable Width */
2040
2041/* Bit masks for KPAD_PRESCALE */
2042
2043#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
2044
2045/* Bit masks for KPAD_MSEL */
2046
2047#define DBON_SCALE 0xff /* Debounce Scale Value */
2048#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
2049
2050/* Bit masks for KPAD_ROWCOL */
2051
2052#define KPAD_ROW 0xff /* Rows Pressed */
2053#define KPAD_COL 0xff00 /* Columns Pressed */
2054
2055/* Bit masks for KPAD_STAT */
2056
2057#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
2058#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
2059#define KPAD_PRESSED 0x8 /* Key press current status */
2060
2061/* Bit masks for KPAD_SOFTEVAL */
2062
2063#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
2064
2065/* Bit masks for SDH_COMMAND */
2066
2067#define CMD_IDX 0x3f /* Command Index */
2068#define CMD_RSP 0x40 /* Response */
2069#define CMD_L_RSP 0x80 /* Long Response */
2070#define CMD_INT_E 0x100 /* Command Interrupt */
2071#define CMD_PEND_E 0x200 /* Command Pending */
2072#define CMD_E 0x400 /* Command Enable */
2073
2074/* Bit masks for SDH_PWR_CTL */
2075
2076#define PWR_ON 0x3 /* Power On */
2077#if 0
2078#define TBD 0x3c /* TBD */
2079#endif
2080#define SD_CMD_OD 0x40 /* Open Drain Output */
2081#define ROD_CTL 0x80 /* Rod Control */
2082
2083/* Bit masks for SDH_CLK_CTL */
2084
2085#define CLKDIV 0xff /* MC_CLK Divisor */
2086#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
2087#define PWR_SV_E 0x200 /* Power Save Enable */
2088#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
2089#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
2090
2091/* Bit masks for SDH_RESP_CMD */
2092
2093#define RESP_CMD 0x3f /* Response Command */
2094
2095/* Bit masks for SDH_DATA_CTL */
2096
2097#define DTX_E 0x1 /* Data Transfer Enable */
2098#define DTX_DIR 0x2 /* Data Transfer Direction */
2099#define DTX_MODE 0x4 /* Data Transfer Mode */
2100#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
2101#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
2102
2103/* Bit masks for SDH_STATUS */
2104
2105#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
2106#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
2107#define CMD_TIME_OUT 0x4 /* CMD Time Out */
2108#define DAT_TIME_OUT 0x8 /* Data Time Out */
2109#define TX_UNDERRUN 0x10 /* Transmit Underrun */
2110#define RX_OVERRUN 0x20 /* Receive Overrun */
2111#define CMD_RESP_END 0x40 /* CMD Response End */
2112#define CMD_SENT 0x80 /* CMD Sent */
2113#define DAT_END 0x100 /* Data End */
2114#define START_BIT_ERR 0x200 /* Start Bit Error */
2115#define DAT_BLK_END 0x400 /* Data Block End */
2116#define CMD_ACT 0x800 /* CMD Active */
2117#define TX_ACT 0x1000 /* Transmit Active */
2118#define RX_ACT 0x2000 /* Receive Active */
2119#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
2120#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
2121#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
2122#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
2123#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
2124#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
2125#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
2126#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
2127
2128/* Bit masks for SDH_STATUS_CLR */
2129
2130#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
2131#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
2132#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
2133#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
2134#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
2135#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
2136#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
2137#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
2138#define DAT_END_STAT 0x100 /* Data End Status */
2139#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
2140#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
2141
2142/* Bit masks for SDH_MASK0 */
2143
2144#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
2145#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
2146#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
2147#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
2148#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
2149#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
2150#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
2151#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
2152#define DAT_END_MASK 0x100 /* Data End Mask */
2153#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
2154#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
2155#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
2156#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
2157#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
2158#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
2159#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
2160#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
2161#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
2162#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
2163#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
2164#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
2165#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
2166
2167/* Bit masks for SDH_FIFO_CNT */
2168
2169#define FIFO_COUNT 0x7fff /* FIFO Count */
2170
2171/* Bit masks for SDH_E_STATUS */
2172
2173#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
2174#define SD_CARD_DET 0x10 /* SD Card Detect */
2175
2176/* Bit masks for SDH_E_MASK */
2177
2178#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
2179#define SCD_MSK 0x40 /* Mask Card Detect */
2180
2181/* Bit masks for SDH_CFG */
2182
2183#define CLKS_EN 0x1 /* Clocks Enable */
2184#define SD4E 0x4 /* SDIO 4-Bit Enable */
2185#define MWE 0x8 /* Moving Window Enable */
2186#define SD_RST 0x10 /* SDMMC Reset */
2187#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
2188#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
2189#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
2190
2191/* Bit masks for SDH_RD_WAIT_EN */
2192
2193#define RWR 0x1 /* Read Wait Request */
2194
2195/* Bit masks for ATAPI_CONTROL */
2196
2197#define PIO_START 0x1 /* Start PIO/Reg Op */
2198#define MULTI_START 0x2 /* Start Multi-DMA Op */
2199#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
2200#define XFER_DIR 0x8 /* Transfer Direction */
2201#define IORDY_EN 0x10 /* IORDY Enable */
2202#define FIFO_FLUSH 0x20 /* Flush FIFOs */
2203#define SOFT_RST 0x40 /* Soft Reset */
2204#define DEV_RST 0x80 /* Device Reset */
2205#define TFRCNT_RST 0x100 /* Trans Count Reset */
2206#define END_ON_TERM 0x200 /* End/Terminate Select */
2207#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
2208#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
2209
2210/* Bit masks for ATAPI_STATUS */
2211
2212#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
2213#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
2214#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
2215#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
2216
2217/* Bit masks for ATAPI_DEV_ADDR */
2218
2219#define DEV_ADDR 0x1f /* Device Address */
2220
2221/* Bit masks for ATAPI_INT_MASK */
2222
2223#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
2224#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
2225#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
2226#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
2227#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
2228#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
2229#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
2230#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
2231#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
2232
2233/* Bit masks for ATAPI_INT_STATUS */
2234
2235#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
2236#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
2237#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
2238#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
2239#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
2240#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
2241#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
2242#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
2243#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
2244
2245/* Bit masks for ATAPI_LINE_STATUS */
2246
2247#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
2248#define ATAPI_DASP 0x2 /* Device dasp to host line status */
2249#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
2250#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
2251#define ATAPI_ADDR 0x70 /* ATAPI address line status */
2252#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
2253#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
2254#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
2255#define ATAPI_DIORN 0x400 /* ATAPI read line status */
2256#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
2257
2258/* Bit masks for ATAPI_SM_STATE */
2259
2260#define PIO_CSTATE 0xf /* PIO mode state machine current state */
2261#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */
2262#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
2263#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
2264
2265/* Bit masks for ATAPI_TERMINATE */
2266
2267#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
2268
2269/* Bit masks for ATAPI_REG_TIM_0 */
2270
2271#define T2_REG 0xff /* End of cycle time for register access transfers */
2272#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */
2273
2274/* Bit masks for ATAPI_PIO_TIM_0 */
2275
2276#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */
2277#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */
2278#define T4_REG 0xf000 /* DIOW data hold */
2279
2280/* Bit masks for ATAPI_PIO_TIM_1 */
2281
2282#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
2283
2284/* Bit masks for ATAPI_MULTI_TIM_0 */
2285
2286#define TD 0xff /* DIOR/DIOW asserted pulsewidth */
2287#define TM 0xff00 /* Time from address valid to DIOR/DIOW */
2288
2289/* Bit masks for ATAPI_MULTI_TIM_1 */
2290
2291#define TKW 0xff /* Selects DIOW negated pulsewidth */
2292#define TKR 0xff00 /* Selects DIOR negated pulsewidth */
2293
2294/* Bit masks for ATAPI_MULTI_TIM_2 */
2295
2296#define TH 0xff /* Selects DIOW data hold */
2297#define TEOC 0xff00 /* Selects end of cycle for DMA */
2298
2299/* Bit masks for ATAPI_ULTRA_TIM_0 */
2300
2301#define TACK 0xff /* Selects setup and hold times for TACK */
2302#define TENV 0xff00 /* Selects envelope time */
2303
2304/* Bit masks for ATAPI_ULTRA_TIM_1 */
2305
2306#define TDVS 0xff /* Selects data valid setup time */
2307#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
2308
2309/* Bit masks for ATAPI_ULTRA_TIM_2 */
2310
2311#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
2312#define TMLI 0xff00 /* Selects interlock time */
2313
2314/* Bit masks for ATAPI_ULTRA_TIM_3 */
2315
2316#define TZAH 0xff /* Selects minimum delay required for output */
2317#define READY_PAUSE 0xff00 /* Selects ready to pause */
2318
2319/* Bit masks for TIMER_ENABLE1 */
2320
2321#define TIMEN8 0x1 /* Timer 8 Enable */
2322#define TIMEN9 0x2 /* Timer 9 Enable */
2323#define TIMEN10 0x4 /* Timer 10 Enable */
2324
2325/* Bit masks for TIMER_DISABLE1 */
2326
2327#define TIMDIS8 0x1 /* Timer 8 Disable */
2328#define TIMDIS9 0x2 /* Timer 9 Disable */
2329#define TIMDIS10 0x4 /* Timer 10 Disable */
2330
2331/* Bit masks for TIMER_STATUS1 */
2332
2333#define TIMIL8 0x1 /* Timer 8 Interrupt */
2334#define TIMIL9 0x2 /* Timer 9 Interrupt */
2335#define TIMIL10 0x4 /* Timer 10 Interrupt */
2336#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
2337#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
2338#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
2339#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
2340#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
2341#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
2342
2343/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
2344
2345/* Bit masks for USB_FADDR */
2346
2347#define FUNCTION_ADDRESS 0x7f /* Function address */
2348
2349/* Bit masks for USB_POWER */
2350
2351#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
2352#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
2353#define RESUME_MODE 0x4 /* DMA Mode */
2354#define RESET 0x8 /* Reset indicator */
2355#define HS_MODE 0x10 /* High Speed mode indicator */
2356#define HS_ENABLE 0x20 /* high Speed Enable */
2357#define SOFT_CONN 0x40 /* Soft connect */
2358#define ISO_UPDATE 0x80 /* Isochronous update */
2359
2360/* Bit masks for USB_INTRTX */
2361
2362#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
2363#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
2364#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
2365#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
2366#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
2367#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
2368#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
2369#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
2370
2371/* Bit masks for USB_INTRRX */
2372
2373#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
2374#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
2375#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
2376#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
2377#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
2378#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
2379#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
2380
2381/* Bit masks for USB_INTRTXE */
2382
2383#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
2384#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
2385#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
2386#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
2387#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
2388#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
2389#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
2390#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
2391
2392/* Bit masks for USB_INTRRXE */
2393
2394#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
2395#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
2396#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
2397#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
2398#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
2399#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
2400#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
2401
2402/* Bit masks for USB_INTRUSB */
2403
2404#define SUSPEND_B 0x1 /* Suspend indicator */
2405#define RESUME_B 0x2 /* Resume indicator */
2406#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
2407#define SOF_B 0x8 /* Start of frame */
2408#define CONN_B 0x10 /* Connection indicator */
2409#define DISCON_B 0x20 /* Disconnect indicator */
2410#define SESSION_REQ_B 0x40 /* Session Request */
2411#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
2412
2413/* Bit masks for USB_INTRUSBE */
2414
2415#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
2416#define RESUME_BE 0x2 /* Resume indicator int enable */
2417#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
2418#define SOF_BE 0x8 /* Start of frame int enable */
2419#define CONN_BE 0x10 /* Connection indicator int enable */
2420#define DISCON_BE 0x20 /* Disconnect indicator int enable */
2421#define SESSION_REQ_BE 0x40 /* Session Request int enable */
2422#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
2423
2424/* Bit masks for USB_FRAME */
2425
2426#define FRAME_NUMBER 0x7ff /* Frame number */
2427
2428/* Bit masks for USB_INDEX */
2429
2430#define SELECTED_ENDPOINT 0xf /* selected endpoint */
2431
2432/* Bit masks for USB_GLOBAL_CTL */
2433
2434#define GLOBAL_ENA 0x1 /* enables USB module */
2435#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
2436#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
2437#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
2438#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
2439#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
2440#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
2441#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
2442#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
2443#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
2444#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
2445#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
2446#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
2447#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
2448#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
2449
2450/* Bit masks for USB_OTG_DEV_CTL */
2451
2452#define SESSION 0x1 /* session indicator */
2453#define HOST_REQ 0x2 /* Host negotiation request */
2454#define HOST_MODE 0x4 /* indicates USBDRC is a host */
2455#define VBUS0 0x8 /* Vbus level indicator[0] */
2456#define VBUS1 0x10 /* Vbus level indicator[1] */
2457#define LSDEV 0x20 /* Low-speed indicator */
2458#define FSDEV 0x40 /* Full or High-speed indicator */
2459#define B_DEVICE 0x80 /* A' or 'B' device indicator */
2460
2461/* Bit masks for USB_OTG_VBUS_IRQ */
2462
2463#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
2464#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
2465#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
2466#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
2467#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
2468#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
2469
2470/* Bit masks for USB_OTG_VBUS_MASK */
2471
2472#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
2473#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
2474#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
2475#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
2476#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
2477#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
2478
2479/* Bit masks for USB_CSR0 */
2480
2481#define RXPKTRDY 0x1 /* data packet receive indicator */
2482#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
2483#define STALL_SENT 0x4 /* STALL handshake sent */
2484#define DATAEND 0x8 /* Data end indicator */
2485#define SETUPEND 0x10 /* Setup end */
2486#define SENDSTALL 0x20 /* Send STALL handshake */
2487#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
2488#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
2489#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
2490#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
2491#define SETUPPKT_H 0x8 /* send Setup token host mode */
2492#define ERROR_H 0x10 /* timeout error indicator host mode */
2493#define REQPKT_H 0x20 /* Request an IN transaction host mode */
2494#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
2495#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
2496
2497/* Bit masks for USB_COUNT0 */
2498
2499#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
2500
2501/* Bit masks for USB_NAKLIMIT0 */
2502
2503#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
2504
2505/* Bit masks for USB_TX_MAX_PACKET */
2506
2507#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
2508
2509/* Bit masks for USB_RX_MAX_PACKET */
2510
2511#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
2512
2513/* Bit masks for USB_TXCSR */
2514
2515#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
2516#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
2517#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
2518#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
2519#define STALL_SEND_T 0x10 /* issue a Stall handshake */
2520#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
2521#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
2522#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
2523#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
2524#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
2525#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
2526#define ISO_T 0x4000 /* enable Isochronous transfers */
2527#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
2528#define ERROR_TH 0x4 /* error condition host mode */
2529#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
2530#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
2531
2532/* Bit masks for USB_TXCOUNT */
2533
2534#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
2535
2536/* Bit masks for USB_RXCSR */
2537
2538#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
2539#define FIFO_FULL_R 0x2 /* FIFO not empty */
2540#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
2541#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
2542#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
2543#define STALL_SEND_R 0x20 /* issue a Stall handshake */
2544#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
2545#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
2546#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
2547#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
2548#define DISNYET_R 0x1000 /* disable Nyet handshakes */
2549#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
2550#define ISO_R 0x4000 /* enable Isochronous transfers */
2551#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
2552#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
2553#define REQPKT_RH 0x20 /* request an IN transaction host mode */
2554#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
2555#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
2556#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
2557#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
2558
2559/* Bit masks for USB_RXCOUNT */
2560
2561#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
2562
2563/* Bit masks for USB_TXTYPE */
2564
2565#define TARGET_EP_NO_T 0xf /* EP number */
2566#define PROTOCOL_T 0xc /* transfer type */
2567
2568/* Bit masks for USB_TXINTERVAL */
2569
2570#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
2571
2572/* Bit masks for USB_RXTYPE */
2573
2574#define TARGET_EP_NO_R 0xf /* EP number */
2575#define PROTOCOL_R 0xc /* transfer type */
2576
2577/* Bit masks for USB_RXINTERVAL */
2578
2579#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
2580
2581/* Bit masks for USB_DMA_INTERRUPT */
2582
2583#define DMA0_INT 0x1 /* DMA0 pending interrupt */
2584#define DMA1_INT 0x2 /* DMA1 pending interrupt */
2585#define DMA2_INT 0x4 /* DMA2 pending interrupt */
2586#define DMA3_INT 0x8 /* DMA3 pending interrupt */
2587#define DMA4_INT 0x10 /* DMA4 pending interrupt */
2588#define DMA5_INT 0x20 /* DMA5 pending interrupt */
2589#define DMA6_INT 0x40 /* DMA6 pending interrupt */
2590#define DMA7_INT 0x80 /* DMA7 pending interrupt */
2591
2592/* Bit masks for USB_DMAxCONTROL */
2593
2594#define DMA_ENA 0x1 /* DMA enable */
2595#define DIRECTION 0x2 /* direction of DMA transfer */
2596#define MODE 0x4 /* DMA Bus error */
2597#define INT_ENA 0x8 /* Interrupt enable */
2598#define EPNUM 0xf0 /* EP number */
2599#define BUSERROR 0x100 /* DMA Bus error */
2600
2601/* Bit masks for USB_DMAxADDRHIGH */
2602
2603#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
2604
2605/* Bit masks for USB_DMAxADDRLOW */
2606
2607#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
2608
2609/* Bit masks for USB_DMAxCOUNTHIGH */
2610
2611#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
2612
2613/* Bit masks for USB_DMAxCOUNTLOW */
2614
2615#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
2616
2617/* Bit masks for HMDMAx_CONTROL */
2618
2619#define HMDMAEN 0x1 /* Handshake MDMA Enable */
2620#define REP 0x2 /* Handshake MDMA Request Polarity */
2621#define UTE 0x8 /* Urgency Threshold Enable */
2622#define OIE 0x10 /* Overflow Interrupt Enable */
2623#define BDIE 0x20 /* Block Done Interrupt Enable */
2624#define MBDI 0x40 /* Mask Block Done Interrupt */
2625#define DRQ 0x300 /* Handshake MDMA Request Type */
2626#define RBC 0x1000 /* Force Reload of BCOUNT */
2627#define PS 0x2000 /* Pin Status */
2628#define OI 0x4000 /* Overflow Interrupt Generated */
2629#define BDI 0x8000 /* Block Done Interrupt Generated */
2630
2631/* ******************************************* */ 1053/* ******************************************* */
2632/* MULTI BIT MACRO ENUMERATIONS */ 1054/* MULTI BIT MACRO ENUMERATIONS */
2633/* ******************************************* */ 1055/* ******************************************* */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 03:39:33 -0500