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authorMike Frysinger <vapier.adi@gmail.com>2008-11-18 04:48:22 -0500
committerBryan Wu <cooloney@kernel.org>2008-11-18 04:48:22 -0500
commit31fba6e752fee4ef8747bc9cac141dc70ae74652 (patch)
tree22c3f5d2824af2e7043498b1a6b5710df3e4c777 /arch/blackfin
parent89c6c139a57e27617850ddc7df90e267374a1a5c (diff)
Blackfin arch: introduce an IM_MEM macro to kgdb
create an IN_MEM() macro to simplify comparing an address in an on-chip region of memory and make things readable Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin')
-rw-r--r--arch/blackfin/kernel/kgdb.c105
1 files changed, 35 insertions, 70 deletions
diff --git a/arch/blackfin/kernel/kgdb.c b/arch/blackfin/kernel/kgdb.c
index 2af3a886c14..62c3032d843 100644
--- a/arch/blackfin/kernel/kgdb.c
+++ b/arch/blackfin/kernel/kgdb.c
@@ -34,6 +34,15 @@ int gdb_bfin_vector = -1;
34#error change the definition of slavecpulocks 34#error change the definition of slavecpulocks
35#endif 35#endif
36 36
37#define IN_MEM(addr, size, l1_addr, l1_size) \
38({ \
39 unsigned long __addr = (unsigned long)(addr); \
40 (__addr >= l1_addr && __addr + (size) <= l1_addr + l1_size); \
41})
42#define ASYNC_BANK_SIZE \
43 (ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \
44 ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE)
45
37void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs) 46void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
38{ 47{
39 gdb_regs[BFIN_R0] = regs->r0; 48 gdb_regs[BFIN_R0] = regs->r0;
@@ -462,55 +471,32 @@ static int validate_memory_access_address(unsigned long addr, int size)
462 return 0; 471 return 0;
463 if (addr >= SYSMMR_BASE) 472 if (addr >= SYSMMR_BASE)
464 return 0; 473 return 0;
465 if (addr >= ASYNC_BANK0_BASE 474 if (IN_MEM(addr, size, ASYNC_BANK0_BASE, ASYNC_BANK_SIZE))
466 && addr + size <= ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE)
467 return 0; 475 return 0;
468 if (cpu == 0) { 476 if (cpu == 0) {
469 if (addr >= L1_SCRATCH_START 477 if (IN_MEM(addr, size, L1_SCRATCH_START, L1_SCRATCH_LENGTH))
470 && (addr + size <= L1_SCRATCH_START + L1_SCRATCH_LENGTH))
471 return 0; 478 return 0;
472#if L1_CODE_LENGTH != 0 479 if (IN_MEM(addr, size, L1_CODE_START, L1_CODE_LENGTH))
473 if (addr >= L1_CODE_START
474 && (addr + size <= L1_CODE_START + L1_CODE_LENGTH))
475 return 0; 480 return 0;
476#endif 481 if (IN_MEM(addr, size, L1_DATA_A_START, L1_DATA_A_LENGTH))
477#if L1_DATA_A_LENGTH != 0
478 if (addr >= L1_DATA_A_START
479 && (addr + size <= L1_DATA_A_START + L1_DATA_A_LENGTH))
480 return 0; 482 return 0;
481#endif 483 if (IN_MEM(addr, size, L1_DATA_B_START, L1_DATA_B_LENGTH))
482#if L1_DATA_B_LENGTH != 0
483 if (addr >= L1_DATA_B_START
484 && (addr + size <= L1_DATA_B_START + L1_DATA_B_LENGTH))
485 return 0; 484 return 0;
486#endif
487#ifdef CONFIG_SMP 485#ifdef CONFIG_SMP
488 } else if (cpu == 1) { 486 } else if (cpu == 1) {
489 if (addr >= COREB_L1_SCRATCH_START 487 if (IN_MEM(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
490 && (addr + size <= COREB_L1_SCRATCH_START
491 + L1_SCRATCH_LENGTH))
492 return 0; 488 return 0;
493# if L1_CODE_LENGTH != 0 489 if (IN_MEM(addr, size, COREB_L1_CODE_START, L1_CODE_LENGTH))
494 if (addr >= COREB_L1_CODE_START
495 && (addr + size <= COREB_L1_CODE_START + L1_CODE_LENGTH))
496 return 0; 490 return 0;
497# endif 491 if (IN_MEM(addr, size, COREB_L1_DATA_A_START, L1_DATA_A_LENGTH))
498# if L1_DATA_A_LENGTH != 0
499 if (addr >= COREB_L1_DATA_A_START
500 && (addr + size <= COREB_L1_DATA_A_START + L1_DATA_A_LENGTH))
501 return 0; 492 return 0;
502# endif 493 if (IN_MEM(addr, size, COREB_L1_DATA_B_START, L1_DATA_B_LENGTH))
503# if L1_DATA_B_LENGTH != 0
504 if (addr >= COREB_L1_DATA_B_START
505 && (addr + size <= COREB_L1_DATA_B_START + L1_DATA_B_LENGTH))
506 return 0; 494 return 0;
507# endif
508#endif 495#endif
509 } 496 }
510 497
511#if L2_LENGTH != 0 498#if L2_LENGTH
512 if (addr >= L2_START 499 if (IN_MEM(addr, size, L2_START, L2_LENGTH))
513 && addr + size <= L2_START + L2_LENGTH)
514 return 0; 500 return 0;
515#endif 501#endif
516 502
@@ -566,12 +552,9 @@ int kgdb_mem2hex(char *mem, char *buf, int count)
566 default: 552 default:
567 err = EFAULT; 553 err = EFAULT;
568 } 554 }
569 } else if ((cpu == 0 && (unsigned int)mem >= L1_CODE_START && 555 } else if ((cpu == 0 && IN_MEM(mem, count, L1_CODE_START, L1_CODE_LENGTH))
570 (unsigned int)(mem + count) <= L1_CODE_START + L1_CODE_LENGTH)
571#ifdef CONFIG_SMP 556#ifdef CONFIG_SMP
572 || (cpu == 1 && (unsigned int)mem >= COREB_L1_CODE_START && 557 || (cpu == 1 && IN_MEM(mem, count, COREB_L1_CODE_START, L1_CODE_LENGTH))
573 (unsigned int)(mem + count) <=
574 COREB_L1_CODE_START + L1_CODE_LENGTH)
575#endif 558#endif
576 ) { 559 ) {
577 /* access L1 instruction SRAM*/ 560 /* access L1 instruction SRAM*/
@@ -642,12 +625,9 @@ int kgdb_ebin2mem(char *buf, char *mem, int count)
642 default: 625 default:
643 return EFAULT; 626 return EFAULT;
644 } 627 }
645 } else if ((cpu == 0 && (unsigned int)mem >= L1_CODE_START && 628 } else if ((cpu == 0 && IN_MEM(mem, count, L1_CODE_START, L1_CODE_LENGTH))
646 (unsigned int)(mem + count) <= L1_CODE_START + L1_CODE_LENGTH)
647#ifdef CONFIG_SMP 629#ifdef CONFIG_SMP
648 || (cpu == 1 && (unsigned int)mem >= COREB_L1_CODE_START && 630 || (cpu == 1 && IN_MEM(mem, count, COREB_L1_CODE_START, L1_CODE_LENGTH))
649 (unsigned int)(mem + count) <=
650 COREB_L1_CODE_START + L1_CODE_LENGTH)
651#endif 631#endif
652 ) { 632 ) {
653 /* access L1 instruction SRAM */ 633 /* access L1 instruction SRAM */
@@ -707,12 +687,9 @@ int kgdb_hex2mem(char *buf, char *mem, int count)
707 default: 687 default:
708 return EFAULT; 688 return EFAULT;
709 } 689 }
710 } else if ((cpu == 0 && (unsigned int)mem >= L1_CODE_START && 690 } else if ((cpu == 0 && IN_MEM(mem, count, L1_CODE_START, L1_CODE_LENGTH))
711 (unsigned int)(mem + count) <= L1_CODE_START + L1_CODE_LENGTH)
712#ifdef CONFIG_SMP 691#ifdef CONFIG_SMP
713 || (cpu == 1 && (unsigned int)mem >= COREB_L1_CODE_START && 692 || (cpu == 1 && IN_MEM(mem, count, COREB_L1_CODE_START, L1_CODE_LENGTH))
714 (unsigned int)(mem + count) <=
715 COREB_L1_CODE_START + L1_CODE_LENGTH)
716#endif 693#endif
717 ) { 694 ) {
718 /* access L1 instruction SRAM */ 695 /* access L1 instruction SRAM */
@@ -729,22 +706,16 @@ int kgdb_validate_break_address(unsigned long addr)
729 706
730 if (addr >= 0x1000 && (addr + BREAK_INSTR_SIZE) <= physical_mem_end) 707 if (addr >= 0x1000 && (addr + BREAK_INSTR_SIZE) <= physical_mem_end)
731 return 0; 708 return 0;
732 if (addr >= ASYNC_BANK0_BASE 709 if (IN_MEM(addr, BREAK_INSTR_SIZE, ASYNC_BANK0_BASE, ASYNC_BANK_SIZE))
733 && addr + BREAK_INSTR_SIZE <= ASYNC_BANK3_BASE + ASYNC_BANK3_BASE)
734 return 0; 710 return 0;
735#if L1_CODE_LENGTH != 0 711 if (cpu == 0 && IN_MEM(addr, BREAK_INSTR_SIZE, L1_CODE_START, L1_CODE_LENGTH))
736 if (cpu == 0 && addr >= L1_CODE_START
737 && addr + BREAK_INSTR_SIZE <= L1_CODE_START + L1_CODE_LENGTH)
738 return 0; 712 return 0;
739# ifdef CONFIG_SMP 713#ifdef CONFIG_SMP
740 else if (cpu == 1 && addr >= COREB_L1_CODE_START 714 else if (cpu == 1 && IN_MEM(addr, BREAK_INSTR_SIZE, COREB_L1_CODE_START, L1_CODE_LENGTH))
741 && addr + BREAK_INSTR_SIZE <= COREB_L1_CODE_START + L1_CODE_LENGTH)
742 return 0; 715 return 0;
743# endif
744#endif 716#endif
745#if L2_LENGTH != 0 717#if L2_LENGTH
746 if (addr >= L2_START 718 if (IN_MEM(addr, BREAK_INSTR_SIZE, L2_START, L2_LENGTH))
747 && addr + BREAK_INSTR_SIZE <= L2_START + L2_LENGTH)
748 return 0; 719 return 0;
749#endif 720#endif
750 721
@@ -756,13 +727,9 @@ int kgdb_arch_set_breakpoint(unsigned long addr, char *saved_instr)
756 int err; 727 int err;
757 int cpu = raw_smp_processor_id(); 728 int cpu = raw_smp_processor_id();
758 729
759 if ((cpu == 0 && (unsigned int)addr >= L1_CODE_START 730 if ((cpu == 0 && IN_MEM(addr, BREAK_INSTR_SIZE, L1_CODE_START, L1_CODE_LENGTH))
760 && (unsigned int)(addr + BREAK_INSTR_SIZE)
761 <= L1_CODE_START + L1_CODE_LENGTH)
762#ifdef CONFIG_SMP 731#ifdef CONFIG_SMP
763 || (cpu == 1 && (unsigned int)addr >= COREB_L1_CODE_START 732 || (cpu == 1 && IN_MEM(addr, BREAK_INSTR_SIZE, COREB_L1_CODE_START, L1_CODE_LENGTH))
764 && (unsigned int)(addr + BREAK_INSTR_SIZE)
765 <= COREB_L1_CODE_START + L1_CODE_LENGTH)
766#endif 733#endif
767 ) { 734 ) {
768 /* access L1 instruction SRAM */ 735 /* access L1 instruction SRAM */
@@ -788,9 +755,7 @@ int kgdb_arch_set_breakpoint(unsigned long addr, char *saved_instr)
788 755
789int kgdb_arch_remove_breakpoint(unsigned long addr, char *bundle) 756int kgdb_arch_remove_breakpoint(unsigned long addr, char *bundle)
790{ 757{
791 if ((unsigned int)addr >= L1_CODE_START && 758 if (IN_MEM(addr, BREAK_INSTR_SIZE, L1_CODE_START, L1_CODE_LENGTH)) {
792 (unsigned int)(addr + BREAK_INSTR_SIZE) <=
793 L1_CODE_START + L1_CODE_LENGTH) {
794 /* access L1 instruction SRAM */ 759 /* access L1 instruction SRAM */
795 if (dma_memcpy((void *)addr, bundle, BREAK_INSTR_SIZE) == NULL) 760 if (dma_memcpy((void *)addr, bundle, BREAK_INSTR_SIZE) == NULL)
796 return -EFAULT; 761 return -EFAULT;