diff options
| author | Mike Frysinger <vapier@gentoo.org> | 2011-03-30 04:09:26 -0400 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2011-05-25 08:13:42 -0400 |
| commit | 115103a9fe5c7b03149af7ea13f837c5e71924be (patch) | |
| tree | 8a18576acc975b4af9c5b85e35d4e4dfeec08c13 /arch/blackfin/mach-bf561 | |
| parent | 3dd666067d2b285724c828946e83100ea4c43d4b (diff) | |
Blackfin: bf533/bf537/bf561: convert to BFIN_IRQ helper
This brings the parts in line with newer ones, and makes things easier
to read at a glance.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf561')
| -rw-r--r-- | arch/blackfin/mach-bf561/include/mach/irq.h | 129 |
1 files changed, 64 insertions, 65 deletions
diff --git a/arch/blackfin/mach-bf561/include/mach/irq.h b/arch/blackfin/mach-bf561/include/mach/irq.h index 391091efcfe..d6998520f70 100644 --- a/arch/blackfin/mach-bf561/include/mach/irq.h +++ b/arch/blackfin/mach-bf561/include/mach/irq.h | |||
| @@ -11,93 +11,92 @@ | |||
| 11 | 11 | ||
| 12 | #define NR_PERI_INTS (2 * 32) | 12 | #define NR_PERI_INTS (2 * 32) |
| 13 | 13 | ||
| 14 | #define IVG_BASE 7 | 14 | #define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ |
| 15 | #define IRQ_PLL_WAKEUP (IVG_BASE + 0) /* PLL Wakeup Interrupt */ | 15 | #define IRQ_DMA1_ERROR BFIN_IRQ(1) /* DMA1 Error (general) */ |
| 16 | #define IRQ_DMA1_ERROR (IVG_BASE + 1) /* DMA1 Error (general) */ | ||
| 17 | #define IRQ_DMA_ERROR IRQ_DMA1_ERROR /* DMA1 Error (general) */ | 16 | #define IRQ_DMA_ERROR IRQ_DMA1_ERROR /* DMA1 Error (general) */ |
| 18 | #define IRQ_DMA2_ERROR (IVG_BASE + 2) /* DMA2 Error (general) */ | 17 | #define IRQ_DMA2_ERROR BFIN_IRQ(2) /* DMA2 Error (general) */ |
| 19 | #define IRQ_IMDMA_ERROR (IVG_BASE + 3) /* IMDMA Error Interrupt */ | 18 | #define IRQ_IMDMA_ERROR BFIN_IRQ(3) /* IMDMA Error Interrupt */ |
| 20 | #define IRQ_PPI1_ERROR (IVG_BASE + 4) /* PPI1 Error Interrupt */ | 19 | #define IRQ_PPI1_ERROR BFIN_IRQ(4) /* PPI1 Error Interrupt */ |
| 21 | #define IRQ_PPI_ERROR IRQ_PPI1_ERROR /* PPI1 Error Interrupt */ | 20 | #define IRQ_PPI_ERROR IRQ_PPI1_ERROR /* PPI1 Error Interrupt */ |
| 22 | #define IRQ_PPI2_ERROR (IVG_BASE + 5) /* PPI2 Error Interrupt */ | 21 | #define IRQ_PPI2_ERROR BFIN_IRQ(5) /* PPI2 Error Interrupt */ |
| 23 | #define IRQ_SPORT0_ERROR (IVG_BASE + 6) /* SPORT0 Error Interrupt */ | 22 | #define IRQ_SPORT0_ERROR BFIN_IRQ(6) /* SPORT0 Error Interrupt */ |
| 24 | #define IRQ_SPORT1_ERROR (IVG_BASE + 7) /* SPORT1 Error Interrupt */ | 23 | #define IRQ_SPORT1_ERROR BFIN_IRQ(7) /* SPORT1 Error Interrupt */ |
| 25 | #define IRQ_SPI_ERROR (IVG_BASE + 8) /* SPI Error Interrupt */ | 24 | #define IRQ_SPI_ERROR BFIN_IRQ(8) /* SPI Error Interrupt */ |
| 26 | #define IRQ_UART_ERROR (IVG_BASE + 9) /* UART Error Interrupt */ | 25 | #define IRQ_UART_ERROR BFIN_IRQ(9) /* UART Error Interrupt */ |
| 27 | #define IRQ_RESERVED_ERROR (IVG_BASE + 10) /* Reversed */ | 26 | #define IRQ_RESERVED_ERROR BFIN_IRQ(10) /* Reversed */ |
| 28 | #define IRQ_DMA1_0 (IVG_BASE + 11) /* DMA1 0 Interrupt(PPI1) */ | 27 | #define IRQ_DMA1_0 BFIN_IRQ(11) /* DMA1 0 Interrupt(PPI1) */ |
| 29 | #define IRQ_PPI IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */ | 28 | #define IRQ_PPI IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */ |
| 30 | #define IRQ_PPI0 IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */ | 29 | #define IRQ_PPI0 IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */ |
| 31 | #define IRQ_DMA1_1 (IVG_BASE + 12) /* DMA1 1 Interrupt(PPI2) */ | 30 | #define IRQ_DMA1_1 BFIN_IRQ(12) /* DMA1 1 Interrupt(PPI2) */ |
| 32 | #define IRQ_PPI1 IRQ_DMA1_1 /* DMA1 1 Interrupt(PPI2) */ | 31 | #define IRQ_PPI1 IRQ_DMA1_1 /* DMA1 1 Interrupt(PPI2) */ |
| 33 | #define IRQ_DMA1_2 (IVG_BASE + 13) /* DMA1 2 Interrupt */ | 32 | #define IRQ_DMA1_2 BFIN_IRQ(13) /* DMA1 2 Interrupt */ |
| 34 | #define IRQ_DMA1_3 (IVG_BASE + 14) /* DMA1 3 Interrupt */ | 33 | #define IRQ_DMA1_3 BFIN_IRQ(14) /* DMA1 3 Interrupt */ |
| 35 | #define IRQ_DMA1_4 (IVG_BASE + 15) /* DMA1 4 Interrupt */ | 34 | #define IRQ_DMA1_4 BFIN_IRQ(15) /* DMA1 4 Interrupt */ |
| 36 | #define IRQ_DMA1_5 (IVG_BASE + 16) /* DMA1 5 Interrupt */ | 35 | #define IRQ_DMA1_5 BFIN_IRQ(16) /* DMA1 5 Interrupt */ |
| 37 | #define IRQ_DMA1_6 (IVG_BASE + 17) /* DMA1 6 Interrupt */ | 36 | #define IRQ_DMA1_6 BFIN_IRQ(17) /* DMA1 6 Interrupt */ |
| 38 | #define IRQ_DMA1_7 (IVG_BASE + 18) /* DMA1 7 Interrupt */ | 37 | #define IRQ_DMA1_7 BFIN_IRQ(18) /* DMA1 7 Interrupt */ |
| 39 | #define IRQ_DMA1_8 (IVG_BASE + 19) /* DMA1 8 Interrupt */ | 38 | #define IRQ_DMA1_8 BFIN_IRQ(19) /* DMA1 8 Interrupt */ |
| 40 | #define IRQ_DMA1_9 (IVG_BASE + 20) /* DMA1 9 Interrupt */ | 39 | #define IRQ_DMA1_9 BFIN_IRQ(20) /* DMA1 9 Interrupt */ |
| 41 | #define IRQ_DMA1_10 (IVG_BASE + 21) /* DMA1 10 Interrupt */ | 40 | #define IRQ_DMA1_10 BFIN_IRQ(21) /* DMA1 10 Interrupt */ |
| 42 | #define IRQ_DMA1_11 (IVG_BASE + 22) /* DMA1 11 Interrupt */ | 41 | #define IRQ_DMA1_11 BFIN_IRQ(22) /* DMA1 11 Interrupt */ |
| 43 | #define IRQ_DMA2_0 (IVG_BASE + 23) /* DMA2 0 (SPORT0 RX) */ | 42 | #define IRQ_DMA2_0 BFIN_IRQ(23) /* DMA2 0 (SPORT0 RX) */ |
| 44 | #define IRQ_SPORT0_RX IRQ_DMA2_0 /* DMA2 0 (SPORT0 RX) */ | 43 | #define IRQ_SPORT0_RX IRQ_DMA2_0 /* DMA2 0 (SPORT0 RX) */ |
| 45 | #define IRQ_DMA2_1 (IVG_BASE + 24) /* DMA2 1 (SPORT0 TX) */ | 44 | #define IRQ_DMA2_1 BFIN_IRQ(24) /* DMA2 1 (SPORT0 TX) */ |
| 46 | #define IRQ_SPORT0_TX IRQ_DMA2_1 /* DMA2 1 (SPORT0 TX) */ | 45 | #define IRQ_SPORT0_TX IRQ_DMA2_1 /* DMA2 1 (SPORT0 TX) */ |
| 47 | #define IRQ_DMA2_2 (IVG_BASE + 25) /* DMA2 2 (SPORT1 RX) */ | 46 | #define IRQ_DMA2_2 BFIN_IRQ(25) /* DMA2 2 (SPORT1 RX) */ |
| 48 | #define IRQ_SPORT1_RX IRQ_DMA2_2 /* DMA2 2 (SPORT1 RX) */ | 47 | #define IRQ_SPORT1_RX IRQ_DMA2_2 /* DMA2 2 (SPORT1 RX) */ |
| 49 | #define IRQ_DMA2_3 (IVG_BASE + 26) /* DMA2 3 (SPORT2 TX) */ | 48 | #define IRQ_DMA2_3 BFIN_IRQ(26) /* DMA2 3 (SPORT2 TX) */ |
| 50 | #define IRQ_SPORT1_TX IRQ_DMA2_3 /* DMA2 3 (SPORT2 TX) */ | 49 | #define IRQ_SPORT1_TX IRQ_DMA2_3 /* DMA2 3 (SPORT2 TX) */ |
| 51 | #define IRQ_DMA2_4 (IVG_BASE + 27) /* DMA2 4 (SPI) */ | 50 | #define IRQ_DMA2_4 BFIN_IRQ(27) /* DMA2 4 (SPI) */ |
| 52 | #define IRQ_SPI IRQ_DMA2_4 /* DMA2 4 (SPI) */ | 51 | #define IRQ_SPI IRQ_DMA2_4 /* DMA2 4 (SPI) */ |
| 53 | #define IRQ_DMA2_5 (IVG_BASE + 28) /* DMA2 5 (UART RX) */ | 52 | #define IRQ_DMA2_5 BFIN_IRQ(28) /* DMA2 5 (UART RX) */ |
| 54 | #define IRQ_UART_RX IRQ_DMA2_5 /* DMA2 5 (UART RX) */ | 53 | #define IRQ_UART_RX IRQ_DMA2_5 /* DMA2 5 (UART RX) */ |
| 55 | #define IRQ_DMA2_6 (IVG_BASE + 29) /* DMA2 6 (UART TX) */ | 54 | #define IRQ_DMA2_6 BFIN_IRQ(29) /* DMA2 6 (UART TX) */ |
| 56 | #define IRQ_UART_TX IRQ_DMA2_6 /* DMA2 6 (UART TX) */ | 55 | #define IRQ_UART_TX IRQ_DMA2_6 /* DMA2 6 (UART TX) */ |
| 57 | #define IRQ_DMA2_7 (IVG_BASE + 30) /* DMA2 7 Interrupt */ | 56 | #define IRQ_DMA2_7 BFIN_IRQ(30) /* DMA2 7 Interrupt */ |
| 58 | #define IRQ_DMA2_8 (IVG_BASE + 31) /* DMA2 8 Interrupt */ | 57 | #define IRQ_DMA2_8 BFIN_IRQ(31) /* DMA2 8 Interrupt */ |
| 59 | #define IRQ_DMA2_9 (IVG_BASE + 32) /* DMA2 9 Interrupt */ | 58 | #define IRQ_DMA2_9 BFIN_IRQ(32) /* DMA2 9 Interrupt */ |
| 60 | #define IRQ_DMA2_10 (IVG_BASE + 33) /* DMA2 10 Interrupt */ | 59 | #define IRQ_DMA2_10 BFIN_IRQ(33) /* DMA2 10 Interrupt */ |
| 61 | #define IRQ_DMA2_11 (IVG_BASE + 34) /* DMA2 11 Interrupt */ | 60 | #define IRQ_DMA2_11 BFIN_IRQ(34) /* DMA2 11 Interrupt */ |
| 62 | #define IRQ_TIMER0 (IVG_BASE + 35) /* TIMER 0 Interrupt */ | 61 | #define IRQ_TIMER0 BFIN_IRQ(35) /* TIMER 0 Interrupt */ |
| 63 | #define IRQ_TIMER1 (IVG_BASE + 36) /* TIMER 1 Interrupt */ | 62 | #define IRQ_TIMER1 BFIN_IRQ(36) /* TIMER 1 Interrupt */ |
| 64 | #define IRQ_TIMER2 (IVG_BASE + 37) /* TIMER 2 Interrupt */ | 63 | #define IRQ_TIMER2 BFIN_IRQ(37) /* TIMER 2 Interrupt */ |
| 65 | #define IRQ_TIMER3 (IVG_BASE + 38) /* TIMER 3 Interrupt */ | 64 | #define IRQ_TIMER3 BFIN_IRQ(38) /* TIMER 3 Interrupt */ |
| 66 | #define IRQ_TIMER4 (IVG_BASE + 39) /* TIMER 4 Interrupt */ | 65 | #define IRQ_TIMER4 BFIN_IRQ(39) /* TIMER 4 Interrupt */ |
| 67 | #define IRQ_TIMER5 (IVG_BASE + 40) /* TIMER 5 Interrupt */ | 66 | #define IRQ_TIMER5 BFIN_IRQ(40) /* TIMER 5 Interrupt */ |
| 68 | #define IRQ_TIMER6 (IVG_BASE + 41) /* TIMER 6 Interrupt */ | 67 | #define IRQ_TIMER6 BFIN_IRQ(41) /* TIMER 6 Interrupt */ |
| 69 | #define IRQ_TIMER7 (IVG_BASE + 42) /* TIMER 7 Interrupt */ | 68 | #define IRQ_TIMER7 BFIN_IRQ(42) /* TIMER 7 Interrupt */ |
| 70 | #define IRQ_TIMER8 (IVG_BASE + 43) /* TIMER 8 Interrupt */ | 69 | #define IRQ_TIMER8 BFIN_IRQ(43) /* TIMER 8 Interrupt */ |
| 71 | #define IRQ_TIMER9 (IVG_BASE + 44) /* TIMER 9 Interrupt */ | 70 | #define IRQ_TIMER9 BFIN_IRQ(44) /* TIMER 9 Interrupt */ |
| 72 | #define IRQ_TIMER10 (IVG_BASE + 45) /* TIMER 10 Interrupt */ | 71 | #define IRQ_TIMER10 BFIN_IRQ(45) /* TIMER 10 Interrupt */ |
| 73 | #define IRQ_TIMER11 (IVG_BASE + 46) /* TIMER 11 Interrupt */ | 72 | #define IRQ_TIMER11 BFIN_IRQ(46) /* TIMER 11 Interrupt */ |
| 74 | #define IRQ_PROG0_INTA (IVG_BASE + 47) /* Programmable Flags0 A (8) */ | 73 | #define IRQ_PROG0_INTA BFIN_IRQ(47) /* Programmable Flags0 A (8) */ |
| 75 | #define IRQ_PROG_INTA IRQ_PROG0_INTA /* Programmable Flags0 A (8) */ | 74 | #define IRQ_PROG_INTA IRQ_PROG0_INTA /* Programmable Flags0 A (8) */ |
| 76 | #define IRQ_PROG0_INTB (IVG_BASE + 48) /* Programmable Flags0 B (8) */ | 75 | #define IRQ_PROG0_INTB BFIN_IRQ(48) /* Programmable Flags0 B (8) */ |
| 77 | #define IRQ_PROG_INTB IRQ_PROG0_INTB /* Programmable Flags0 B (8) */ | 76 | #define IRQ_PROG_INTB IRQ_PROG0_INTB /* Programmable Flags0 B (8) */ |
| 78 | #define IRQ_PROG1_INTA (IVG_BASE + 49) /* Programmable Flags1 A (8) */ | 77 | #define IRQ_PROG1_INTA BFIN_IRQ(49) /* Programmable Flags1 A (8) */ |
| 79 | #define IRQ_PROG1_INTB (IVG_BASE + 50) /* Programmable Flags1 B (8) */ | 78 | #define IRQ_PROG1_INTB BFIN_IRQ(50) /* Programmable Flags1 B (8) */ |
| 80 | #define IRQ_PROG2_INTA (IVG_BASE + 51) /* Programmable Flags2 A (8) */ | 79 | #define IRQ_PROG2_INTA BFIN_IRQ(51) /* Programmable Flags2 A (8) */ |
| 81 | #define IRQ_PROG2_INTB (IVG_BASE + 52) /* Programmable Flags2 B (8) */ | 80 | #define IRQ_PROG2_INTB BFIN_IRQ(52) /* Programmable Flags2 B (8) */ |
| 82 | #define IRQ_DMA1_WRRD0 (IVG_BASE + 53) /* MDMA1 0 write/read INT */ | 81 | #define IRQ_DMA1_WRRD0 BFIN_IRQ(53) /* MDMA1 0 write/read INT */ |
| 83 | #define IRQ_DMA_WRRD0 IRQ_DMA1_WRRD0 /* MDMA1 0 write/read INT */ | 82 | #define IRQ_DMA_WRRD0 IRQ_DMA1_WRRD0 /* MDMA1 0 write/read INT */ |
| 84 | #define IRQ_MEM_DMA0 IRQ_DMA1_WRRD0 | 83 | #define IRQ_MEM_DMA0 IRQ_DMA1_WRRD0 |
| 85 | #define IRQ_DMA1_WRRD1 (IVG_BASE + 54) /* MDMA1 1 write/read INT */ | 84 | #define IRQ_DMA1_WRRD1 BFIN_IRQ(54) /* MDMA1 1 write/read INT */ |
| 86 | #define IRQ_DMA_WRRD1 IRQ_DMA1_WRRD1 /* MDMA1 1 write/read INT */ | 85 | #define IRQ_DMA_WRRD1 IRQ_DMA1_WRRD1 /* MDMA1 1 write/read INT */ |
| 87 | #define IRQ_MEM_DMA1 IRQ_DMA1_WRRD1 | 86 | #define IRQ_MEM_DMA1 IRQ_DMA1_WRRD1 |
| 88 | #define IRQ_DMA2_WRRD0 (IVG_BASE + 55) /* MDMA2 0 write/read INT */ | 87 | #define IRQ_DMA2_WRRD0 BFIN_IRQ(55) /* MDMA2 0 write/read INT */ |
| 89 | #define IRQ_MEM_DMA2 IRQ_DMA2_WRRD0 | 88 | #define IRQ_MEM_DMA2 IRQ_DMA2_WRRD0 |
| 90 | #define IRQ_DMA2_WRRD1 (IVG_BASE + 56) /* MDMA2 1 write/read INT */ | 89 | #define IRQ_DMA2_WRRD1 BFIN_IRQ(56) /* MDMA2 1 write/read INT */ |
| 91 | #define IRQ_MEM_DMA3 IRQ_DMA2_WRRD1 | 90 | #define IRQ_MEM_DMA3 IRQ_DMA2_WRRD1 |
| 92 | #define IRQ_IMDMA_WRRD0 (IVG_BASE + 57) /* IMDMA 0 write/read INT */ | 91 | #define IRQ_IMDMA_WRRD0 BFIN_IRQ(57) /* IMDMA 0 write/read INT */ |
| 93 | #define IRQ_IMEM_DMA0 IRQ_IMDMA_WRRD0 | 92 | #define IRQ_IMEM_DMA0 IRQ_IMDMA_WRRD0 |
| 94 | #define IRQ_IMDMA_WRRD1 (IVG_BASE + 58) /* IMDMA 1 write/read INT */ | 93 | #define IRQ_IMDMA_WRRD1 BFIN_IRQ(58) /* IMDMA 1 write/read INT */ |
| 95 | #define IRQ_IMEM_DMA1 IRQ_IMDMA_WRRD1 | 94 | #define IRQ_IMEM_DMA1 IRQ_IMDMA_WRRD1 |
| 96 | #define IRQ_WATCH (IVG_BASE + 59) /* Watch Dog Timer */ | 95 | #define IRQ_WATCH BFIN_IRQ(59) /* Watch Dog Timer */ |
| 97 | #define IRQ_RESERVED_1 (IVG_BASE + 60) /* Reserved interrupt */ | 96 | #define IRQ_RESERVED_1 BFIN_IRQ(60) /* Reserved interrupt */ |
| 98 | #define IRQ_RESERVED_2 (IVG_BASE + 61) /* Reserved interrupt */ | 97 | #define IRQ_RESERVED_2 BFIN_IRQ(61) /* Reserved interrupt */ |
| 99 | #define IRQ_SUPPLE_0 (IVG_BASE + 62) /* Supplemental interrupt 0 */ | 98 | #define IRQ_SUPPLE_0 BFIN_IRQ(62) /* Supplemental interrupt 0 */ |
| 100 | #define IRQ_SUPPLE_1 (IVG_BASE + 63) /* Supplemental interrupt 1 */ | 99 | #define IRQ_SUPPLE_1 BFIN_IRQ(63) /* supplemental interrupt 1 */ |
| 101 | 100 | ||
| 102 | #define SYS_IRQS 71 | 101 | #define SYS_IRQS 71 |
| 103 | 102 | ||