diff options
author | Sonic Zhang <sonic.zhang@analog.com> | 2007-11-21 10:49:52 -0500 |
---|---|---|
committer | Bryan Wu <bryan.wu@analog.com> | 2007-11-21 10:49:52 -0500 |
commit | e40540b304d5d15c344585c4a7b3116e73add2db (patch) | |
tree | e991ef8446686a84640f77f76c2f88d89e68b8ff /arch/blackfin/mach-bf548 | |
parent | 28a44d4bd6bdc7d013405bfc2aa7f126d39a7b2b (diff) |
Blackfin arch: fix bug NOR Flash MTD mount fail
Config EBIU flash mode properly. EBIU_MODE EBIU_FCTL
EBIU_MBSCTL register should be configurd to Flash
mode.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'arch/blackfin/mach-bf548')
-rw-r--r-- | arch/blackfin/mach-bf548/head.S | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/blackfin/mach-bf548/head.S b/arch/blackfin/mach-bf548/head.S index 3071c243d42..74b34c7f362 100644 --- a/arch/blackfin/mach-bf548/head.S +++ b/arch/blackfin/mach-bf548/head.S | |||
@@ -158,6 +158,27 @@ ENTRY(__stext) | |||
158 | w[p2] = r0; | 158 | w[p2] = r0; |
159 | ssync; | 159 | ssync; |
160 | 160 | ||
161 | p2.h = hi(EBIU_MBSCTL); | ||
162 | p2.l = lo(EBIU_MBSCTL); | ||
163 | r0.h = hi(CONFIG_EBIU_MBSCTLVAL); | ||
164 | r0.l = lo(CONFIG_EBIU_MBSCTLVAL); | ||
165 | [p2] = r0; | ||
166 | ssync; | ||
167 | |||
168 | p2.h = hi(EBIU_MODE); | ||
169 | p2.l = lo(EBIU_MODE); | ||
170 | r0.h = hi(CONFIG_EBIU_MODEVAL); | ||
171 | r0.l = lo(CONFIG_EBIU_MODEVAL); | ||
172 | [p2] = r0; | ||
173 | ssync; | ||
174 | |||
175 | p2.h = hi(EBIU_FCTL); | ||
176 | p2.l = lo(EBIU_FCTL); | ||
177 | r0.h = hi(CONFIG_EBIU_FCTLVAL); | ||
178 | r0.l = lo(CONFIG_EBIU_FCTLVAL); | ||
179 | [p2] = r0; | ||
180 | ssync; | ||
181 | |||
161 | /* This section keeps the processor in supervisor mode | 182 | /* This section keeps the processor in supervisor mode |
162 | * during kernel boot. Switches to user mode at end of boot. | 183 | * during kernel boot. Switches to user mode at end of boot. |
163 | * See page 3-9 of Hardware Reference manual for documentation. | 184 | * See page 3-9 of Hardware Reference manual for documentation. |