Blackfin arch: merge adeos blackfin part to arch/blackfin/

[Mike Frysinger <vapier.adi@gmail.com>:
 - handle bf531/bf532/bf534/bf536 variants in ipipe.h
 - cleanup IPIPE logic for bfin_set_irq_handler()
 - cleanup ipipe asm code a bit and add missing ENDPROC()
 - simplify IPIPE code in trap_c
 - unify some of the IPIPE code and fix style
 - simplify DO_IRQ_L1 handling with ipipe code
 - revert IRQ_SW_INT# addition from ipipe merge
 - remove duplicate get_{c,s}clk() prototypes
]

Signed-off-by: Yi Li <yi.li@analog.com>
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>

4 files changed, 45 insertions, 45 deletions

diff --git a/arch/blackfin/mach-bf537/Kconfig b/arch/blackfin/mach-bf537/Kconfig
index 8255374c04a..bbc08fd4f12 100644
--- a/arch/blackfin/mach-bf537/Kconfig
+++ b/arch/blackfin/mach-bf537/Kconfig
@@ -64,29 +64,29 @@ config IRQ_MAC_RX
 config IRQ_MAC_TX
         int "IRQ_MAC_TX"
         default 11
-config IRQ_TMR0
-        int "IRQ_TMR0"
-        default 12
-config IRQ_TMR1
-        int "IRQ_TMR1"
+config IRQ_TIMER0
+        int "IRQ_TIMER0"
+        default 8
+config IRQ_TIMER1
+        int "IRQ_TIMER1"
         default 12
-config IRQ_TMR2
-        int "IRQ_TMR2"
+config IRQ_TIMER2
+        int "IRQ_TIMER2"
         default 12
-config IRQ_TMR3
-        int "IRQ_TMR3"
+config IRQ_TIMER3
+        int "IRQ_TIMER3"
         default 12
-config IRQ_TMR4
-        int "IRQ_TMR4"
+config IRQ_TIMER4
+        int "IRQ_TIMER4"
         default 12
-config IRQ_TMR5
-        int "IRQ_TMR5"
+config IRQ_TIMER5
+        int "IRQ_TIMER5"
         default 12
-config IRQ_TMR6
-        int "IRQ_TMR6"
+config IRQ_TIMER6
+        int "IRQ_TIMER6"
         default 12
-config IRQ_TMR7
-        int "IRQ_TMR7"
+config IRQ_TIMER7
+        int "IRQ_TIMER7"
         default 12
 config IRQ_PROG_INTA
         int "IRQ_PROG_INTA"
diff --git a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
index f3416923be6..5f8b5f845be 100644
--- a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
+++ b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
@@ -1783,7 +1783,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
         if (val == bfin_read_PLL_CTL())
                 return;
 
-        local_irq_save(flags);
+        local_irq_save_hw(flags);
         /* Enable the PLL Wakeup bit in SIC IWR */
         iwr = bfin_read32(SIC_IWR);
         /* Only allow PPL Wakeup) */
@@ -1794,7 +1794,7 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val)
         asm("IDLE;");
 
         bfin_write32(SIC_IWR, iwr);
-        local_irq_restore(flags);
+        local_irq_restore_hw(flags);
 }
 
 /* Writing to VR_CTL initiates a PLL relock sequence. */
@@ -1805,7 +1805,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
         if (val == bfin_read_VR_CTL())
                 return;
 
-        local_irq_save(flags);
+        local_irq_save_hw(flags);
         /* Enable the PLL Wakeup bit in SIC IWR */
         iwr = bfin_read32(SIC_IWR);
         /* Only allow PPL Wakeup) */
@@ -1816,7 +1816,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
         asm("IDLE;");
 
         bfin_write32(SIC_IWR, iwr);
-        local_irq_restore(flags);
+        local_irq_restore_hw(flags);
 }
 
 #endif                          /* _CDEF_BF534_H */
diff --git a/arch/blackfin/mach-bf537/include/mach/irq.h b/arch/blackfin/mach-bf537/include/mach/irq.h
index 2e68a8a1e73..b2a71d5d4e5 100644
--- a/arch/blackfin/mach-bf537/include/mach/irq.h
+++ b/arch/blackfin/mach-bf537/include/mach/irq.h
@@ -82,14 +82,14 @@
 #define IRQ_CAN_TX          23  /*CAN Transmit Interrupt */
 #define IRQ_MAC_RX          24  /*DMA1 (Ethernet RX) Interrupt */
 #define IRQ_MAC_TX          25  /*DMA2 (Ethernet TX) Interrupt */
-#define IRQ_TMR0            26  /*Timer 0 */
-#define IRQ_TMR1            27  /*Timer 1 */
-#define IRQ_TMR2            28  /*Timer 2 */
-#define IRQ_TMR3            29  /*Timer 3 */
-#define IRQ_TMR4            30  /*Timer 4 */
-#define IRQ_TMR5            31  /*Timer 5 */
-#define IRQ_TMR6            32  /*Timer 6 */
-#define IRQ_TMR7            33  /*Timer 7 */
+#define IRQ_TIMER0            26        /*Timer 0 */
+#define IRQ_TIMER1            27        /*Timer 1 */
+#define IRQ_TIMER2            28        /*Timer 2 */
+#define IRQ_TIMER3            29        /*Timer 3 */
+#define IRQ_TIMER4            30        /*Timer 4 */
+#define IRQ_TIMER5            31        /*Timer 5 */
+#define IRQ_TIMER6            32        /*Timer 6 */
+#define IRQ_TIMER7            33        /*Timer 7 */
 #define IRQ_PROG_INTA       34  /* PF Ports F&G (PF15:0) Interrupt A */
 #define IRQ_PORTG_INTB      35  /* PF Port G (PF15:0) Interrupt B */
 #define IRQ_MEM_DMA0        36  /*(Memory DMA Stream 0) */
@@ -195,16 +195,16 @@
 #define IRQ_CAN_TX_POS      0
 #define IRQ_MAC_RX_POS      4
 #define IRQ_MAC_TX_POS      8
-#define IRQ_TMR0_POS        12
-#define IRQ_TMR1_POS        16
-#define IRQ_TMR2_POS        20
-#define IRQ_TMR3_POS        24
-#define IRQ_TMR4_POS        28
+#define IRQ_TIMER0_POS        12
+#define IRQ_TIMER1_POS        16
+#define IRQ_TIMER2_POS        20
+#define IRQ_TIMER3_POS        24
+#define IRQ_TIMER4_POS        28
 
 /* IAR3 BIT FIELDS*/
-#define IRQ_TMR5_POS        0
-#define IRQ_TMR6_POS        4
-#define IRQ_TMR7_POS        8
+#define IRQ_TIMER5_POS        0
+#define IRQ_TIMER6_POS        4
+#define IRQ_TIMER7_POS        8
 #define IRQ_PROG_INTA_POS   12
 #define IRQ_PORTG_INTB_POS   16
 #define IRQ_MEM_DMA0_POS    20
diff --git a/arch/blackfin/mach-bf537/ints-priority.c b/arch/blackfin/mach-bf537/ints-priority.c
index b1300b3f181..51c48087e03 100644
--- a/arch/blackfin/mach-bf537/ints-priority.c
+++ b/arch/blackfin/mach-bf537/ints-priority.c
@@ -55,15 +55,15 @@ void __init program_IAR(void)
         bfin_write_SIC_IAR2(((CONFIG_IRQ_CAN_TX - 7) << IRQ_CAN_TX_POS) |
                             ((CONFIG_IRQ_MAC_RX - 7) << IRQ_MAC_RX_POS) |
                             ((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) |
-                            ((CONFIG_IRQ_TMR0 - 7) << IRQ_TMR0_POS) |
-                            ((CONFIG_IRQ_TMR1 - 7) << IRQ_TMR1_POS) |
-                            ((CONFIG_IRQ_TMR2 - 7) << IRQ_TMR2_POS) |
-                            ((CONFIG_IRQ_TMR3 - 7) << IRQ_TMR3_POS) |
-                            ((CONFIG_IRQ_TMR4 - 7) << IRQ_TMR4_POS));
+                            ((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
+                            ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) |
+                            ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
+                            ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
+                            ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS));
 
-        bfin_write_SIC_IAR3(((CONFIG_IRQ_TMR5 - 7) << IRQ_TMR5_POS) |
-                            ((CONFIG_IRQ_TMR6 - 7) << IRQ_TMR6_POS) |
-                            ((CONFIG_IRQ_TMR7 - 7) << IRQ_TMR7_POS) |
+        bfin_write_SIC_IAR3(((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
+                            ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
+                            ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) |
                             ((CONFIG_IRQ_PROG_INTA - 7) << IRQ_PROG_INTA_POS) |
                             ((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) |
                             ((CONFIG_IRQ_MEM_DMA0 - 7) << IRQ_MEM_DMA0_POS) |