[ARM] 3832/1: iop3xx: coding style cleanup

Since the iop32x code isn't iop321-specific, and the iop33x code isn't
iop331-specfic, do a s/iop321/iop32x/ and s/iop331/iop33x/, and tidy up
the code to conform to the coding style guidelines somewhat better.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

11 files changed, 127 insertions, 146 deletions

diff --git a/arch/arm/mach-iop32x/Kconfig b/arch/arm/mach-iop32x/Kconfig
index ff8a77a8866..d7abfaa525c 100644
--- a/arch/arm/mach-iop32x/Kconfig
+++ b/arch/arm/mach-iop32x/Kconfig
@@ -8,13 +8,14 @@ config ARCH_IQ80321
         bool "Enable support for IQ80321"
         help
           Say Y here if you want to run your kernel on the Intel IQ80321
-          evaluation kit for the IOP321 chipset.
+          evaluation kit for the IOP321 processor.
 
 config ARCH_IQ31244
-        bool "Enable support for IQ31244"
+        bool "Enable support for EP80219/IQ31244"
         help
-          Say Y here if you want to run your kernel on the Intel IQ31244
-          evaluation kit for the IOP321 chipset.
+          Say Y here if you want to run your kernel on the Intel EP80219
+          evaluation kit for the Intel 80219 processor (a IOP321 variant)
+          or the IQ31244 evaluation kit for the IOP321 processor.
 
 endmenu
 
diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c
index 88b77d32b0a..be4aedfa0de 100644
--- a/arch/arm/mach-iop32x/iq31244.c
+++ b/arch/arm/mach-iop32x/iq31244.c
@@ -98,16 +98,16 @@ ep80219_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 
         if (slot == 0) {
                 /* CFlash */
-                irq = IRQ_IOP321_XINT1;
+                irq = IRQ_IOP32X_XINT1;
         } else if (slot == 1) {
                 /* 82551 Pro 100 */
-                irq = IRQ_IOP321_XINT0;
+                irq = IRQ_IOP32X_XINT0;
         } else if (slot == 2) {
                 /* PCI-X Slot */
-                irq = IRQ_IOP321_XINT3;
+                irq = IRQ_IOP32X_XINT3;
         } else if (slot == 3) {
                 /* SATA */
-                irq = IRQ_IOP321_XINT2;
+                irq = IRQ_IOP32X_XINT2;
         } else {
                 printk(KERN_ERR "ep80219_pci_map_irq() called for unknown "
                         "device PCI:%d:%d:%d\n", dev->bus->number,
@@ -134,18 +134,18 @@ iq31244_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 
         if (slot == 0) {
                 /* CFlash */
-                irq = IRQ_IOP321_XINT1;
+                irq = IRQ_IOP32X_XINT1;
         } else if (slot == 1) {
                 /* SATA */
-                irq = IRQ_IOP321_XINT2;
+                irq = IRQ_IOP32X_XINT2;
         } else if (slot == 2) {
                 /* PCI-X Slot */
-                irq = IRQ_IOP321_XINT3;
+                irq = IRQ_IOP32X_XINT3;
         } else if (slot == 3) {
                 /* 82546 GigE */
-                irq = IRQ_IOP321_XINT0;
+                irq = IRQ_IOP32X_XINT0;
         } else {
-                printk(KERN_ERR "iq31244_pci_map_irq() called for unknown "
+                printk(KERN_ERR "iq31244_pci_map_irq called for unknown "
                         "device PCI:%d:%d:%d\n", dev->bus->number,
                         PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
                 irq = -1;
@@ -206,7 +206,7 @@ static struct plat_serial8250_port iq31244_serial_port[] = {
         {
                 .mapbase        = IQ31244_UART,
                 .membase        = (char *)IQ31244_UART,
-                .irq            = IRQ_IOP321_XINT1,
+                .irq            = IRQ_IOP32X_XINT1,
                 .flags          = UPF_SKIP_TEST,
                 .iotype         = UPIO_MEM,
                 .regshift       = 0,
@@ -287,7 +287,7 @@ MACHINE_START(IQ31244, "Intel IQ31244")
         .io_pg_offst    = ((IQ31244_UART) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = iq31244_map_io,
-        .init_irq       = iop321_init_irq,
+        .init_irq       = iop32x_init_irq,
         .timer          = &iq31244_timer,
         .init_machine   = iq31244_init_machine,
 MACHINE_END
diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c
index 3c9b8627175..1f37b550188 100644
--- a/arch/arm/mach-iop32x/iq80321.c
+++ b/arch/arm/mach-iop32x/iq80321.c
@@ -78,19 +78,19 @@ iq80321_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 
         if ((slot == 2 || slot == 6) && pin == 1) {
                 /* PCI-X Slot INTA */
-                irq = IRQ_IOP321_XINT2;
+                irq = IRQ_IOP32X_XINT2;
         } else if ((slot == 2 || slot == 6) && pin == 2) {
                 /* PCI-X Slot INTA */
-                irq = IRQ_IOP321_XINT3;
+                irq = IRQ_IOP32X_XINT3;
         } else if ((slot == 2 || slot == 6) && pin == 3) {
                 /* PCI-X Slot INTA */
-                irq = IRQ_IOP321_XINT0;
+                irq = IRQ_IOP32X_XINT0;
         } else if ((slot == 2 || slot == 6) && pin == 4) {
                 /* PCI-X Slot INTA */
-                irq = IRQ_IOP321_XINT1;
+                irq = IRQ_IOP32X_XINT1;
         } else if (slot == 4 || slot == 8) {
                 /* Gig-E */
-                irq = IRQ_IOP321_XINT0;
+                irq = IRQ_IOP32X_XINT0;
         } else {
                 printk(KERN_ERR "iq80321_pci_map_irq() called for unknown "
                         "device PCI:%d:%d:%d\n", dev->bus->number,
@@ -148,7 +148,7 @@ static struct plat_serial8250_port iq80321_serial_port[] = {
         {
                 .mapbase        = IQ80321_UART,
                 .membase        = (char *)IQ80321_UART,
-                .irq            = IRQ_IOP321_XINT1,
+                .irq            = IRQ_IOP32X_XINT1,
                 .flags          = UPF_SKIP_TEST,
                 .iotype         = UPIO_MEM,
                 .regshift       = 0,
@@ -187,7 +187,7 @@ MACHINE_START(IQ80321, "Intel IQ80321")
         .io_pg_offst    = ((IQ80321_UART) >> 18) & 0xfffc,
         .boot_params    = 0xa0000100,
         .map_io         = iq80321_map_io,
-        .init_irq       = iop321_init_irq,
+        .init_irq       = iop32x_init_irq,
         .timer          = &iq80321_timer,
         .init_machine   = iq80321_init_machine,
 MACHINE_END
diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c
index ff049e02f5f..21294be5a36 100644
--- a/arch/arm/mach-iop32x/irq.c
+++ b/arch/arm/mach-iop32x/irq.c
@@ -1,5 +1,5 @@
 /*
- * linux/arch/arm/mach-iop32x/irq.c
+ * arch/arm/mach-iop32x/irq.c
  *
  * Generic IOP32X IRQ handling functionality
  *
@@ -9,76 +9,66 @@
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
- *
- * Added IOP3XX chipset and IQ80321 board masking code.
- *
  */
+
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/list.h>
-
 #include <asm/mach/irq.h>
 #include <asm/irq.h>
 #include <asm/hardware.h>
-
 #include <asm/mach-types.h>
 
-static u32 iop321_mask /* = 0 */;
+static u32 iop32x_mask;
 
 static inline void intctl_write(u32 val)
 {
         iop3xx_cp6_enable();
-        asm volatile("mcr p6,0,%0,c0,c0,0"::"r" (val));
+        asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
         iop3xx_cp6_disable();
 }
 
 static inline void intstr_write(u32 val)
 {
         iop3xx_cp6_enable();
-        asm volatile("mcr p6,0,%0,c4,c0,0"::"r" (val));
+        asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val));
         iop3xx_cp6_disable();
 }
 
 static void
-iop321_irq_mask (unsigned int irq)
+iop32x_irq_mask(unsigned int irq)
 {
-
-        iop321_mask &= ~(1 << irq);
-
-        intctl_write(iop321_mask);
+        iop32x_mask &= ~(1 << irq);
+        intctl_write(iop32x_mask);
 }
 
 static void
-iop321_irq_unmask (unsigned int irq)
+iop32x_irq_unmask(unsigned int irq)
 {
-        iop321_mask |= (1 << irq);
-
-        intctl_write(iop321_mask);
+        iop32x_mask |= 1 << irq;
+        intctl_write(iop32x_mask);
 }
 
 struct irq_chip ext_chip = {
-        .name   = "IOP",
-        .ack    = iop321_irq_mask,
-        .mask   = iop321_irq_mask,
-        .unmask = iop321_irq_unmask,
+        .name   = "IOP32x",
+        .ack    = iop32x_irq_mask,
+        .mask   = iop32x_irq_mask,
+        .unmask = iop32x_irq_unmask,
 };
 
-void __init iop321_init_irq(void)
+void __init iop32x_init_irq(void)
 {
-        unsigned int i;
+        int i;
 
-        intctl_write(0);                // disable all interrupts
-        intstr_write(0);                // treat all as IRQ
-        if(machine_is_iq80321() ||
-           machine_is_iq31244())        // all interrupts are inputs to chip
+        intctl_write(0);
+        intstr_write(0);
+        if (machine_is_iq80321() ||
+            machine_is_iq31244())
                 *IOP3XX_PCIIRSR = 0x0f;
 
-        for(i = 0; i < NR_IRQS; i++)
-        {
+        for (i = 0; i < NR_IRQS; i++) {
                 set_irq_chip(i, &ext_chip);
                 set_irq_handler(i, do_level_IRQ);
                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
-
         }
 }
-
diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c
index 6b8475da3df..97a7b748826 100644
--- a/arch/arm/mach-iop33x/iq80331.c
+++ b/arch/arm/mach-iop33x/iq80331.c
@@ -61,19 +61,19 @@ iq80331_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 
         if (slot == 1 && pin == 1) {
                 /* PCI-X Slot INTA */
-                irq = IRQ_IOP331_XINT1;
+                irq = IRQ_IOP33X_XINT1;
         } else if (slot == 1 && pin == 2) {
                 /* PCI-X Slot INTB */
-                irq = IRQ_IOP331_XINT2;
+                irq = IRQ_IOP33X_XINT2;
         } else if (slot == 1 && pin == 3) {
                 /* PCI-X Slot INTC */
-                irq = IRQ_IOP331_XINT3;
+                irq = IRQ_IOP33X_XINT3;
         } else if (slot == 1 && pin == 4) {
                 /* PCI-X Slot INTD */
-                irq = IRQ_IOP331_XINT0;
+                irq = IRQ_IOP33X_XINT0;
         } else if (slot == 2) {
                 /* GigE */
-                irq = IRQ_IOP331_XINT2;
+                irq = IRQ_IOP33X_XINT2;
         } else {
                 printk(KERN_ERR "iq80331_pci_map_irq() called for unknown "
                         "device PCI:%d:%d:%d\n", dev->bus->number,
@@ -142,7 +142,7 @@ MACHINE_START(IQ80331, "Intel IQ80331")
         .io_pg_offst    = ((0xfffff000) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .map_io         = iop3xx_map_io,
-        .init_irq       = iop331_init_irq,
+        .init_irq       = iop33x_init_irq,
         .timer          = &iq80331_timer,
         .init_machine   = iq80331_init_machine,
 MACHINE_END
diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c
index 150f3fd5de0..9887bfc1c07 100644
--- a/arch/arm/mach-iop33x/iq80332.c
+++ b/arch/arm/mach-iop33x/iq80332.c
@@ -61,19 +61,19 @@ iq80332_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 
         if (slot == 4 && pin == 1) {
                 /* PCI-X Slot INTA */
-                irq = IRQ_IOP331_XINT0;
+                irq = IRQ_IOP33X_XINT0;
         } else if (slot == 4 && pin == 2) {
                 /* PCI-X Slot INTB */
-                irq = IRQ_IOP331_XINT1;
+                irq = IRQ_IOP33X_XINT1;
         } else if (slot == 4 && pin == 3) {
                 /* PCI-X Slot INTC */
-                irq = IRQ_IOP331_XINT2;
+                irq = IRQ_IOP33X_XINT2;
         } else if (slot == 4 && pin == 4) {
                 /* PCI-X Slot INTD */
-                irq = IRQ_IOP331_XINT3;
+                irq = IRQ_IOP33X_XINT3;
         } else if (slot == 6) {
                 /* GigE */
-                irq = IRQ_IOP331_XINT2;
+                irq = IRQ_IOP33X_XINT2;
         } else {
                 printk(KERN_ERR "iq80332_pci_map_irq() called for unknown "
                         "device PCI:%d:%d:%d\n", dev->bus->number,
@@ -142,7 +142,7 @@ MACHINE_START(IQ80332, "Intel IQ80332")
         .io_pg_offst    = ((0xfffff000) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .map_io         = iop3xx_map_io,
-        .init_irq       = iop331_init_irq,
+        .init_irq       = iop33x_init_irq,
         .timer          = &iq80332_timer,
         .init_machine   = iq80332_init_machine,
 MACHINE_END
diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c
index 3c720551ac1..63304b3d0d7 100644
--- a/arch/arm/mach-iop33x/irq.c
+++ b/arch/arm/mach-iop33x/irq.c
@@ -1,5 +1,5 @@
 /*
- * linux/arch/arm/mach-iop33x/irq.c
+ * arch/arm/mach-iop33x/irq.c
  *
  * Generic IOP331 IRQ handling functionality
  *
@@ -9,51 +9,44 @@
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
- *
- *
  */
+
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/list.h>
-
 #include <asm/mach/irq.h>
 #include <asm/irq.h>
 #include <asm/hardware.h>
-
 #include <asm/mach-types.h>
 
-static u32 iop331_mask0 = 0;
-static u32 iop331_mask1 = 0;
+static u32 iop33x_mask0;
+static u32 iop33x_mask1;
 
-static inline void intctl_write0(u32 val)
+static inline void intctl0_write(u32 val)
 {
-    // INTCTL0
         iop3xx_cp6_enable();
-        asm volatile("mcr p6,0,%0,c0,c0,0"::"r" (val));
+        asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
         iop3xx_cp6_disable();
 }
 
-static inline void intctl_write1(u32 val)
+static inline void intctl1_write(u32 val)
 {
-    // INTCTL1
         iop3xx_cp6_enable();
-    asm volatile("mcr p6,0,%0,c1,c0,0"::"r" (val));
+        asm volatile("mcr p6, 0, %0, c1, c0, 0" : : "r" (val));
         iop3xx_cp6_disable();
 }
 
-static inline void intstr_write0(u32 val)
+static inline void intstr0_write(u32 val)
 {
-    // INTSTR0
         iop3xx_cp6_enable();
-        asm volatile("mcr p6,0,%0,c2,c0,0"::"r" (val));
+        asm volatile("mcr p6, 0, %0, c2, c0, 0" : : "r" (val));
         iop3xx_cp6_disable();
 }
 
-static inline void intstr_write1(u32 val)
+static inline void intstr1_write(u32 val)
 {
-    // INTSTR1
         iop3xx_cp6_enable();
-        asm volatile("mcr p6,0,%0,c3,c0,0"::"r" (val));
+        asm volatile("mcr p6, 0, %0, c3, c0, 0" : : "r" (val));
         iop3xx_cp6_disable();
 }
 
@@ -72,65 +65,63 @@ static inline void intsize_write(u32 val)
 }
 
 static void
-iop331_irq_mask1 (unsigned int irq)
+iop33x_irq_mask1 (unsigned int irq)
 {
-        iop331_mask0 &= ~(1 << irq);
-        intctl_write0(iop331_mask0);
+        iop33x_mask0 &= ~(1 << irq);
+        intctl0_write(iop33x_mask0);
 }
 
 static void
-iop331_irq_mask2 (unsigned int irq)
+iop33x_irq_mask2 (unsigned int irq)
 {
-        iop331_mask1 &= ~(1 << (irq - 32));
-        intctl_write1(iop331_mask1);
+        iop33x_mask1 &= ~(1 << (irq - 32));
+        intctl1_write(iop33x_mask1);
 }
 
 static void
-iop331_irq_unmask1(unsigned int irq)
+iop33x_irq_unmask1(unsigned int irq)
 {
-        iop331_mask0 |= (1 << irq);
-        intctl_write0(iop331_mask0);
+        iop33x_mask0 |= 1 << irq;
+        intctl0_write(iop33x_mask0);
 }
 
 static void
-iop331_irq_unmask2(unsigned int irq)
+iop33x_irq_unmask2(unsigned int irq)
 {
-        iop331_mask1 |= (1 << (irq - 32));
-        intctl_write1(iop331_mask1);
+        iop33x_mask1 |= (1 << (irq - 32));
+        intctl1_write(iop33x_mask1);
 }
 
-struct irq_chip iop331_irqchip1 = {
-        .name   = "IOP-1",
-        .ack    = iop331_irq_mask1,
-        .mask   = iop331_irq_mask1,
-        .unmask = iop331_irq_unmask1,
+struct irq_chip iop33x_irqchip1 = {
+        .name   = "IOP33x-1",
+        .ack    = iop33x_irq_mask1,
+        .mask   = iop33x_irq_mask1,
+        .unmask = iop33x_irq_unmask1,
 };
 
-struct irq_chip iop331_irqchip2 = {
-        .name   = "IOP-2",
-        .ack    = iop331_irq_mask2,
-        .mask   = iop331_irq_mask2,
-        .unmask = iop331_irq_unmask2,
+struct irq_chip iop33x_irqchip2 = {
+        .name   = "IOP33x-2",
+        .ack    = iop33x_irq_mask2,
+        .mask   = iop33x_irq_mask2,
+        .unmask = iop33x_irq_unmask2,
 };
 
-void __init iop331_init_irq(void)
+void __init iop33x_init_irq(void)
 {
-        unsigned int i;
+        int i;
 
-        intctl_write0(0);               // disable all interrupts
-        intctl_write1(0);
-        intstr_write0(0);               // treat all as IRQ
-        intstr_write1(0);
+        intctl0_write(0);
+        intctl1_write(0);
+        intstr0_write(0);
+        intstr1_write(0);
         intbase_write(0);
         intsize_write(1);
-        if(machine_is_iq80331())        // all interrupts are inputs to chip
+        if (machine_is_iq80331())
                 *IOP3XX_PCIIRSR = 0x0f;
 
-        for(i = 0; i < NR_IRQS; i++)
-        {
-                set_irq_chip(i, (i < 32) ? &iop331_irqchip1 : &iop331_irqchip2);
+        for (i = 0; i < NR_IRQS; i++) {
+                set_irq_chip(i, (i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2);
                 set_irq_handler(i, do_level_IRQ);
                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
         }
 }
-
diff --git a/arch/arm/mach-iop33x/uart.c b/arch/arm/mach-iop33x/uart.c
index d221d4abaa8..ac297cd0276 100644
--- a/arch/arm/mach-iop33x/uart.c
+++ b/arch/arm/mach-iop33x/uart.c
@@ -1,5 +1,5 @@
 /*
- * linux/arch/arm/mach-iop33x/uart.c
+ * arch/arm/mach-iop33x/uart.c
  *
  * Author: Dave Jiang (dave.jiang@intel.com)
  * Copyright (C) 2004 Intel Corporation.
@@ -17,7 +17,6 @@
 #include <linux/serial.h>
 #include <linux/tty.h>
 #include <linux/serial_8250.h>
-
 #include <asm/io.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
@@ -30,14 +29,14 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#define IOP331_UART_XTAL 33334000
+#define IOP33X_UART_XTAL 33334000
 
 static struct plat_serial8250_port iop33x_uart0_data[] = {
         {
-                .membase        = (char *)IOP331_UART0_VIRT,
-                .mapbase        = IOP331_UART0_PHYS,
-                .irq            = IRQ_IOP331_UART0,
-                .uartclk        = IOP331_UART_XTAL,
+                .membase        = (char *)IOP33X_UART0_VIRT,
+                .mapbase        = IOP33X_UART0_PHYS,
+                .irq            = IRQ_IOP33X_UART0,
+                .uartclk        = IOP33X_UART_XTAL,
                 .regshift       = 2,
                 .iotype         = UPIO_MEM,
                 .flags          = UPF_SKIP_TEST,
@@ -47,13 +46,13 @@ static struct plat_serial8250_port iop33x_uart0_data[] = {
 
 static struct resource iop33x_uart0_resources[] = {
         [0] = {
-                .start  = IOP331_UART0_PHYS,
-                .end    = IOP331_UART0_PHYS + 0x3f,
+                .start  = IOP33X_UART0_PHYS,
+                .end    = IOP33X_UART0_PHYS + 0x3f,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = IRQ_IOP331_UART0,
-                .end    = IRQ_IOP331_UART0,
+                .start  = IRQ_IOP33X_UART0,
+                .end    = IRQ_IOP33X_UART0,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -71,23 +70,23 @@ struct platform_device iop33x_uart0_device = {
 
 static struct resource iop33x_uart1_resources[] = {
         [0] = {
-                .start  = IOP331_UART1_PHYS,
-                .end    = IOP331_UART1_PHYS + 0x3f,
+                .start  = IOP33X_UART1_PHYS,
+                .end    = IOP33X_UART1_PHYS + 0x3f,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = IRQ_IOP331_UART1,
-                .end    = IRQ_IOP331_UART1,
+                .start  = IRQ_IOP33X_UART1,
+                .end    = IRQ_IOP33X_UART1,
                 .flags  = IORESOURCE_IRQ,
         },
 };
 
 static struct plat_serial8250_port iop33x_uart1_data[] = {
         {
-                .membase        = (char *)IOP331_UART1_VIRT,
-                .mapbase        = IOP331_UART1_PHYS,
-                .irq            = IRQ_IOP331_UART1,
-                .uartclk        = IOP331_UART_XTAL,
+                .membase        = (char *)IOP33X_UART1_VIRT,
+                .mapbase        = IOP33X_UART1_PHYS,
+                .irq            = IRQ_IOP33X_UART1,
+                .uartclk        = IOP33X_UART_XTAL,
                 .regshift       = 2,
                 .iotype         = UPIO_MEM,
                 .flags          = UPF_SKIP_TEST,
diff --git a/arch/arm/oprofile/op_model_xscale.c b/arch/arm/oprofile/op_model_xscale.c
index 7e0cc5b15b1..6576143f255 100644
--- a/arch/arm/oprofile/op_model_xscale.c
+++ b/arch/arm/oprofile/op_model_xscale.c
@@ -37,10 +37,10 @@
 #define XSCALE_PMU_IRQ  IRQ_XS80200_PMU
 #endif
 #ifdef CONFIG_ARCH_IOP32X
-#define XSCALE_PMU_IRQ  IRQ_IOP321_CORE_PMU
+#define XSCALE_PMU_IRQ  IRQ_IOP32X_CORE_PMU
 #endif
 #ifdef CONFIG_ARCH_IOP33X
-#define XSCALE_PMU_IRQ  IRQ_IOP331_CORE_PMU
+#define XSCALE_PMU_IRQ  IRQ_IOP33X_CORE_PMU
 #endif
 #ifdef CONFIG_ARCH_PXA
 #define XSCALE_PMU_IRQ  IRQ_PMU
@@ -88,7 +88,7 @@ static struct pmu_counter results[MAX_COUNTERS];
 /*
  * There are two versions of the PMU in current XScale processors
  * with differing register layouts and number of performance counters.
- * e.g. IOP321 is xsc1 whilst IOP331 is xsc2.
+ * e.g. IOP32x is xsc1 whilst IOP33x is xsc2.
  * We detect which register layout to use in xscale_detect_pmu()
  */
 enum { PMU_XSC1, PMU_XSC2 };
diff --git a/arch/arm/plat-iop/i2c.c b/arch/arm/plat-iop/i2c.c
index 7ae149c2e98..e99909bdba7 100644
--- a/arch/arm/plat-iop/i2c.c
+++ b/arch/arm/plat-iop/i2c.c
@@ -31,12 +31,12 @@
 #include <asm/mach/arch.h>
 
 #ifdef CONFIG_ARCH_IOP32X
-#define IRQ_IOP3XX_I2C_0        IRQ_IOP321_I2C_0
-#define IRQ_IOP3XX_I2C_1        IRQ_IOP321_I2C_1
+#define IRQ_IOP3XX_I2C_0        IRQ_IOP32X_I2C_0
+#define IRQ_IOP3XX_I2C_1        IRQ_IOP32X_I2C_1
 #endif
 #ifdef CONFIG_ARCH_IOP33X
-#define IRQ_IOP3XX_I2C_0        IRQ_IOP331_I2C_0
-#define IRQ_IOP3XX_I2C_1        IRQ_IOP331_I2C_1
+#define IRQ_IOP3XX_I2C_0        IRQ_IOP33X_I2C_0
+#define IRQ_IOP3XX_I2C_1        IRQ_IOP33X_I2C_1
 #endif
 
 static struct resource iop3xx_i2c0_resources[] = {
diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c
index bed20f3669f..06282dffbdc 100644
--- a/arch/arm/plat-iop/time.c
+++ b/arch/arm/plat-iop/time.c
@@ -26,10 +26,10 @@
 #include <asm/mach/time.h>
 
 #ifdef CONFIG_ARCH_IOP32X
-#define IRQ_IOP3XX_TIMER0       IRQ_IOP321_TIMER0
+#define IRQ_IOP3XX_TIMER0       IRQ_IOP32X_TIMER0
 #else
 #ifdef CONFIG_ARCH_IOP33X
-#define IRQ_IOP3XX_TIMER0       IRQ_IOP331_TIMER0
+#define IRQ_IOP3XX_TIMER0       IRQ_IOP33X_TIMER0
 #endif
 #endif