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authorThomas Gleixner <tglx@linutronix.de>2006-07-01 17:32:14 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-07-01 17:32:14 -0400
commitc4bfa28aec58c588de55babe99f4c172ec534704 (patch)
treedc105fc1c44b26e19a82b076b37370812192bd0c /arch/arm
parent4a2581a080098ca3a0c4e416d7a282e96c75ebf8 (diff)
[ARM] 3686/1: ARM: arm/common: convert irq handling
Patch from Thomas Gleixner From: Thomas Gleixner <tglx@linutronix.de> Convert the files in arch/arm/common to use the generic irq handling functions. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/common/gic.c18
-rw-r--r--arch/arm/common/sa1111.c6
-rw-r--r--arch/arm/common/time-acorn.c1
3 files changed, 20 insertions, 5 deletions
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index c02dc8116a1..f3c1ebfdd0a 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -33,6 +33,7 @@
33 33
34static void __iomem *gic_dist_base; 34static void __iomem *gic_dist_base;
35static void __iomem *gic_cpu_base; 35static void __iomem *gic_cpu_base;
36static DEFINE_SPINLOCK(irq_controller_lock);
36 37
37/* 38/*
38 * Routines to acknowledge, disable and enable interrupts 39 * Routines to acknowledge, disable and enable interrupts
@@ -52,32 +53,45 @@ static void __iomem *gic_cpu_base;
52static void gic_ack_irq(unsigned int irq) 53static void gic_ack_irq(unsigned int irq)
53{ 54{
54 u32 mask = 1 << (irq % 32); 55 u32 mask = 1 << (irq % 32);
56
57 spin_lock(&irq_controller_lock);
55 writel(mask, gic_dist_base + GIC_DIST_ENABLE_CLEAR + (irq / 32) * 4); 58 writel(mask, gic_dist_base + GIC_DIST_ENABLE_CLEAR + (irq / 32) * 4);
56 writel(irq, gic_cpu_base + GIC_CPU_EOI); 59 writel(irq, gic_cpu_base + GIC_CPU_EOI);
60 spin_unlock(&irq_controller_lock);
57} 61}
58 62
59static void gic_mask_irq(unsigned int irq) 63static void gic_mask_irq(unsigned int irq)
60{ 64{
61 u32 mask = 1 << (irq % 32); 65 u32 mask = 1 << (irq % 32);
66
67 spin_lock(&irq_controller_lock);
62 writel(mask, gic_dist_base + GIC_DIST_ENABLE_CLEAR + (irq / 32) * 4); 68 writel(mask, gic_dist_base + GIC_DIST_ENABLE_CLEAR + (irq / 32) * 4);
69 spin_unlock(&irq_controller_lock);
63} 70}
64 71
65static void gic_unmask_irq(unsigned int irq) 72static void gic_unmask_irq(unsigned int irq)
66{ 73{
67 u32 mask = 1 << (irq % 32); 74 u32 mask = 1 << (irq % 32);
75
76 spin_lock(&irq_controller_lock);
68 writel(mask, gic_dist_base + GIC_DIST_ENABLE_SET + (irq / 32) * 4); 77 writel(mask, gic_dist_base + GIC_DIST_ENABLE_SET + (irq / 32) * 4);
78 spin_unlock(&irq_controller_lock);
69} 79}
70 80
71#ifdef CONFIG_SMP 81#ifdef CONFIG_SMP
72static void gic_set_cpu(struct irqdesc *desc, unsigned int irq, unsigned int cpu) 82static void gic_set_cpu(unsigned int irq, cpumask_t mask_val)
73{ 83{
74 void __iomem *reg = gic_dist_base + GIC_DIST_TARGET + (irq & ~3); 84 void __iomem *reg = gic_dist_base + GIC_DIST_TARGET + (irq & ~3);
75 unsigned int shift = (irq % 4) * 8; 85 unsigned int shift = (irq % 4) * 8;
86 unsigned int cpu = first_cpu(mask_val);
76 u32 val; 87 u32 val;
77 88
89 spin_lock(&irq_controller_lock);
90 irq_desc[irq].cpu = cpu;
78 val = readl(reg) & ~(0xff << shift); 91 val = readl(reg) & ~(0xff << shift);
79 val |= 1 << (cpu + shift); 92 val |= 1 << (cpu + shift);
80 writel(val, reg); 93 writel(val, reg);
94 spin_unlock(&irq_controller_lock);
81} 95}
82#endif 96#endif
83 97
@@ -86,7 +100,7 @@ static struct irqchip gic_chip = {
86 .mask = gic_mask_irq, 100 .mask = gic_mask_irq,
87 .unmask = gic_unmask_irq, 101 .unmask = gic_unmask_irq,
88#ifdef CONFIG_SMP 102#ifdef CONFIG_SMP
89 .set_cpu = gic_set_cpu, 103 .set_affinity = gic_set_cpu,
90#endif 104#endif
91}; 105};
92 106
diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c
index fe06a36a213..1cdb26a47e1 100644
--- a/arch/arm/common/sa1111.c
+++ b/arch/arm/common/sa1111.c
@@ -150,7 +150,7 @@ static void
150sa1111_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs) 150sa1111_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
151{ 151{
152 unsigned int stat0, stat1, i; 152 unsigned int stat0, stat1, i;
153 void __iomem *base = desc->data; 153 void __iomem *base = get_irq_data(irq);
154 154
155 stat0 = sa1111_readl(base + SA1111_INTSTATCLR0); 155 stat0 = sa1111_readl(base + SA1111_INTSTATCLR0);
156 stat1 = sa1111_readl(base + SA1111_INTSTATCLR1); 156 stat1 = sa1111_readl(base + SA1111_INTSTATCLR1);
@@ -168,11 +168,11 @@ sa1111_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
168 168
169 for (i = IRQ_SA1111_START; stat0; i++, stat0 >>= 1) 169 for (i = IRQ_SA1111_START; stat0; i++, stat0 >>= 1)
170 if (stat0 & 1) 170 if (stat0 & 1)
171 do_edge_IRQ(i, irq_desc + i, regs); 171 handle_edge_irq(i, irq_desc + i, regs);
172 172
173 for (i = IRQ_SA1111_START + 32; stat1; i++, stat1 >>= 1) 173 for (i = IRQ_SA1111_START + 32; stat1; i++, stat1 >>= 1)
174 if (stat1 & 1) 174 if (stat1 & 1)
175 do_edge_IRQ(i, irq_desc + i, regs); 175 handle_edge_irq(i, irq_desc + i, regs);
176 176
177 /* For level-based interrupts */ 177 /* For level-based interrupts */
178 desc->chip->unmask(irq); 178 desc->chip->unmask(irq);
diff --git a/arch/arm/common/time-acorn.c b/arch/arm/common/time-acorn.c
index 486add853fb..31b65e2231d 100644
--- a/arch/arm/common/time-acorn.c
+++ b/arch/arm/common/time-acorn.c
@@ -16,6 +16,7 @@
16#include <linux/timex.h> 16#include <linux/timex.h>
17#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/interrupt.h> 18#include <linux/interrupt.h>
19#include <linux/irq.h>
19 20
20#include <asm/hardware.h> 21#include <asm/hardware.h>
21#include <asm/io.h> 22#include <asm/io.h>