diff options
author | Eric Miao <eric.miao@marvell.com> | 2009-01-19 23:09:06 -0500 |
---|---|---|
committer | Eric Miao <eric.miao@marvell.com> | 2009-03-22 22:11:33 -0400 |
commit | 38f539a608c9a3b40b30f1892bd5f9a38f4e5ffe (patch) | |
tree | feb9c3ee23fe75151f73e8916c1afeb7c562e0dd /arch/arm | |
parent | bd5ce4332328c1fe473690a86b2e6a4157be038f (diff) |
[ARM] pxa: move common GPIO handling code into plat-pxa
1. add common GPIO handling code into [arch/arm/plat-pxa]
2. common code in <mach/gpio.h> moved into <plat/gpio.h>, new processors
should implement its own <mach/gpio.h>, provide the following required
definitions and '#include <plat/gpio.h>' in the end:
- GPIO_REGS_VIRT for mapped virtual address of the GPIO registers'
physical I/O memory
- macros of GPLR(), GPSR(), GPDR() for constant optimization for
functions gpio_{set,get}_value() (so that bit-bang code can still
have tolerable performance)
- NR_BUILTIN_GPIO for the number of onchip GPIO
- definitions of __gpio_is_inverted() and __gpio_is_occupied(), they
can be either macros or inlined functions
Signed-off-by: Eric Miao <eric.miao@marvell.com>
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/mach-pxa/Makefile | 2 | ||||
-rw-r--r-- | arch/arm/mach-pxa/include/mach/gpio.h | 32 | ||||
-rw-r--r-- | arch/arm/plat-pxa/Makefile | 1 | ||||
-rw-r--r-- | arch/arm/plat-pxa/gpio.c (renamed from arch/arm/mach-pxa/gpio.c) | 30 | ||||
-rw-r--r-- | arch/arm/plat-pxa/include/plat/gpio.h | 62 |
5 files changed, 66 insertions, 61 deletions
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index 70b46570c5c..c80e1bac494 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile | |||
@@ -4,7 +4,7 @@ | |||
4 | 4 | ||
5 | # Common support (must be linked before board specific support) | 5 | # Common support (must be linked before board specific support) |
6 | obj-y += clock.o devices.o generic.o irq.o \ | 6 | obj-y += clock.o devices.o generic.o irq.o \ |
7 | time.o gpio.o reset.o | 7 | time.o reset.o |
8 | obj-$(CONFIG_PM) += pm.o sleep.o standby.o | 8 | obj-$(CONFIG_PM) += pm.o sleep.o standby.o |
9 | 9 | ||
10 | ifeq ($(CONFIG_CPU_FREQ),y) | 10 | ifeq ($(CONFIG_CPU_FREQ),y) |
diff --git a/arch/arm/mach-pxa/include/mach/gpio.h b/arch/arm/mach-pxa/include/mach/gpio.h index c72c89a2285..b024a8b3743 100644 --- a/arch/arm/mach-pxa/include/mach/gpio.h +++ b/arch/arm/mach-pxa/include/mach/gpio.h | |||
@@ -99,40 +99,12 @@ | |||
99 | #define GAFR(x) GPIO_REG(0x54 + (((x) & 0x70) >> 2)) | 99 | #define GAFR(x) GPIO_REG(0x54 + (((x) & 0x70) >> 2)) |
100 | 100 | ||
101 | 101 | ||
102 | /* NOTE: some PXAs have fewer on-chip GPIOs (like PXA255, with 85). | ||
103 | * Those cases currently cause holes in the GPIO number space, the | ||
104 | * actual number of the last GPIO is recorded by 'pxa_last_gpio'. | ||
105 | */ | ||
106 | extern int pxa_last_gpio; | ||
107 | |||
108 | #define NR_BUILTIN_GPIO 128 | 102 | #define NR_BUILTIN_GPIO 128 |
109 | 103 | ||
110 | static inline int gpio_get_value(unsigned gpio) | ||
111 | { | ||
112 | if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO)) | ||
113 | return GPLR(gpio) & GPIO_bit(gpio); | ||
114 | else | ||
115 | return __gpio_get_value(gpio); | ||
116 | } | ||
117 | |||
118 | static inline void gpio_set_value(unsigned gpio, int value) | ||
119 | { | ||
120 | if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO)) { | ||
121 | if (value) | ||
122 | GPSR(gpio) = GPIO_bit(gpio); | ||
123 | else | ||
124 | GPCR(gpio) = GPIO_bit(gpio); | ||
125 | } else { | ||
126 | __gpio_set_value(gpio, value); | ||
127 | } | ||
128 | } | ||
129 | |||
130 | #define gpio_cansleep __gpio_cansleep | ||
131 | #define gpio_to_bank(gpio) ((gpio) >> 5) | 104 | #define gpio_to_bank(gpio) ((gpio) >> 5) |
132 | #define gpio_to_irq(gpio) IRQ_GPIO(gpio) | 105 | #define gpio_to_irq(gpio) IRQ_GPIO(gpio) |
133 | #define irq_to_gpio(irq) IRQ_TO_GPIO(irq) | 106 | #define irq_to_gpio(irq) IRQ_TO_GPIO(irq) |
134 | 107 | ||
135 | |||
136 | #ifdef CONFIG_CPU_PXA26x | 108 | #ifdef CONFIG_CPU_PXA26x |
137 | /* GPIO86/87/88/89 on PXA26x have their direction bits in GPDR2 inverted, | 109 | /* GPIO86/87/88/89 on PXA26x have their direction bits in GPDR2 inverted, |
138 | * as well as their Alternate Function value being '1' for GPIO in GAFRx. | 110 | * as well as their Alternate Function value being '1' for GPIO in GAFRx. |
@@ -165,7 +137,5 @@ static inline int __gpio_is_occupied(unsigned gpio) | |||
165 | return GPDR(gpio) & GPIO_bit(gpio); | 137 | return GPDR(gpio) & GPIO_bit(gpio); |
166 | } | 138 | } |
167 | 139 | ||
168 | typedef int (*set_wake_t)(unsigned int irq, unsigned int on); | 140 | #include <plat/gpio.h> |
169 | |||
170 | extern void pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn); | ||
171 | #endif | 141 | #endif |
diff --git a/arch/arm/plat-pxa/Makefile b/arch/arm/plat-pxa/Makefile index dcc3ceaf717..b837df44048 100644 --- a/arch/arm/plat-pxa/Makefile +++ b/arch/arm/plat-pxa/Makefile | |||
@@ -4,3 +4,4 @@ | |||
4 | 4 | ||
5 | obj-y := dma.o | 5 | obj-y := dma.o |
6 | 6 | ||
7 | obj-$(CONFIG_GENERIC_GPIO) += gpio.o | ||
diff --git a/arch/arm/mach-pxa/gpio.c b/arch/arm/plat-pxa/gpio.c index 7c2267036bf..af819bf21b6 100644 --- a/arch/arm/mach-pxa/gpio.c +++ b/arch/arm/plat-pxa/gpio.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * linux/arch/arm/mach-pxa/gpio.c | 2 | * linux/arch/arm/plat-pxa/gpio.c |
3 | * | 3 | * |
4 | * Generic PXA GPIO handling | 4 | * Generic PXA GPIO handling |
5 | * | 5 | * |
@@ -22,34 +22,6 @@ | |||
22 | 22 | ||
23 | int pxa_last_gpio; | 23 | int pxa_last_gpio; |
24 | 24 | ||
25 | /* | ||
26 | * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with | ||
27 | * one set of registers. The register offsets are organized below: | ||
28 | * | ||
29 | * GPLR GPDR GPSR GPCR GRER GFER GEDR | ||
30 | * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048 | ||
31 | * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C | ||
32 | * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050 | ||
33 | * | ||
34 | * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148 | ||
35 | * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C | ||
36 | * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150 | ||
37 | * | ||
38 | * NOTE: | ||
39 | * BANK 3 is only available on PXA27x and later processors. | ||
40 | * BANK 4 and 5 are only available on PXA935 | ||
41 | */ | ||
42 | |||
43 | #define GPIO_BANK(n) (GPIO_REGS_VIRT + BANK_OFF(n)) | ||
44 | |||
45 | #define GPLR_OFFSET 0x00 | ||
46 | #define GPDR_OFFSET 0x0C | ||
47 | #define GPSR_OFFSET 0x18 | ||
48 | #define GPCR_OFFSET 0x24 | ||
49 | #define GRER_OFFSET 0x30 | ||
50 | #define GFER_OFFSET 0x3C | ||
51 | #define GEDR_OFFSET 0x48 | ||
52 | |||
53 | struct pxa_gpio_chip { | 25 | struct pxa_gpio_chip { |
54 | struct gpio_chip chip; | 26 | struct gpio_chip chip; |
55 | void __iomem *regbase; | 27 | void __iomem *regbase; |
diff --git a/arch/arm/plat-pxa/include/plat/gpio.h b/arch/arm/plat-pxa/include/plat/gpio.h new file mode 100644 index 00000000000..44248cb926a --- /dev/null +++ b/arch/arm/plat-pxa/include/plat/gpio.h | |||
@@ -0,0 +1,62 @@ | |||
1 | #ifndef __PLAT_GPIO_H | ||
2 | #define __PLAT_GPIO_H | ||
3 | |||
4 | /* | ||
5 | * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with | ||
6 | * one set of registers. The register offsets are organized below: | ||
7 | * | ||
8 | * GPLR GPDR GPSR GPCR GRER GFER GEDR | ||
9 | * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048 | ||
10 | * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C | ||
11 | * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050 | ||
12 | * | ||
13 | * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148 | ||
14 | * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C | ||
15 | * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150 | ||
16 | * | ||
17 | * NOTE: | ||
18 | * BANK 3 is only available on PXA27x and later processors. | ||
19 | * BANK 4 and 5 are only available on PXA935 | ||
20 | */ | ||
21 | |||
22 | #define GPIO_BANK(n) (GPIO_REGS_VIRT + BANK_OFF(n)) | ||
23 | |||
24 | #define GPLR_OFFSET 0x00 | ||
25 | #define GPDR_OFFSET 0x0C | ||
26 | #define GPSR_OFFSET 0x18 | ||
27 | #define GPCR_OFFSET 0x24 | ||
28 | #define GRER_OFFSET 0x30 | ||
29 | #define GFER_OFFSET 0x3C | ||
30 | #define GEDR_OFFSET 0x48 | ||
31 | |||
32 | static inline int gpio_get_value(unsigned gpio) | ||
33 | { | ||
34 | if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO)) | ||
35 | return GPLR(gpio) & GPIO_bit(gpio); | ||
36 | else | ||
37 | return __gpio_get_value(gpio); | ||
38 | } | ||
39 | |||
40 | static inline void gpio_set_value(unsigned gpio, int value) | ||
41 | { | ||
42 | if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO)) { | ||
43 | if (value) | ||
44 | GPSR(gpio) = GPIO_bit(gpio); | ||
45 | else | ||
46 | GPCR(gpio) = GPIO_bit(gpio); | ||
47 | } else | ||
48 | __gpio_set_value(gpio, value); | ||
49 | } | ||
50 | |||
51 | #define gpio_cansleep __gpio_cansleep | ||
52 | |||
53 | /* NOTE: some PXAs have fewer on-chip GPIOs (like PXA255, with 85). | ||
54 | * Those cases currently cause holes in the GPIO number space, the | ||
55 | * actual number of the last GPIO is recorded by 'pxa_last_gpio'. | ||
56 | */ | ||
57 | extern int pxa_last_gpio; | ||
58 | |||
59 | typedef int (*set_wake_t)(unsigned int irq, unsigned int on); | ||
60 | |||
61 | extern void pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn); | ||
62 | #endif /* __PLAT_GPIO_H */ | ||