diff options
author | Sylver Bruneau <sylver.bruneau@googlemail.com> | 2008-06-26 04:47:45 -0400 |
---|---|---|
committer | Wim Van Sebroeck <wim@iguana.be> | 2008-10-10 09:14:17 -0400 |
commit | 22ac92322c83334b562024414b770e48927ae963 (patch) | |
tree | 0d0686491ec9559c3318f2ee8301c52a7555d702 /arch/arm | |
parent | b3112180fe0b8dd80053d1d83e6fc421a266e47a (diff) |
[WATCHDOG] Orion: add hardware watchdog support
This patch allows the use of the hardware watchdog in the
Marvell Orion series of ARM SoCs.
Signed-off-by: Sylver Bruneau <sylver.bruneau@googlemail.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/mach-orion5x/include/mach/orion5x.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h index 61eb74a8886..615cc1d0818 100644 --- a/arch/arm/mach-orion5x/include/mach/orion5x.h +++ b/arch/arm/mach-orion5x/include/mach/orion5x.h | |||
@@ -153,9 +153,11 @@ | |||
153 | #define CPU_CONF ORION5X_BRIDGE_REG(0x100) | 153 | #define CPU_CONF ORION5X_BRIDGE_REG(0x100) |
154 | #define CPU_CTRL ORION5X_BRIDGE_REG(0x104) | 154 | #define CPU_CTRL ORION5X_BRIDGE_REG(0x104) |
155 | #define CPU_RESET_MASK ORION5X_BRIDGE_REG(0x108) | 155 | #define CPU_RESET_MASK ORION5X_BRIDGE_REG(0x108) |
156 | #define WDT_RESET 0x0002 | ||
156 | #define CPU_SOFT_RESET ORION5X_BRIDGE_REG(0x10c) | 157 | #define CPU_SOFT_RESET ORION5X_BRIDGE_REG(0x10c) |
157 | #define POWER_MNG_CTRL_REG ORION5X_BRIDGE_REG(0x11C) | 158 | #define POWER_MNG_CTRL_REG ORION5X_BRIDGE_REG(0x11C) |
158 | #define BRIDGE_CAUSE ORION5X_BRIDGE_REG(0x110) | 159 | #define BRIDGE_CAUSE ORION5X_BRIDGE_REG(0x110) |
160 | #define WDT_INT_REQ 0x0008 | ||
159 | #define BRIDGE_MASK ORION5X_BRIDGE_REG(0x114) | 161 | #define BRIDGE_MASK ORION5X_BRIDGE_REG(0x114) |
160 | #define BRIDGE_INT_TIMER0 0x0002 | 162 | #define BRIDGE_INT_TIMER0 0x0002 |
161 | #define BRIDGE_INT_TIMER1 0x0004 | 163 | #define BRIDGE_INT_TIMER1 0x0004 |