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authorBen Dooks <ben-linux@fluff.org>2010-01-11 22:19:28 -0500
committerBen Dooks <ben-linux@fluff.org>2010-01-15 03:10:14 -0500
commit45426468148d77e8c5eaece21d2a16e063066567 (patch)
tree8745592671e68d2c3a39031800fe4621d0956669 /arch/arm/plat-s5pc1xx
parent85841bcedd6048dd37cab58a504e5317192324c6 (diff)
ARM: S5PC1XX: Move to using generic clksrc_clk for clock code
Remove the copy of the old s3c64xx struct clksrc_clk and use the new one in plat-samsung. This eliminates a bug in the set_parent() call where it failed to set the clk->parent after sucesfully updating the clock. The script that was used to automate much of the process will be supplied seperately. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/plat-s5pc1xx')
-rw-r--r--arch/arm/plat-s5pc1xx/Kconfig1
-rw-r--r--arch/arm/plat-s5pc1xx/s5pc100-clock.c388
2 files changed, 97 insertions, 292 deletions
diff --git a/arch/arm/plat-s5pc1xx/Kconfig b/arch/arm/plat-s5pc1xx/Kconfig
index b7b9e91c024..5d97b1c3cef 100644
--- a/arch/arm/plat-s5pc1xx/Kconfig
+++ b/arch/arm/plat-s5pc1xx/Kconfig
@@ -11,6 +11,7 @@ config PLAT_S5PC1XX
11 select ARM_VIC 11 select ARM_VIC
12 select NO_IOPORT 12 select NO_IOPORT
13 select ARCH_REQUIRE_GPIOLIB 13 select ARCH_REQUIRE_GPIOLIB
14 select SAMSUNG_CLKSRC
14 select S3C_GPIO_TRACK 15 select S3C_GPIO_TRACK
15 select S3C_GPIO_PULL_UPDOWN 16 select S3C_GPIO_PULL_UPDOWN
16 select S3C_GPIO_CFG_S3C24XX 17 select S3C_GPIO_CFG_S3C24XX
diff --git a/arch/arm/plat-s5pc1xx/s5pc100-clock.c b/arch/arm/plat-s5pc1xx/s5pc100-clock.c
index 16f0b907739..52c032c9d7b 100644
--- a/arch/arm/plat-s5pc1xx/s5pc100-clock.c
+++ b/arch/arm/plat-s5pc1xx/s5pc100-clock.c
@@ -29,6 +29,7 @@
29 29
30#include <plat/regs-clock.h> 30#include <plat/regs-clock.h>
31#include <plat/clock.h> 31#include <plat/clock.h>
32#include <plat/clock-clksrc.h>
32#include <plat/cpu.h> 33#include <plat/cpu.h>
33#include <plat/pll.h> 34#include <plat/pll.h>
34#include <plat/devs.h> 35#include <plat/devs.h>
@@ -51,23 +52,6 @@ static struct clk clk_ext_xtal_mux = {
51#define clk_fout_mpll clk_mpll 52#define clk_fout_mpll clk_mpll
52#define clk_vclk_54m clk_54m 53#define clk_vclk_54m clk_54m
53 54
54struct clk_sources {
55 unsigned int nr_sources;
56 struct clk **sources;
57};
58
59struct clksrc_clk {
60 struct clk clk;
61 unsigned int mask;
62 unsigned int shift;
63
64 struct clk_sources *sources;
65
66 unsigned int divider_shift;
67 void __iomem *reg_divider;
68 void __iomem *reg_source;
69};
70
71/* APLL */ 55/* APLL */
72static struct clk clk_fout_apll = { 56static struct clk clk_fout_apll = {
73 .name = "fout_apll", 57 .name = "fout_apll",
@@ -80,7 +64,7 @@ static struct clk *clk_src_apll_list[] = {
80 [1] = &clk_fout_apll, 64 [1] = &clk_fout_apll,
81}; 65};
82 66
83static struct clk_sources clk_src_apll = { 67static struct clksrc_sources clk_src_apll = {
84 .sources = clk_src_apll_list, 68 .sources = clk_src_apll_list,
85 .nr_sources = ARRAY_SIZE(clk_src_apll_list), 69 .nr_sources = ARRAY_SIZE(clk_src_apll_list),
86}; 70};
@@ -90,10 +74,8 @@ static struct clksrc_clk clk_mout_apll = {
90 .name = "mout_apll", 74 .name = "mout_apll",
91 .id = -1, 75 .id = -1,
92 }, 76 },
93 .shift = S5PC100_CLKSRC0_APLL_SHIFT,
94 .mask = S5PC100_CLKSRC0_APLL_MASK,
95 .sources = &clk_src_apll, 77 .sources = &clk_src_apll,
96 .reg_source = S5PC100_CLKSRC0, 78 .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 0, .size = 1, },
97}; 79};
98 80
99static unsigned long s5pc100_clk_dout_apll_get_rate(struct clk *clk) 81static unsigned long s5pc100_clk_dout_apll_get_rate(struct clk *clk)
@@ -240,7 +222,7 @@ static struct clk *clk_src_mpll_list[] = {
240 [1] = &clk_fout_mpll, 222 [1] = &clk_fout_mpll,
241}; 223};
242 224
243static struct clk_sources clk_src_mpll = { 225static struct clksrc_sources clk_src_mpll = {
244 .sources = clk_src_mpll_list, 226 .sources = clk_src_mpll_list,
245 .nr_sources = ARRAY_SIZE(clk_src_mpll_list), 227 .nr_sources = ARRAY_SIZE(clk_src_mpll_list),
246}; 228};
@@ -250,10 +232,8 @@ static struct clksrc_clk clk_mout_mpll = {
250 .name = "mout_mpll", 232 .name = "mout_mpll",
251 .id = -1, 233 .id = -1,
252 }, 234 },
253 .shift = S5PC100_CLKSRC0_MPLL_SHIFT,
254 .mask = S5PC100_CLKSRC0_MPLL_MASK,
255 .sources = &clk_src_mpll, 235 .sources = &clk_src_mpll,
256 .reg_source = S5PC100_CLKSRC0, 236 .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 4, .size = 1, },
257}; 237};
258 238
259static struct clk *clkset_am_list[] = { 239static struct clk *clkset_am_list[] = {
@@ -261,7 +241,7 @@ static struct clk *clkset_am_list[] = {
261 [1] = &clk_dout_apll2, 241 [1] = &clk_dout_apll2,
262}; 242};
263 243
264static struct clk_sources clk_src_am = { 244static struct clksrc_sources clk_src_am = {
265 .sources = clkset_am_list, 245 .sources = clkset_am_list,
266 .nr_sources = ARRAY_SIZE(clkset_am_list), 246 .nr_sources = ARRAY_SIZE(clkset_am_list),
267}; 247};
@@ -271,10 +251,8 @@ static struct clksrc_clk clk_mout_am = {
271 .name = "mout_am", 251 .name = "mout_am",
272 .id = -1, 252 .id = -1,
273 }, 253 },
274 .shift = S5PC100_CLKSRC0_AMMUX_SHIFT,
275 .mask = S5PC100_CLKSRC0_AMMUX_MASK,
276 .sources = &clk_src_am, 254 .sources = &clk_src_am,
277 .reg_source = S5PC100_CLKSRC0, 255 .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 16, .size = 1, },
278}; 256};
279 257
280static unsigned long s5pc100_clk_dout_d1_bus_get_rate(struct clk *clk) 258static unsigned long s5pc100_clk_dout_d1_bus_get_rate(struct clk *clk)
@@ -304,7 +282,7 @@ static struct clk *clkset_onenand_list[] = {
304 [1] = &clk_dout_d1_bus, 282 [1] = &clk_dout_d1_bus,
305}; 283};
306 284
307static struct clk_sources clk_src_onenand = { 285static struct clksrc_sources clk_src_onenand = {
308 .sources = clkset_onenand_list, 286 .sources = clkset_onenand_list,
309 .nr_sources = ARRAY_SIZE(clkset_onenand_list), 287 .nr_sources = ARRAY_SIZE(clkset_onenand_list),
310}; 288};
@@ -314,10 +292,8 @@ static struct clksrc_clk clk_mout_onenand = {
314 .name = "mout_onenand", 292 .name = "mout_onenand",
315 .id = -1, 293 .id = -1,
316 }, 294 },
317 .shift = S5PC100_CLKSRC0_ONENAND_SHIFT,
318 .mask = S5PC100_CLKSRC0_ONENAND_MASK,
319 .sources = &clk_src_onenand, 295 .sources = &clk_src_onenand,
320 .reg_source = S5PC100_CLKSRC0, 296 .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 24, .size = 1, },
321}; 297};
322 298
323static unsigned long s5pc100_clk_dout_pclkd1_get_rate(struct clk *clk) 299static unsigned long s5pc100_clk_dout_pclkd1_get_rate(struct clk *clk)
@@ -419,7 +395,7 @@ static struct clk *clk_src_epll_list[] = {
419 [1] = &clk_fout_epll, 395 [1] = &clk_fout_epll,
420}; 396};
421 397
422static struct clk_sources clk_src_epll = { 398static struct clksrc_sources clk_src_epll = {
423 .sources = clk_src_epll_list, 399 .sources = clk_src_epll_list,
424 .nr_sources = ARRAY_SIZE(clk_src_epll_list), 400 .nr_sources = ARRAY_SIZE(clk_src_epll_list),
425}; 401};
@@ -429,10 +405,8 @@ static struct clksrc_clk clk_mout_epll = {
429 .name = "mout_epll", 405 .name = "mout_epll",
430 .id = -1, 406 .id = -1,
431 }, 407 },
432 .shift = S5PC100_CLKSRC0_EPLL_SHIFT, 408 .sources = &clk_src_epll,
433 .mask = S5PC100_CLKSRC0_EPLL_MASK, 409 .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 8, .size = 1, },
434 .sources = &clk_src_epll,
435 .reg_source = S5PC100_CLKSRC0,
436}; 410};
437 411
438/* HPLL */ 412/* HPLL */
@@ -446,7 +420,7 @@ static struct clk *clk_src_hpll_list[] = {
446 [1] = &clk_fout_hpll, 420 [1] = &clk_fout_hpll,
447}; 421};
448 422
449static struct clk_sources clk_src_hpll = { 423static struct clksrc_sources clk_src_hpll = {
450 .sources = clk_src_hpll_list, 424 .sources = clk_src_hpll_list,
451 .nr_sources = ARRAY_SIZE(clk_src_hpll_list), 425 .nr_sources = ARRAY_SIZE(clk_src_hpll_list),
452}; 426};
@@ -456,10 +430,8 @@ static struct clksrc_clk clk_mout_hpll = {
456 .name = "mout_hpll", 430 .name = "mout_hpll",
457 .id = -1, 431 .id = -1,
458 }, 432 },
459 .shift = S5PC100_CLKSRC0_HPLL_SHIFT, 433 .sources = &clk_src_hpll,
460 .mask = S5PC100_CLKSRC0_HPLL_MASK, 434 .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 12, .size = 1, },
461 .sources = &clk_src_hpll,
462 .reg_source = S5PC100_CLKSRC0,
463}; 435};
464 436
465/* Peripherals */ 437/* Peripherals */
@@ -474,99 +446,6 @@ static struct clksrc_clk clk_mout_hpll = {
474 * have a common parent divisor so are not included here. 446 * have a common parent divisor so are not included here.
475 */ 447 */
476 448
477static inline struct clksrc_clk *to_clksrc(struct clk *clk)
478{
479 return container_of(clk, struct clksrc_clk, clk);
480}
481
482static unsigned long s5pc100_getrate_clksrc(struct clk *clk)
483{
484 struct clksrc_clk *sclk = to_clksrc(clk);
485 unsigned long rate = clk_get_rate(clk->parent);
486 u32 clkdiv = __raw_readl(sclk->reg_divider);
487
488 clkdiv >>= sclk->divider_shift;
489 clkdiv &= 0xf;
490 clkdiv++;
491
492 rate /= clkdiv;
493 return rate;
494}
495
496static int s5pc100_setrate_clksrc(struct clk *clk, unsigned long rate)
497{
498 struct clksrc_clk *sclk = to_clksrc(clk);
499 void __iomem *reg = sclk->reg_divider;
500 unsigned int div;
501 u32 val;
502
503 rate = clk_round_rate(clk, rate);
504 div = clk_get_rate(clk->parent) / rate;
505 if (div > 16)
506 return -EINVAL;
507
508 val = __raw_readl(reg);
509 val &= ~(0xf << sclk->divider_shift);
510 val |= (div - 1) << sclk->divider_shift;
511 __raw_writel(val, reg);
512
513 return 0;
514}
515
516static int s5pc100_setparent_clksrc(struct clk *clk, struct clk *parent)
517{
518 struct clksrc_clk *sclk = to_clksrc(clk);
519 struct clk_sources *srcs = sclk->sources;
520 u32 clksrc = __raw_readl(sclk->reg_source);
521 int src_nr = -1;
522 int ptr;
523
524 for (ptr = 0; ptr < srcs->nr_sources; ptr++)
525 if (srcs->sources[ptr] == parent) {
526 src_nr = ptr;
527 break;
528 }
529
530 if (src_nr >= 0) {
531 clksrc &= ~sclk->mask;
532 clksrc |= src_nr << sclk->shift;
533
534 __raw_writel(clksrc, sclk->reg_source);
535 return 0;
536 }
537
538 return -EINVAL;
539}
540
541static unsigned long s5pc100_roundrate_clksrc(struct clk *clk,
542 unsigned long rate)
543{
544 unsigned long parent_rate = clk_get_rate(clk->parent);
545 int div;
546
547 if (rate > parent_rate)
548 rate = parent_rate;
549 else {
550 div = rate / parent_rate;
551
552 if (div == 0)
553 div = 1;
554 if (div > 16)
555 div = 16;
556
557 rate = parent_rate / div;
558 }
559
560 return rate;
561}
562
563static struct clk_ops s5pc100_clksrc_ops = {
564 .set_parent = s5pc100_setparent_clksrc,
565 .get_rate = s5pc100_getrate_clksrc,
566 .set_rate = s5pc100_setrate_clksrc,
567 .round_rate = s5pc100_roundrate_clksrc,
568};
569
570static struct clk *clkset_spi_list[] = { 449static struct clk *clkset_spi_list[] = {
571 &clk_mout_epll.clk, 450 &clk_mout_epll.clk,
572 &clk_dout_mpll2, 451 &clk_dout_mpll2,
@@ -574,7 +453,7 @@ static struct clk *clkset_spi_list[] = {
574 &clk_mout_hpll.clk, 453 &clk_mout_hpll.clk,
575}; 454};
576 455
577static struct clk_sources clkset_spi = { 456static struct clksrc_sources clkset_spi = {
578 .sources = clkset_spi_list, 457 .sources = clkset_spi_list,
579 .nr_sources = ARRAY_SIZE(clkset_spi_list), 458 .nr_sources = ARRAY_SIZE(clkset_spi_list),
580}; 459};
@@ -587,12 +466,9 @@ static struct clksrc_clk clk_spi0 = {
587 .enable = s5pc100_sclk0_ctrl, 466 .enable = s5pc100_sclk0_ctrl,
588 467
589 }, 468 },
590 .shift = S5PC100_CLKSRC1_SPI0_SHIFT, 469 .sources = &clkset_spi,
591 .mask = S5PC100_CLKSRC1_SPI0_MASK, 470 .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 4, .size = 4, },
592 .sources = &clkset_spi, 471 .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 4, .size = 2, },
593 .divider_shift = S5PC100_CLKDIV2_SPI0_SHIFT,
594 .reg_divider = S5PC100_CLKDIV2,
595 .reg_source = S5PC100_CLKSRC1,
596}; 472};
597 473
598static struct clksrc_clk clk_spi1 = { 474static struct clksrc_clk clk_spi1 = {
@@ -601,14 +477,10 @@ static struct clksrc_clk clk_spi1 = {
601 .id = 1, 477 .id = 1,
602 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1, 478 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1,
603 .enable = s5pc100_sclk0_ctrl, 479 .enable = s5pc100_sclk0_ctrl,
604 .ops = &s5pc100_clksrc_ops,
605 }, 480 },
606 .shift = S5PC100_CLKSRC1_SPI1_SHIFT, 481 .sources = &clkset_spi,
607 .mask = S5PC100_CLKSRC1_SPI1_MASK, 482 .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 8, .size = 4, },
608 .sources = &clkset_spi, 483 .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 8, .size = 2, },
609 .divider_shift = S5PC100_CLKDIV2_SPI1_SHIFT,
610 .reg_divider = S5PC100_CLKDIV2,
611 .reg_source = S5PC100_CLKSRC1,
612}; 484};
613 485
614static struct clksrc_clk clk_spi2 = { 486static struct clksrc_clk clk_spi2 = {
@@ -617,14 +489,10 @@ static struct clksrc_clk clk_spi2 = {
617 .id = 2, 489 .id = 2,
618 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2, 490 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2,
619 .enable = s5pc100_sclk0_ctrl, 491 .enable = s5pc100_sclk0_ctrl,
620 .ops = &s5pc100_clksrc_ops,
621 }, 492 },
622 .shift = S5PC100_CLKSRC1_SPI2_SHIFT, 493 .sources = &clkset_spi,
623 .mask = S5PC100_CLKSRC1_SPI2_MASK, 494 .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 12, .size = 4, },
624 .sources = &clkset_spi, 495 .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 12, .size = 2, },
625 .divider_shift = S5PC100_CLKDIV2_SPI2_SHIFT,
626 .reg_divider = S5PC100_CLKDIV2,
627 .reg_source = S5PC100_CLKSRC1,
628}; 496};
629 497
630static struct clk *clkset_uart_list[] = { 498static struct clk *clkset_uart_list[] = {
@@ -632,7 +500,7 @@ static struct clk *clkset_uart_list[] = {
632 &clk_dout_mpll, 500 &clk_dout_mpll,
633}; 501};
634 502
635static struct clk_sources clkset_uart = { 503static struct clksrc_sources clkset_uart = {
636 .sources = clkset_uart_list, 504 .sources = clkset_uart_list,
637 .nr_sources = ARRAY_SIZE(clkset_uart_list), 505 .nr_sources = ARRAY_SIZE(clkset_uart_list),
638}; 506};
@@ -643,14 +511,10 @@ static struct clksrc_clk clk_uart_uclk1 = {
643 .id = -1, 511 .id = -1,
644 .ctrlbit = S5PC100_CLKGATE_SCLK0_UART, 512 .ctrlbit = S5PC100_CLKGATE_SCLK0_UART,
645 .enable = s5pc100_sclk0_ctrl, 513 .enable = s5pc100_sclk0_ctrl,
646 .ops = &s5pc100_clksrc_ops,
647 }, 514 },
648 .shift = S5PC100_CLKSRC1_UART_SHIFT, 515 .sources = &clkset_uart,
649 .mask = S5PC100_CLKSRC1_UART_MASK, 516 .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 0, .size = 3, },
650 .sources = &clkset_uart, 517 .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 0, .size = 1, },
651 .divider_shift = S5PC100_CLKDIV2_UART_SHIFT,
652 .reg_divider = S5PC100_CLKDIV2,
653 .reg_source = S5PC100_CLKSRC1,
654}; 518};
655 519
656static struct clk clk_iis_cd0 = { 520static struct clk clk_iis_cd0 = {
@@ -687,7 +551,7 @@ static struct clk *clkset_audio0_list[] = {
687 &clk_mout_hpll.clk, 551 &clk_mout_hpll.clk,
688}; 552};
689 553
690static struct clk_sources clkset_audio0 = { 554static struct clksrc_sources clkset_audio0 = {
691 .sources = clkset_audio0_list, 555 .sources = clkset_audio0_list,
692 .nr_sources = ARRAY_SIZE(clkset_audio0_list), 556 .nr_sources = ARRAY_SIZE(clkset_audio0_list),
693}; 557};
@@ -698,14 +562,10 @@ static struct clksrc_clk clk_audio0 = {
698 .id = 0, 562 .id = 0,
699 .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO0, 563 .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO0,
700 .enable = s5pc100_sclk1_ctrl, 564 .enable = s5pc100_sclk1_ctrl,
701 .ops = &s5pc100_clksrc_ops,
702 }, 565 },
703 .shift = S5PC100_CLKSRC3_AUDIO0_SHIFT, 566 .sources = &clkset_audio0,
704 .mask = S5PC100_CLKSRC3_AUDIO0_MASK, 567 .reg_div = { .reg = S5PC100_CLKDIV4, .shift = 12, .size = 4, },
705 .sources = &clkset_audio0, 568 .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 12, .size = 3, },
706 .divider_shift = S5PC100_CLKDIV4_AUDIO0_SHIFT,
707 .reg_divider = S5PC100_CLKDIV4,
708 .reg_source = S5PC100_CLKSRC3,
709}; 569};
710 570
711static struct clk *clkset_audio1_list[] = { 571static struct clk *clkset_audio1_list[] = {
@@ -717,7 +577,7 @@ static struct clk *clkset_audio1_list[] = {
717 &clk_mout_hpll.clk, 577 &clk_mout_hpll.clk,
718}; 578};
719 579
720static struct clk_sources clkset_audio1 = { 580static struct clksrc_sources clkset_audio1 = {
721 .sources = clkset_audio1_list, 581 .sources = clkset_audio1_list,
722 .nr_sources = ARRAY_SIZE(clkset_audio1_list), 582 .nr_sources = ARRAY_SIZE(clkset_audio1_list),
723}; 583};
@@ -728,14 +588,10 @@ static struct clksrc_clk clk_audio1 = {
728 .id = 1, 588 .id = 1,
729 .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO1, 589 .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO1,
730 .enable = s5pc100_sclk1_ctrl, 590 .enable = s5pc100_sclk1_ctrl,
731 .ops = &s5pc100_clksrc_ops,
732 }, 591 },
733 .shift = S5PC100_CLKSRC3_AUDIO1_SHIFT, 592 .sources = &clkset_audio1,
734 .mask = S5PC100_CLKSRC3_AUDIO1_MASK, 593 .reg_div = { .reg = S5PC100_CLKDIV4, .shift = 16, .size = 4, },
735 .sources = &clkset_audio1, 594 .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 16, .size = 3, },
736 .divider_shift = S5PC100_CLKDIV4_AUDIO1_SHIFT,
737 .reg_divider = S5PC100_CLKDIV4,
738 .reg_source = S5PC100_CLKSRC3,
739}; 595};
740 596
741static struct clk *clkset_audio2_list[] = { 597static struct clk *clkset_audio2_list[] = {
@@ -746,7 +602,7 @@ static struct clk *clkset_audio2_list[] = {
746 &clk_mout_hpll.clk, 602 &clk_mout_hpll.clk,
747}; 603};
748 604
749static struct clk_sources clkset_audio2 = { 605static struct clksrc_sources clkset_audio2 = {
750 .sources = clkset_audio2_list, 606 .sources = clkset_audio2_list,
751 .nr_sources = ARRAY_SIZE(clkset_audio2_list), 607 .nr_sources = ARRAY_SIZE(clkset_audio2_list),
752}; 608};
@@ -757,14 +613,10 @@ static struct clksrc_clk clk_audio2 = {
757 .id = 2, 613 .id = 2,
758 .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO2, 614 .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO2,
759 .enable = s5pc100_sclk1_ctrl, 615 .enable = s5pc100_sclk1_ctrl,
760 .ops = &s5pc100_clksrc_ops,
761 }, 616 },
762 .shift = S5PC100_CLKSRC3_AUDIO2_SHIFT, 617 .sources = &clkset_audio2,
763 .mask = S5PC100_CLKSRC3_AUDIO2_MASK, 618 .reg_div = { .reg = S5PC100_CLKDIV4, .shift = 20, .size = 4, },
764 .sources = &clkset_audio2, 619 .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 20, .size = 3, },
765 .divider_shift = S5PC100_CLKDIV4_AUDIO2_SHIFT,
766 .reg_divider = S5PC100_CLKDIV4,
767 .reg_source = S5PC100_CLKSRC3,
768}; 620};
769 621
770static struct clk *clkset_spdif_list[] = { 622static struct clk *clkset_spdif_list[] = {
@@ -773,7 +625,7 @@ static struct clk *clkset_spdif_list[] = {
773 &clk_audio2.clk, 625 &clk_audio2.clk,
774}; 626};
775 627
776static struct clk_sources clkset_spdif = { 628static struct clksrc_sources clkset_spdif = {
777 .sources = clkset_spdif_list, 629 .sources = clkset_spdif_list,
778 .nr_sources = ARRAY_SIZE(clkset_spdif_list), 630 .nr_sources = ARRAY_SIZE(clkset_spdif_list),
779}; 631};
@@ -783,10 +635,8 @@ static struct clksrc_clk clk_spdif = {
783 .name = "spdif", 635 .name = "spdif",
784 .id = -1, 636 .id = -1,
785 }, 637 },
786 .shift = S5PC100_CLKSRC3_SPDIF_SHIFT,
787 .mask = S5PC100_CLKSRC3_SPDIF_MASK,
788 .sources = &clkset_spdif, 638 .sources = &clkset_spdif,
789 .reg_source = S5PC100_CLKSRC3, 639 .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 24, .size = 2, },
790}; 640};
791 641
792static struct clk *clkset_lcd_fimc_list[] = { 642static struct clk *clkset_lcd_fimc_list[] = {
@@ -796,7 +646,7 @@ static struct clk *clkset_lcd_fimc_list[] = {
796 &clk_vclk_54m, 646 &clk_vclk_54m,
797}; 647};
798 648
799static struct clk_sources clkset_lcd_fimc = { 649static struct clksrc_sources clkset_lcd_fimc = {
800 .sources = clkset_lcd_fimc_list, 650 .sources = clkset_lcd_fimc_list,
801 .nr_sources = ARRAY_SIZE(clkset_lcd_fimc_list), 651 .nr_sources = ARRAY_SIZE(clkset_lcd_fimc_list),
802}; 652};
@@ -807,14 +657,10 @@ static struct clksrc_clk clk_lcd = {
807 .id = -1, 657 .id = -1,
808 .ctrlbit = S5PC100_CLKGATE_SCLK1_LCD, 658 .ctrlbit = S5PC100_CLKGATE_SCLK1_LCD,
809 .enable = s5pc100_sclk1_ctrl, 659 .enable = s5pc100_sclk1_ctrl,
810 .ops = &s5pc100_clksrc_ops,
811 }, 660 },
812 .shift = S5PC100_CLKSRC2_LCD_SHIFT, 661 .sources = &clkset_lcd_fimc,
813 .mask = S5PC100_CLKSRC2_LCD_MASK, 662 .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 12, .size = 4, },
814 .sources = &clkset_lcd_fimc, 663 .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 12, .size = 2, },
815 .divider_shift = S5PC100_CLKDIV3_LCD_SHIFT,
816 .reg_divider = S5PC100_CLKDIV3,
817 .reg_source = S5PC100_CLKSRC2,
818}; 664};
819 665
820static struct clksrc_clk clk_fimc0 = { 666static struct clksrc_clk clk_fimc0 = {
@@ -823,14 +669,10 @@ static struct clksrc_clk clk_fimc0 = {
823 .id = 0, 669 .id = 0,
824 .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC0, 670 .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC0,
825 .enable = s5pc100_sclk1_ctrl, 671 .enable = s5pc100_sclk1_ctrl,
826 .ops = &s5pc100_clksrc_ops,
827 }, 672 },
828 .shift = S5PC100_CLKSRC2_FIMC0_SHIFT, 673 .sources = &clkset_lcd_fimc,
829 .mask = S5PC100_CLKSRC2_FIMC0_MASK, 674 .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 16, .size = 4, },
830 .sources = &clkset_lcd_fimc, 675 .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 16, .size = 2, },
831 .divider_shift = S5PC100_CLKDIV3_FIMC0_SHIFT,
832 .reg_divider = S5PC100_CLKDIV3,
833 .reg_source = S5PC100_CLKSRC2,
834}; 676};
835 677
836static struct clksrc_clk clk_fimc1 = { 678static struct clksrc_clk clk_fimc1 = {
@@ -839,14 +681,10 @@ static struct clksrc_clk clk_fimc1 = {
839 .id = 1, 681 .id = 1,
840 .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC1, 682 .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC1,
841 .enable = s5pc100_sclk1_ctrl, 683 .enable = s5pc100_sclk1_ctrl,
842 .ops = &s5pc100_clksrc_ops,
843 }, 684 },
844 .shift = S5PC100_CLKSRC2_FIMC1_SHIFT,
845 .mask = S5PC100_CLKSRC2_FIMC1_MASK,
846 .sources = &clkset_lcd_fimc, 685 .sources = &clkset_lcd_fimc,
847 .divider_shift = S5PC100_CLKDIV3_FIMC1_SHIFT, 686 .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 20, .size = 4, },
848 .reg_divider = S5PC100_CLKDIV3, 687 .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 20, .size = 2, },
849 .reg_source = S5PC100_CLKSRC2,
850}; 688};
851 689
852static struct clksrc_clk clk_fimc2 = { 690static struct clksrc_clk clk_fimc2 = {
@@ -855,14 +693,10 @@ static struct clksrc_clk clk_fimc2 = {
855 .id = 2, 693 .id = 2,
856 .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC2, 694 .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC2,
857 .enable = s5pc100_sclk1_ctrl, 695 .enable = s5pc100_sclk1_ctrl,
858 .ops = &s5pc100_clksrc_ops,
859 }, 696 },
860 .shift = S5PC100_CLKSRC2_FIMC2_SHIFT, 697 .sources = &clkset_lcd_fimc,
861 .mask = S5PC100_CLKSRC2_FIMC2_MASK, 698 .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 24, .size = 4, },
862 .sources = &clkset_lcd_fimc, 699 .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 24, .size = 2, },
863 .divider_shift = S5PC100_CLKDIV3_FIMC2_SHIFT,
864 .reg_divider = S5PC100_CLKDIV3,
865 .reg_source = S5PC100_CLKSRC2,
866}; 700};
867 701
868static struct clk *clkset_mmc_list[] = { 702static struct clk *clkset_mmc_list[] = {
@@ -872,7 +706,7 @@ static struct clk *clkset_mmc_list[] = {
872 &clk_mout_hpll.clk , 706 &clk_mout_hpll.clk ,
873}; 707};
874 708
875static struct clk_sources clkset_mmc = { 709static struct clksrc_sources clkset_mmc = {
876 .sources = clkset_mmc_list, 710 .sources = clkset_mmc_list,
877 .nr_sources = ARRAY_SIZE(clkset_mmc_list), 711 .nr_sources = ARRAY_SIZE(clkset_mmc_list),
878}; 712};
@@ -883,14 +717,10 @@ static struct clksrc_clk clk_mmc0 = {
883 .id = 0, 717 .id = 0,
884 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0, 718 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0,
885 .enable = s5pc100_sclk0_ctrl, 719 .enable = s5pc100_sclk0_ctrl,
886 .ops = &s5pc100_clksrc_ops,
887 }, 720 },
888 .shift = S5PC100_CLKSRC2_MMC0_SHIFT, 721 .sources = &clkset_mmc,
889 .mask = S5PC100_CLKSRC2_MMC0_MASK, 722 .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 0, .size = 4, },
890 .sources = &clkset_mmc, 723 .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 0, .size = 2, },
891 .divider_shift = S5PC100_CLKDIV3_MMC0_SHIFT,
892 .reg_divider = S5PC100_CLKDIV3,
893 .reg_source = S5PC100_CLKSRC2,
894}; 724};
895 725
896static struct clksrc_clk clk_mmc1 = { 726static struct clksrc_clk clk_mmc1 = {
@@ -899,14 +729,10 @@ static struct clksrc_clk clk_mmc1 = {
899 .id = 1, 729 .id = 1,
900 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1, 730 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1,
901 .enable = s5pc100_sclk0_ctrl, 731 .enable = s5pc100_sclk0_ctrl,
902 .ops = &s5pc100_clksrc_ops,
903 }, 732 },
904 .shift = S5PC100_CLKSRC2_MMC1_SHIFT, 733 .sources = &clkset_mmc,
905 .mask = S5PC100_CLKSRC2_MMC1_MASK, 734 .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 4, .size = 4, },
906 .sources = &clkset_mmc, 735 .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 4, .size = 2, },
907 .divider_shift = S5PC100_CLKDIV3_MMC1_SHIFT,
908 .reg_divider = S5PC100_CLKDIV3,
909 .reg_source = S5PC100_CLKSRC2,
910}; 736};
911 737
912static struct clksrc_clk clk_mmc2 = { 738static struct clksrc_clk clk_mmc2 = {
@@ -915,14 +741,10 @@ static struct clksrc_clk clk_mmc2 = {
915 .id = 2, 741 .id = 2,
916 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2, 742 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2,
917 .enable = s5pc100_sclk0_ctrl, 743 .enable = s5pc100_sclk0_ctrl,
918 .ops = &s5pc100_clksrc_ops,
919 }, 744 },
920 .shift = S5PC100_CLKSRC2_MMC2_SHIFT,
921 .mask = S5PC100_CLKSRC2_MMC2_MASK,
922 .sources = &clkset_mmc, 745 .sources = &clkset_mmc,
923 .divider_shift = S5PC100_CLKDIV3_MMC2_SHIFT, 746 .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 8, .size = 4, },
924 .reg_divider = S5PC100_CLKDIV3, 747 .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 8, .size = 2, },
925 .reg_source = S5PC100_CLKSRC2,
926}; 748};
927 749
928 750
@@ -933,7 +755,7 @@ static struct clk *clkset_usbhost_list[] = {
933 &clk_48m, 755 &clk_48m,
934}; 756};
935 757
936static struct clk_sources clkset_usbhost = { 758static struct clksrc_sources clkset_usbhost = {
937 .sources = clkset_usbhost_list, 759 .sources = clkset_usbhost_list,
938 .nr_sources = ARRAY_SIZE(clkset_usbhost_list), 760 .nr_sources = ARRAY_SIZE(clkset_usbhost_list),
939}; 761};
@@ -944,14 +766,10 @@ static struct clksrc_clk clk_usbhost = {
944 .id = -1, 766 .id = -1,
945 .ctrlbit = S5PC100_CLKGATE_SCLK0_USBHOST, 767 .ctrlbit = S5PC100_CLKGATE_SCLK0_USBHOST,
946 .enable = s5pc100_sclk0_ctrl, 768 .enable = s5pc100_sclk0_ctrl,
947 .ops = &s5pc100_clksrc_ops,
948 }, 769 },
949 .shift = S5PC100_CLKSRC1_UHOST_SHIFT, 770 .sources = &clkset_usbhost,
950 .mask = S5PC100_CLKSRC1_UHOST_MASK, 771 .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 20, .size = 4, },
951 .sources = &clkset_usbhost, 772 .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 20, .size = 2, },
952 .divider_shift = S5PC100_CLKDIV2_UHOST_SHIFT,
953 .reg_divider = S5PC100_CLKDIV2,
954 .reg_source = S5PC100_CLKSRC1,
955}; 773};
956 774
957/* Clock initialisation code */ 775/* Clock initialisation code */
@@ -981,27 +799,6 @@ static struct clksrc_clk *init_parents[] = {
981 &clk_usbhost, 799 &clk_usbhost,
982}; 800};
983 801
984static void __init_or_cpufreq s5pc100_set_clksrc(struct clksrc_clk *clk)
985{
986 struct clk_sources *srcs = clk->sources;
987 u32 clksrc = __raw_readl(clk->reg_source);
988
989 clksrc &= clk->mask;
990 clksrc >>= clk->shift;
991
992 if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) {
993 printk(KERN_ERR "%s: bad source %d\n",
994 clk->clk.name, clksrc);
995 return;
996 }
997
998 clk->clk.parent = srcs->sources[clksrc];
999
1000 printk(KERN_INFO "%s: source is %s (%d), rate is %ld.%03ld MHz\n",
1001 clk->clk.name, clk->clk.parent->name, clksrc,
1002 print_mhz(clk_get_rate(&clk->clk)));
1003}
1004
1005#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) 802#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
1006 803
1007void __init_or_cpufreq s5pc100_setup_clocks(void) 804void __init_or_cpufreq s5pc100_setup_clocks(void)
@@ -1065,50 +862,54 @@ void __init_or_cpufreq s5pc100_setup_clocks(void)
1065 clk_f.rate = armclk; 862 clk_f.rate = armclk;
1066 863
1067 for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) 864 for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
1068 s5pc100_set_clksrc(init_parents[ptr]); 865 s3c_set_clksrc(init_parents[ptr], true);
1069} 866}
1070 867
1071static struct clk *clks[] __initdata = { 868static struct clk *clks[] __initdata = {
1072 &clk_ext_xtal_mux, 869 &clk_ext_xtal_mux,
1073 &clk_mout_apll.clk,
1074 &clk_dout_apll, 870 &clk_dout_apll,
1075 &clk_dout_d0_bus, 871 &clk_dout_d0_bus,
1076 &clk_dout_pclkd0, 872 &clk_dout_pclkd0,
1077 &clk_dout_apll2, 873 &clk_dout_apll2,
1078 &clk_mout_mpll.clk,
1079 &clk_mout_am.clk, 874 &clk_mout_am.clk,
1080 &clk_dout_d1_bus, 875 &clk_dout_d1_bus,
1081 &clk_mout_onenand.clk,
1082 &clk_dout_pclkd1, 876 &clk_dout_pclkd1,
1083 &clk_dout_mpll2, 877 &clk_dout_mpll2,
1084 &clk_dout_cam, 878 &clk_dout_cam,
1085 &clk_dout_mpll, 879 &clk_dout_mpll,
1086 &clk_mout_epll.clk,
1087 &clk_fout_epll, 880 &clk_fout_epll,
1088 &clk_iis_cd0, 881 &clk_iis_cd0,
1089 &clk_iis_cd1, 882 &clk_iis_cd1,
1090 &clk_iis_cd2, 883 &clk_iis_cd2,
1091 &clk_pcm_cd0, 884 &clk_pcm_cd0,
1092 &clk_pcm_cd1, 885 &clk_pcm_cd1,
1093 &clk_spi0.clk,
1094 &clk_spi1.clk,
1095 &clk_spi2.clk,
1096 &clk_uart_uclk1.clk,
1097 &clk_audio0.clk,
1098 &clk_audio1.clk,
1099 &clk_audio2.clk,
1100 &clk_spdif.clk,
1101 &clk_lcd.clk,
1102 &clk_fimc0.clk,
1103 &clk_fimc1.clk,
1104 &clk_fimc2.clk,
1105 &clk_mmc0.clk,
1106 &clk_mmc1.clk,
1107 &clk_mmc2.clk,
1108 &clk_usbhost.clk,
1109 &clk_arm, 886 &clk_arm,
1110}; 887};
1111 888
889/* simplest change - will aggregate clocks later */
890static struct clksrc_clk *clks_src[] = {
891 &clk_mout_apll,
892 &clk_mout_mpll,
893 &clk_mout_onenand,
894 &clk_mout_epll,
895 &clk_spi0,
896 &clk_spi1,
897 &clk_spi2,
898 &clk_uart_uclk1,
899 &clk_audio0,
900 &clk_audio1,
901 &clk_audio2,
902 &clk_spdif,
903 &clk_lcd,
904 &clk_fimc0,
905 &clk_fimc1,
906 &clk_fimc2,
907 &clk_mmc0,
908 &clk_mmc1,
909 &clk_mmc2,
910 &clk_usbhost,
911};
912
1112void __init s5pc100_register_clocks(void) 913void __init s5pc100_register_clocks(void)
1113{ 914{
1114 struct clk *clkp; 915 struct clk *clkp;
@@ -1123,4 +924,7 @@ void __init s5pc100_register_clocks(void)
1123 clkp->name, ret); 924 clkp->name, ret);
1124 } 925 }
1125 } 926 }
927
928 for (ptr = 0; ptr < ARRAY_SIZE(clks_src); ptr++)
929 s3c_register_clksrc(clks_src[ptr], 1);
1126} 930}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-08 10:15:49 -0500