[ARM] S3C64XX: Clock support for S3C6400/S3C6410

Add the PLL clock initialisation and clock registration
and include the clocks sourced via CLKDIVx for most of
the on-chip peripherals.

Signed-off-by: Ben Dooks <ben-linux@fluff.org>

2 files changed, 96 insertions, 1 deletions

diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
index 462558ec1af..78938a5e1d2 100644
--- a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
+++ b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
@@ -33,6 +33,59 @@
 #define S3C_PCLK_GATE           S3C_CLKREG(0x34)
 #define S3C_SCLK_GATE           S3C_CLKREG(0x38)
 
+/* CLKDIV0 */
+#define S3C6400_CLKDIV0_MFC_MASK        (0xf << 28)
+#define S3C6400_CLKDIV0_MFC_SHIFT       (28)
+#define S3C6400_CLKDIV0_JPEG_MASK       (0xf << 24)
+#define S3C6400_CLKDIV0_JPEG_SHIFT      (24)
+#define S3C6400_CLKDIV0_CAM_MASK        (0xf << 20)
+#define S3C6400_CLKDIV0_CAM_SHIFT       (20)
+#define S3C6400_CLKDIV0_SECURITY_MASK   (0x3 << 18)
+#define S3C6400_CLKDIV0_SECURITY_SHIFT  (18)
+#define S3C6400_CLKDIV0_PCLK_MASK       (0xf << 12)
+#define S3C6400_CLKDIV0_PCLK_SHIFT      (12)
+#define S3C6400_CLKDIV0_HCLK2_MASK      (0x7 << 9)
+#define S3C6400_CLKDIV0_HCLK2_SHIFT     (9)
+#define S3C6400_CLKDIV0_HCLK_MASK       (0x1 << 8)
+#define S3C6400_CLKDIV0_HCLK_SHIFT      (8)
+#define S3C6400_CLKDIV0_MPLL_MASK       (0x1 << 4)
+#define S3C6400_CLKDIV0_MPLL_SHIFT      (4)
+#define S3C6400_CLKDIV0_ARM_MASK        (0x3 << 0)
+#define S3C6410_CLKDIV0_ARM_MASK        (0x7 << 0)
+#define S3C6400_CLKDIV0_ARM_SHIFT       (0)
+
+/* CLKDIV1 */
+#define S3C6410_CLKDIV1_FIMC_MASK       (0xf << 24)
+#define S3C6410_CLKDIV1_FIMC_SHIFT      (24)
+#define S3C6400_CLKDIV1_UHOST_MASK      (0xf << 20)
+#define S3C6400_CLKDIV1_UHOST_SHIFT     (20)
+#define S3C6400_CLKDIV1_SCALER_MASK     (0xf << 16)
+#define S3C6400_CLKDIV1_SCALER_SHIFT    (16)
+#define S3C6400_CLKDIV1_LCD_MASK        (0xf << 12)
+#define S3C6400_CLKDIV1_LCD_SHIFT       (12)
+#define S3C6400_CLKDIV1_MMC2_MASK       (0xf << 8)
+#define S3C6400_CLKDIV1_MMC2_SHIFT      (8)
+#define S3C6400_CLKDIV1_MMC1_MASK       (0xf << 4)
+#define S3C6400_CLKDIV1_MMC1_SHIFT      (4)
+#define S3C6400_CLKDIV1_MMC0_MASK       (0xf << 0)
+#define S3C6400_CLKDIV1_MMC0_SHIFT      (0)
+
+/* CLKDIV2 */
+#define S3C6410_CLKDIV2_AUDIO2_MASK     (0xf << 24)
+#define S3C6410_CLKDIV2_AUDIO2_SHIFT    (24)
+#define S3C6400_CLKDIV2_IRDA_MASK       (0xf << 20)
+#define S3C6400_CLKDIV2_IRDA_SHIFT      (20)
+#define S3C6400_CLKDIV2_UART_MASK       (0xf << 16)
+#define S3C6400_CLKDIV2_UART_SHIFT      (16)
+#define S3C6400_CLKDIV2_AUDIO1_MASK     (0xf << 12)
+#define S3C6400_CLKDIV2_AUDIO1_SHIFT    (12)
+#define S3C6400_CLKDIV2_AUDIO0_MASK     (0xf << 8)
+#define S3C6400_CLKDIV2_AUDIO0_SHIFT    (8)
+#define S3C6400_CLKDIV2_SPI1_MASK       (0xf << 4)
+#define S3C6400_CLKDIV2_SPI1_SHIFT      (4)
+#define S3C6400_CLKDIV2_SPI0_MASK       (0xf << 0)
+#define S3C6400_CLKDIV2_SPI0_SHIFT      (0)
+
 /* HCLK GATE Registers */
 #define S3C_CLKCON_HCLK_BUS     (1<<30)
 #define S3C_CLKCON_HCLK_SECUR   (1<<29)
@@ -128,4 +181,44 @@
 #define S3C_CLKCON_SCLK_CAM             (1<<2)
 #define S3C_CLKCON_SCLK_JPEG            (1<<1)
 
-#endif /* __PLAT_REGS_CLOCK_H */
+/* CLKSRC */
+
+#define S3C6400_CLKSRC_APLL_MOUT        (1 << 0)
+#define S3C6400_CLKSRC_MPLL_MOUT        (1 << 1)
+#define S3C6400_CLKSRC_EPLL_MOUT        (1 << 2)
+#define S3C6400_CLKSRC_APLL_MOUT_SHIFT  (0)
+#define S3C6400_CLKSRC_MPLL_MOUT_SHIFT  (1)
+#define S3C6400_CLKSRC_EPLL_MOUT_SHIFT  (2)
+#define S3C6400_CLKSRC_MFC              (1 << 4)
+
+#define S3C6410_CLKSRC_TV27_MASK        (0x1 << 31)
+#define S3C6410_CLKSRC_TV27_SHIFT       (31)
+#define S3C6410_CLKSRC_DAC27_MASK       (0x1 << 30)
+#define S3C6410_CLKSRC_DAC27_SHIFT      (30)
+#define S3C6400_CLKSRC_SCALER_MASK      (0x3 << 28)
+#define S3C6400_CLKSRC_SCALER_SHIFT     (28)
+#define S3C6400_CLKSRC_LCD_MASK         (0x3 << 26)
+#define S3C6400_CLKSRC_LCD_SHIFT        (26)
+#define S3C6400_CLKSRC_IRDA_MASK        (0x3 << 24)
+#define S3C6400_CLKSRC_IRDA_SHIFT       (24)
+#define S3C6400_CLKSRC_MMC2_MASK        (0x3 << 22)
+#define S3C6400_CLKSRC_MMC2_SHIFT       (22)
+#define S3C6400_CLKSRC_MMC1_MASK        (0x3 << 20)
+#define S3C6400_CLKSRC_MMC1_SHIFT       (20)
+#define S3C6400_CLKSRC_MMC0_MASK        (0xf << 1)
+#define S3C6400_CLKSRC_MMC0_SHIFT       (1)
+#define S3C6400_CLKSRC_SPI1_MASK        (0x3 << 16)
+#define S3C6400_CLKSRC_SPI1_SHIFT       (16)
+#define S3C6400_CLKSRC_SPI0_MASK        (0x3 << 14)
+#define S3C6400_CLKSRC_SPI0_SHIFT       (14)
+#define S3C6400_CLKSRC_UART_MASK        (0x1 << 13)
+#define S3C6400_CLKSRC_UART_SHIFT       (13)
+#define S3C6400_CLKSRC_AUDIO1_MASK      (0x7 << 10)
+#define S3C6400_CLKSRC_AUDIO1_SHIFT     (10)
+#define S3C6400_CLKSRC_AUDIO0_MASK      (0x7 << 7)
+#define S3C6400_CLKSRC_AUDIO0_SHIFT     (7)
+#define S3C6400_CLKSRC_UHOST_MASK       (0x3 << 5)
+#define S3C6400_CLKSRC_UHOST_SHIFT      (5)
+
+
+#endif /* _PLAT_REGS_CLOCK_H */
diff --git a/arch/arm/plat-s3c64xx/include/plat/s3c6400.h b/arch/arm/plat-s3c64xx/include/plat/s3c6400.h
index 142bb3d18cd..571eaa2e54f 100644
--- a/arch/arm/plat-s3c64xx/include/plat/s3c6400.h
+++ b/arch/arm/plat-s3c64xx/include/plat/s3c6400.h
@@ -15,6 +15,8 @@
 /* Common init code for S3C6400 related SoCs */
 
 extern void s3c6400_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+extern void s3c6400_register_clocks(void);
+extern void s3c6400_setup_clocks(void);
 
 #ifdef CONFIG_CPU_S3C6400