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authorAmit Kucheria <amit.kucheria@canonical.com>2010-02-04 15:09:40 -0500
committerAmit Kucheria <amit.kucheria@canonical.com>2010-02-09 11:32:10 -0500
commit438caa3f6c91ba21c539a8547c4075b619dc6500 (patch)
tree6590ae5c3b5140babd9642572a042695a2c49c82 /arch/arm/plat-mxc
parent0f3332c4fabb2227b1bc15dc7542017d08f10a09 (diff)
mxc: changes to common plat-mxc code to add support for i.MX5
Prepare for i.MX5 SoC code by adding the relevant macros to common plat-mxc code. Signed-off-by: Amit Kucheria <amit.kucheria@canonical.com>
Diffstat (limited to 'arch/arm/plat-mxc')
-rw-r--r--arch/arm/plat-mxc/include/mach/debug-macro.S9
-rw-r--r--arch/arm/plat-mxc/include/mach/hardware.h4
-rw-r--r--arch/arm/plat-mxc/include/mach/irqs.h3
-rw-r--r--arch/arm/plat-mxc/include/mach/memory.h3
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc.h13
-rw-r--r--arch/arm/plat-mxc/include/mach/timex.h2
6 files changed, 34 insertions, 0 deletions
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
index 916d4fcb2ef..133d66bfb53 100644
--- a/arch/arm/plat-mxc/include/mach/debug-macro.S
+++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
@@ -45,6 +45,15 @@
45#define UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) 45#define UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
46#endif 46#endif
47 47
48#ifdef CONFIG_ARCH_MX5
49#ifdef UART_PADDR
50#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
51#endif
52#include <mach/mx51.h>
53#define UART_PADDR MX51_UART1_BASE_ADDR
54#define UART_VADDR MX51_AIPS1_IO_ADDRESS(MX51_UART1_BASE_ADDR)
55#endif
56
48#ifdef CONFIG_ARCH_MXC91231 57#ifdef CONFIG_ARCH_MXC91231
49#ifdef UART_PADDR 58#ifdef UART_PADDR
50#error "CONFIG_DEBUG_LL is incompatible with multiple archs" 59#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index db14c56930a..ebadf4ac43f 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -27,6 +27,10 @@
27 (((unsigned long)((addr) - (module ## _BASE_ADDR)) < module ## _SIZE) ?\ 27 (((unsigned long)((addr) - (module ## _BASE_ADDR)) < module ## _SIZE) ?\
28 (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)) 28 (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0))
29 29
30#ifdef CONFIG_ARCH_MX5
31#include <mach/mx51.h>
32#endif
33
30#ifdef CONFIG_ARCH_MX3 34#ifdef CONFIG_ARCH_MX3
31#include <mach/mx3x.h> 35#include <mach/mx3x.h>
32#include <mach/mx31.h> 36#include <mach/mx31.h>
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
index 38f150162e4..a3ad643de5a 100644
--- a/arch/arm/plat-mxc/include/mach/irqs.h
+++ b/arch/arm/plat-mxc/include/mach/irqs.h
@@ -30,6 +30,8 @@
30#define MXC_GPIO_IRQS (32 * 3) 30#define MXC_GPIO_IRQS (32 * 3)
31#elif defined CONFIG_ARCH_MX25 31#elif defined CONFIG_ARCH_MX25
32#define MXC_GPIO_IRQS (32 * 4) 32#define MXC_GPIO_IRQS (32 * 4)
33#elif defined CONFIG_ARCH_MX5
34#define MXC_GPIO_IRQS (32 * 4)
33#elif defined CONFIG_ARCH_MXC91231 35#elif defined CONFIG_ARCH_MXC91231
34#define MXC_GPIO_IRQS (32 * 4) 36#define MXC_GPIO_IRQS (32 * 4)
35#endif 37#endif
@@ -55,6 +57,7 @@
55#else 57#else
56#define MX3_IPU_IRQS 0 58#define MX3_IPU_IRQS 0
57#endif 59#endif
60/* REVISIT: Add IPU irqs on IMX51 */
58 61
59#define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS) 62#define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS)
60 63
diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
index 002eb91ab23..7cae9cb6208 100644
--- a/arch/arm/plat-mxc/include/mach/memory.h
+++ b/arch/arm/plat-mxc/include/mach/memory.h
@@ -16,6 +16,7 @@
16#define MX25_PHYS_OFFSET UL(0x80000000) 16#define MX25_PHYS_OFFSET UL(0x80000000)
17#define MX27_PHYS_OFFSET UL(0xa0000000) 17#define MX27_PHYS_OFFSET UL(0xa0000000)
18#define MX3x_PHYS_OFFSET UL(0x80000000) 18#define MX3x_PHYS_OFFSET UL(0x80000000)
19#define MX51_PHYS_OFFSET UL(0x90000000)
19#define MXC91231_PHYS_OFFSET UL(0x90000000) 20#define MXC91231_PHYS_OFFSET UL(0x90000000)
20 21
21#if !defined(CONFIG_RUNTIME_PHYS_OFFSET) 22#if !defined(CONFIG_RUNTIME_PHYS_OFFSET)
@@ -31,6 +32,8 @@
31# define PHYS_OFFSET MX3x_PHYS_OFFSET 32# define PHYS_OFFSET MX3x_PHYS_OFFSET
32# elif defined CONFIG_ARCH_MXC91231 33# elif defined CONFIG_ARCH_MXC91231
33# define PHYS_OFFSET MXC91231_PHYS_OFFSET 34# define PHYS_OFFSET MXC91231_PHYS_OFFSET
35# elif defined CONFIG_ARCH_MX5
36# define PHYS_OFFSET MX51_PHYS_OFFSET
34# endif 37# endif
35#endif 38#endif
36 39
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index 800ae2a33b1..a790bf21297 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -30,6 +30,7 @@
30#define MXC_CPU_MX27 27 30#define MXC_CPU_MX27 27
31#define MXC_CPU_MX31 31 31#define MXC_CPU_MX31 31
32#define MXC_CPU_MX35 35 32#define MXC_CPU_MX35 35
33#define MXC_CPU_MX51 51
33#define MXC_CPU_MXC91231 91231 34#define MXC_CPU_MXC91231 91231
34 35
35#ifndef __ASSEMBLY__ 36#ifndef __ASSEMBLY__
@@ -108,6 +109,18 @@ extern unsigned int __mxc_cpu_type;
108# define cpu_is_mx35() (0) 109# define cpu_is_mx35() (0)
109#endif 110#endif
110 111
112#ifdef CONFIG_ARCH_MX5
113# ifdef mxc_cpu_type
114# undef mxc_cpu_type
115# define mxc_cpu_type __mxc_cpu_type
116# else
117# define mxc_cpu_type MXC_CPU_MX51
118# endif
119# define cpu_is_mx51() (mxc_cpu_type == MXC_CPU_MX51)
120#else
121# define cpu_is_mx51() (0)
122#endif
123
111#ifdef CONFIG_ARCH_MXC91231 124#ifdef CONFIG_ARCH_MXC91231
112# ifdef mxc_cpu_type 125# ifdef mxc_cpu_type
113# undef mxc_cpu_type 126# undef mxc_cpu_type
diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h
index 527a6c24788..024416ed11c 100644
--- a/arch/arm/plat-mxc/include/mach/timex.h
+++ b/arch/arm/plat-mxc/include/mach/timex.h
@@ -28,6 +28,8 @@
28#define CLOCK_TICK_RATE 16625000 28#define CLOCK_TICK_RATE 16625000
29#elif defined CONFIG_ARCH_MX25 29#elif defined CONFIG_ARCH_MX25
30#define CLOCK_TICK_RATE 16000000 30#define CLOCK_TICK_RATE 16000000
31#elif defined CONFIG_ARCH_MX5
32#define CLOCK_TICK_RATE 8000000
31#elif defined CONFIG_ARCH_MXC91231 33#elif defined CONFIG_ARCH_MXC91231
32#define CLOCK_TICK_RATE 13000000 34#define CLOCK_TICK_RATE 13000000
33#endif 35#endif