Merge master.kernel.org:/home/rmk/linux-2.6-arm

* master.kernel.org:/home/rmk/linux-2.6-arm:
  [ARM] 4634/1: DaVinci GPIO header build fix
  [ARM] 4636/1: pxa: add default configuration for zylonite
  [ARM] 4635/1: pxa: Change Eric Miao's email address to eric.miao@marvell.com
  [ARM] Fix assignment instead of condition in arm/mach-omap2/clock.c
  [ARM] nommu: fix breakage caused by f9720205d1f847cb59e197e851b5276425363f6b
  [ARM] pxa: shut up CLOCK_EVT_MODE_RESUME warning
  [ARM] Fix FIQ issue with ARM926
  [ARM] Fix pxamci regression
  [ARM] Fix netx_defconfig regression
  [ARM] Fix ateb9200_defconfig build regression
  [ARM] Fix an rpc_defconfig regression
  [ARM] Fix omap_h2_1610_defconfig regressions
  [ARM] 4632/1: Fix a typo in include/asm-arm/plat-s3c/regs-nand.h

1 files changed, 4 insertions, 0 deletions

diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 5b80b6bdd0c..194ef48968e 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -105,9 +105,13 @@ ENTRY(cpu_arm926_do_idle)
         mrc     p15, 0, r1, c1, c0, 0           @ Read control register
         mcr     p15, 0, r0, c7, c10, 4          @ Drain write buffer
         bic     r2, r1, #1 << 12
+        mrs     r3, cpsr                        @ Disable FIQs while Icache
+        orr     ip, r3, #PSR_F_BIT              @ is disabled
+        msr     cpsr_c, ip
         mcr     p15, 0, r2, c1, c0, 0           @ Disable I cache
         mcr     p15, 0, r0, c7, c0, 4           @ Wait for interrupt
         mcr     p15, 0, r1, c1, c0, 0           @ Restore ICache enable
+        msr     cpsr_c, r3                      @ Restore FIQ state
         mov     pc, lr
 
 /*