[ARM] nommu: provide a way for correct control register value selection

Most MMU-based CPUs have a restriction on the setting of the data cache
enable and mmu enable bits in the control register, whereby if the data
cache is enabled, the MMU must also be enabled.  Enabling the data
cache without the MMU is an invalid combination.

However, there are CPUs where the data cache can be enabled without the
MMU.

In order to allow these CPUs to take advantage of that, provide a
method whereby each proc-*.S file defines the control regsiter value
for use with nommu (with the MMU disabled.)  Later on, when we add
support for enabling the MMU on these devices, we can adjust the
"crval" macro to also enable the data cache for nommu.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 5 insertions, 9 deletions

diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index aaa9f985b24..07f2a888c93 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -455,11 +455,10 @@ __arm925_setup:
         mcr     p15, 7, r0, c15, c0, 0
 #endif
 
+        adr     r5, {r5, r6}
         mrc     p15, 0, r0, c1, c0              @ get control register v4
-        ldr     r5, arm925_cr1_clear
         bic     r0, r0, r5
-        ldr     r5, arm925_cr1_set
-        orr     r0, r0, r5
+        orr     r0, r0, r6
 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
         orr     r0, r0, #0x4000                 @ .1.. .... .... ....
 #endif
@@ -472,12 +471,9 @@ __arm925_setup:
          * .011 0001 ..11 1101
          * 
          */
-        .type   arm925_cr1_clear, #object
-        .type   arm925_cr1_set, #object
-arm925_cr1_clear:
-        .word   0x7f3f
-arm925_cr1_set:
-        .word   0x313d
+        .type   arm925_crval, #object
+arm925_crval:
+        crval   clear=0x00007f3f, mmuset=0x0000313d, ucset=0x00001130
 
         __INITDATA