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authorRabin Vincent <rabin.vincent@stericsson.com>2010-12-08 00:37:59 -0500
committerLinus Walleij <linus.walleij@stericsson.com>2011-01-10 12:34:53 -0500
commitabf12d719a2c9e45f7f90c02a3a25107206ed57a (patch)
tree0aa9d9ecc7188b748eeda954b609dd74a8f5d24f /arch/arm/mach-ux500/cpu-db8500.c
parent5dc55e0a39434ec8bec7978aef2dc00c91a530ba (diff)
ux500: dynamic SOC detection
Dynamically detect the DBx500 SOC an revision based on the ASIC ID. Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
Diffstat (limited to 'arch/arm/mach-ux500/cpu-db8500.c')
-rw-r--r--arch/arm/mach-ux500/cpu-db8500.c91
1 files changed, 10 insertions, 81 deletions
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 1b2b81c0f27..1748fbc5853 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -29,9 +29,12 @@ static struct platform_device *platform_devs[] __initdata = {
29}; 29};
30 30
31/* minimum static i/o mapping required to boot U8500 platforms */ 31/* minimum static i/o mapping required to boot U8500 platforms */
32static struct map_desc u8500_io_desc[] __initdata = { 32static struct map_desc u8500_uart_io_desc[] __initdata = {
33 __IO_DEV_DESC(U8500_UART0_BASE, SZ_4K), 33 __IO_DEV_DESC(U8500_UART0_BASE, SZ_4K),
34 __IO_DEV_DESC(U8500_UART2_BASE, SZ_4K), 34 __IO_DEV_DESC(U8500_UART2_BASE, SZ_4K),
35};
36
37static struct map_desc u8500_io_desc[] __initdata = {
35 __IO_DEV_DESC(U8500_GIC_CPU_BASE, SZ_4K), 38 __IO_DEV_DESC(U8500_GIC_CPU_BASE, SZ_4K),
36 __IO_DEV_DESC(U8500_GIC_DIST_BASE, SZ_4K), 39 __IO_DEV_DESC(U8500_GIC_DIST_BASE, SZ_4K),
37 __IO_DEV_DESC(U8500_L2CC_BASE, SZ_4K), 40 __IO_DEV_DESC(U8500_L2CC_BASE, SZ_4K),
@@ -51,7 +54,6 @@ static struct map_desc u8500_io_desc[] __initdata = {
51 __IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K), 54 __IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K),
52 __IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K), 55 __IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K),
53 __IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K), 56 __IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K),
54 __MEM_DEV_DESC(U8500_BOOT_ROM_BASE, SZ_1M),
55}; 57};
56 58
57static struct map_desc u8500_ed_io_desc[] __initdata = { 59static struct map_desc u8500_ed_io_desc[] __initdata = {
@@ -68,71 +70,15 @@ static struct map_desc u8500_v2_io_desc[] __initdata = {
68 __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K), 70 __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K),
69}; 71};
70 72
71/* 73void __init u8500_map_io(void)
72 * Functions to differentiate between later ASICs
73 * We look into the end of the ROM to locate the hardcoded ASIC ID.
74 * This is only needed to differentiate between minor revisions and
75 * process variants of an ASIC, the major revisions are encoded in
76 * the cpuid.
77 */
78#define U8500_ASIC_ID_LOC_ED_V1 (U8500_BOOT_ROM_BASE + 0x1FFF4)
79#define U8500_ASIC_ID_LOC_V2 (U8500_BOOT_ROM_BASE + 0x1DBF4)
80#define U8500_ASIC_REV_ED 0x01
81#define U8500_ASIC_REV_V10 0xA0
82#define U8500_ASIC_REV_V11 0xA1
83#define U8500_ASIC_REV_V20 0xB0
84
85/**
86 * struct db8500_asic_id - fields of the ASIC ID
87 * @process: the manufacturing process, 0x40 is 40 nm
88 * 0x00 is "standard"
89 * @partnumber: hithereto 0x8500 for DB8500
90 * @revision: version code in the series
91 * This field definion is not formally defined but makes
92 * sense.
93 */
94struct db8500_asic_id {
95 u8 process;
96 u16 partnumber;
97 u8 revision;
98};
99
100/* This isn't going to change at runtime */
101static struct db8500_asic_id db8500_id;
102
103static void __init get_db8500_asic_id(void)
104{
105 u32 asicid;
106
107 if (cpu_is_u8500v1() || cpu_is_u8500ed())
108 asicid = readl(__io_address(U8500_ASIC_ID_LOC_ED_V1));
109 else if (cpu_is_u8500v2())
110 asicid = readl(__io_address(U8500_ASIC_ID_LOC_V2));
111 else
112 BUG();
113
114 db8500_id.process = (asicid >> 24);
115 db8500_id.partnumber = (asicid >> 16) & 0xFFFFU;
116 db8500_id.revision = asicid & 0xFFU;
117}
118
119bool cpu_is_u8500v10(void)
120{
121 return (db8500_id.revision == U8500_ASIC_REV_V10);
122}
123
124bool cpu_is_u8500v11(void)
125{ 74{
126 return (db8500_id.revision == U8500_ASIC_REV_V11); 75 /*
127} 76 * Map the UARTs early so that the DEBUG_LL stuff continues to work.
77 */
78 iotable_init(u8500_uart_io_desc, ARRAY_SIZE(u8500_uart_io_desc));
128 79
129bool cpu_is_u8500v20(void) 80 ux500_map_io();
130{
131 return (db8500_id.revision == U8500_ASIC_REV_V20);
132}
133 81
134void __init u8500_map_io(void)
135{
136 iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc)); 82 iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc));
137 83
138 if (cpu_is_u8500ed()) 84 if (cpu_is_u8500ed())
@@ -141,9 +87,6 @@ void __init u8500_map_io(void)
141 iotable_init(u8500_v1_io_desc, ARRAY_SIZE(u8500_v1_io_desc)); 87 iotable_init(u8500_v1_io_desc, ARRAY_SIZE(u8500_v1_io_desc));
142 else if (cpu_is_u8500v2()) 88 else if (cpu_is_u8500v2())
143 iotable_init(u8500_v2_io_desc, ARRAY_SIZE(u8500_v2_io_desc)); 89 iotable_init(u8500_v2_io_desc, ARRAY_SIZE(u8500_v2_io_desc));
144
145 /* Read out the ASIC ID as early as we can */
146 get_db8500_asic_id();
147} 90}
148 91
149static resource_size_t __initdata db8500_gpio_base[] = { 92static resource_size_t __initdata db8500_gpio_base[] = {
@@ -173,20 +116,6 @@ static void __init db8500_add_gpios(void)
173 */ 116 */
174void __init u8500_init_devices(void) 117void __init u8500_init_devices(void)
175{ 118{
176 /* Display some ASIC boilerplate */
177 pr_info("DB8500: process: %02x, revision ID: 0x%02x\n",
178 db8500_id.process, db8500_id.revision);
179 if (cpu_is_u8500ed())
180 pr_info("DB8500: Early Drop (ED)\n");
181 else if (cpu_is_u8500v10())
182 pr_info("DB8500: version 1.0\n");
183 else if (cpu_is_u8500v11())
184 pr_info("DB8500: version 1.1\n");
185 else if (cpu_is_u8500v20())
186 pr_info("DB8500: version 2.0\n");
187 else
188 pr_warning("ASIC: UNKNOWN SILICON VERSION!\n");
189
190 if (cpu_is_u8500ed()) 119 if (cpu_is_u8500ed())
191 dma40_u8500ed_fixup(); 120 dma40_u8500ed_fixup();
192 121