diff options
| author | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2010-03-22 13:23:46 -0400 |
|---|---|---|
| committer | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2010-03-22 13:23:46 -0400 |
| commit | 74511020dde10252f8b8e648690d99dba721de14 (patch) | |
| tree | 04fc22bc7dd5d5b8d9294b2e57985b093858bd84 /arch/arm/mach-pxa/include/mach/zeus.h | |
| parent | 69266866a5790080d7fe80094b28d670ff8aa765 (diff) | |
| parent | 3cc4e53f86dab635166929bfa47cc68d59b28c26 (diff) | |
Merge branch 'for-2.6.34' into for-2.6.35
Diffstat (limited to 'arch/arm/mach-pxa/include/mach/zeus.h')
| -rw-r--r-- | arch/arm/mach-pxa/include/mach/zeus.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/mach-pxa/include/mach/zeus.h b/arch/arm/mach-pxa/include/mach/zeus.h index c387046d2f2..6e119976003 100644 --- a/arch/arm/mach-pxa/include/mach/zeus.h +++ b/arch/arm/mach-pxa/include/mach/zeus.h | |||
| @@ -58,6 +58,8 @@ | |||
| 58 | #define ZEUS_EXT1_GPIO(x) (ZEUS_EXT1_GPIO_BASE + (x)) | 58 | #define ZEUS_EXT1_GPIO(x) (ZEUS_EXT1_GPIO_BASE + (x)) |
| 59 | #define ZEUS_USER_GPIO(x) (ZEUS_USER_GPIO_BASE + (x)) | 59 | #define ZEUS_USER_GPIO(x) (ZEUS_USER_GPIO_BASE + (x)) |
| 60 | 60 | ||
| 61 | #define ZEUS_CAN_SHDN_GPIO ZEUS_EXT1_GPIO(2) | ||
| 62 | |||
| 61 | /* | 63 | /* |
| 62 | * CPLD registers: | 64 | * CPLD registers: |
| 63 | * Only 4 registers, but spreaded over a 32MB address space. | 65 | * Only 4 registers, but spreaded over a 32MB address space. |
| @@ -68,7 +70,6 @@ | |||
| 68 | #define ZEUS_CPLD_VERSION (ZEUS_CPLD + 0x0000) | 70 | #define ZEUS_CPLD_VERSION (ZEUS_CPLD + 0x0000) |
| 69 | #define ZEUS_CPLD_ISA_IRQ (ZEUS_CPLD + 0x1000) | 71 | #define ZEUS_CPLD_ISA_IRQ (ZEUS_CPLD + 0x1000) |
| 70 | #define ZEUS_CPLD_CONTROL (ZEUS_CPLD + 0x2000) | 72 | #define ZEUS_CPLD_CONTROL (ZEUS_CPLD + 0x2000) |
| 71 | #define ZEUS_CPLD_EXTWDOG (ZEUS_CPLD + 0x3000) | ||
| 72 | 73 | ||
| 73 | /* CPLD register bits */ | 74 | /* CPLD register bits */ |
| 74 | #define ZEUS_CPLD_CONTROL_CF_RST 0x01 | 75 | #define ZEUS_CPLD_CONTROL_CF_RST 0x01 |