[ARM] 5204/1: Trizeps4 SOM update

- use MFP-API for GPIO
- support TRIZEPS4WL module
- cleanups

Signed-off-by: Jrgen Schindele <linux@schindele.name>
Acked-by: Eric Miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 70 insertions, 14 deletions

diff --git a/arch/arm/mach-pxa/include/mach/trizeps4.h b/arch/arm/mach-pxa/include/mach/trizeps4.h
index 641d0ec110b..903e1a2e664 100644
--- a/arch/arm/mach-pxa/include/mach/trizeps4.h
+++ b/arch/arm/mach-pxa/include/mach/trizeps4.h
@@ -17,11 +17,16 @@
 #define TRIZEPS4_PIC_PHYS       (PXA_CS3_PHYS)  /* Logic chip on ConXS-Board */
 #define TRIZEPS4_SDRAM_BASE     0xa0000000      /* SDRAM region */
 
-#define TRIZEPS4_CFSR_PHYS      (PXA_CS3_PHYS)                  /* Logic chip on ConXS-Board CSFR register */
-#define TRIZEPS4_BOCR_PHYS      (PXA_CS3_PHYS+0x02000000)       /* Logic chip on ConXS-Board BOCR register */
-#define TRIZEPS4_IRCR_PHYS      (PXA_CS3_PHYS+0x02400000)       /* Logic chip on ConXS-Board IRCR register*/
-#define TRIZEPS4_UPSR_PHYS      (PXA_CS3_PHYS+0x02800000)       /* Logic chip on ConXS-Board UPSR register*/
-#define TRIZEPS4_DICR_PHYS      (PXA_CS3_PHYS+0x03800000)       /* Logic chip on ConXS-Board DICR register*/
+                                /* Logic on ConXS-board CSFR register*/
+#define TRIZEPS4_CFSR_PHYS      (PXA_CS3_PHYS)
+                                /* Logic on ConXS-board BOCR register*/
+#define TRIZEPS4_BOCR_PHYS      (PXA_CS3_PHYS+0x02000000)
+                                /* Logic on ConXS-board IRCR register*/
+#define TRIZEPS4_IRCR_PHYS      (PXA_CS3_PHYS+0x02400000)
+                                /* Logic on ConXS-board UPSR register*/
+#define TRIZEPS4_UPSR_PHYS      (PXA_CS3_PHYS+0x02800000)
+                                /* Logic on ConXS-board DICR register*/
+#define TRIZEPS4_DICR_PHYS      (PXA_CS3_PHYS+0x03800000)
 
 /* virtual memory regions */
 #define TRIZEPS4_DISK_VIRT      0xF0000000      /* Disk On Chip region */
@@ -54,6 +59,15 @@
 #define GPIO_MMC_DET            12
 #define TRIZEPS4_MMC_IRQ        IRQ_GPIO(GPIO_MMC_DET)
 
+/* DOC NAND chip */
+#define GPIO_DOC_LOCK           94
+#define GPIO_DOC_IRQ            93
+#define TRIZEPS4_DOC_IRQ        IRQ_GPIO(GPIO_DOC_IRQ)
+
+/* SPI interface */
+#define GPIO_SPI                53
+#define TRIZEPS4_SPI_IRQ        IRQ_GPIO(GPIO_SPI)
+
 /* LEDS using tx2 / rx2 */
 #define GPIO_SYS_BUSY_LED       46
 #define GPIO_HEARTBEAT_LED      47
@@ -62,24 +76,66 @@
 #define GPIO_PIC                0
 #define TRIZEPS4_PIC_IRQ        IRQ_GPIO(GPIO_PIC)
 
-#define CFSR_P2V(x)             ((x) - TRIZEPS4_CFSR_PHYS + TRIZEPS4_CFSR_VIRT)
-#define CFSR_V2P(x)             ((x) - TRIZEPS4_CFSR_VIRT + TRIZEPS4_CFSR_PHYS)
+#ifdef CONFIG_MACH_TRIZEPS_CONXS
+/* for CONXS base board define these registers */
+#define CFSR_P2V(x)     ((x) - TRIZEPS4_CFSR_PHYS + TRIZEPS4_CFSR_VIRT)
+#define CFSR_V2P(x)     ((x) - TRIZEPS4_CFSR_VIRT + TRIZEPS4_CFSR_PHYS)
 
-#define BCR_P2V(x)              ((x) - TRIZEPS4_BOCR_PHYS + TRIZEPS4_BOCR_VIRT)
-#define BCR_V2P(x)              ((x) - TRIZEPS4_BOCR_VIRT + TRIZEPS4_BOCR_PHYS)
+#define BCR_P2V(x)      ((x) - TRIZEPS4_BOCR_PHYS + TRIZEPS4_BOCR_VIRT)
+#define BCR_V2P(x)      ((x) - TRIZEPS4_BOCR_VIRT + TRIZEPS4_BOCR_PHYS)
 
-#define DCR_P2V(x)              ((x) - TRIZEPS4_DICR_PHYS + TRIZEPS4_DICR_VIRT)
-#define DCR_V2P(x)              ((x) - TRIZEPS4_DICR_VIRT + TRIZEPS4_DICR_PHYS)
+#define DCR_P2V(x)      ((x) - TRIZEPS4_DICR_PHYS + TRIZEPS4_DICR_VIRT)
+#define DCR_V2P(x)      ((x) - TRIZEPS4_DICR_VIRT + TRIZEPS4_DICR_PHYS)
+
+#define IRCR_P2V(x)     ((x) - TRIZEPS4_IRCR_PHYS + TRIZEPS4_IRCR_VIRT)
+#define IRCR_V2P(x)     ((x) - TRIZEPS4_IRCR_VIRT + TRIZEPS4_IRCR_PHYS)
 
 #ifndef __ASSEMBLY__
-#define ConXS_CFSR              (*((volatile unsigned short *)CFSR_P2V(0x0C000000)))
-#define ConXS_BCR               (*((volatile unsigned short *)BCR_P2V(0x0E000000)))
-#define ConXS_DCR               (*((volatile unsigned short *)DCR_P2V(0x0F800000)))
+static inline unsigned short CFSR_readw(void)
+{
+        /* [Compact Flash Status Register] is read only */
+        return *((unsigned short *)CFSR_P2V(0x0C000000));
+}
+static inline void BCR_writew(unsigned short value)
+{
+        /* [Board Control Regsiter] is write only */
+        *((unsigned short *)BCR_P2V(0x0E000000)) = value;
+}
+static inline void DCR_writew(unsigned short value)
+{
+        /* [Display Control Register] is write only */
+        *((unsigned short *)DCR_P2V(0x0E000000)) = value;
+}
+static inline void IRCR_writew(unsigned short value)
+{
+        /* [InfraRed data Control Register] is write only */
+        *((unsigned short *)IRCR_P2V(0x0E000000)) = value;
+}
 #else
 #define ConXS_CFSR              CFSR_P2V(0x0C000000)
 #define ConXS_BCR               BCR_P2V(0x0E000000)
 #define ConXS_DCR               DCR_P2V(0x0F800000)
+#define ConXS_IRCR              IRCR_P2V(0x0F800000)
 #endif
+#else
+/* for whatever baseboard define function registers */
+static inline unsigned short CFSR_readw(void)
+{
+        return 0;
+}
+static inline void BCR_writew(unsigned short value)
+{
+        ;
+}
+static inline void DCR_writew(unsigned short value)
+{
+        ;
+}
+static inline void IRCR_writew(unsigned short value)
+{
+        ;
+}
+#endif  /* CONFIG_MACH_TRIZEPS_CONXS */
 
 #define ConXS_CFSR_BVD_MASK     0x0003
 #define ConXS_CFSR_BVD1         (1 << 0)