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authorSimon Arlott <simon@fire.lp0.eu>2007-05-11 15:40:30 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-05-20 15:10:32 -0400
commit6cbdc8c5357276307a77deeada3f04626ff17da6 (patch)
treee0a4190d816fa4efb6ddb331b859bf0d5eb9c1a3 /arch/arm/mach-pxa/corgi_lcd.c
parentfc432e1952a3899ce35e84b417e5d60f74cb901b (diff)
[ARM] spelling fixes
Spelling fixes in arch/arm/. Signed-off-by: Simon Arlott <simon@fire.lp0.eu> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-pxa/corgi_lcd.c')
-rw-r--r--arch/arm/mach-pxa/corgi_lcd.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/mach-pxa/corgi_lcd.c b/arch/arm/mach-pxa/corgi_lcd.c
index a72476c2462..365b9435f74 100644
--- a/arch/arm/mach-pxa/corgi_lcd.c
+++ b/arch/arm/mach-pxa/corgi_lcd.c
@@ -40,7 +40,7 @@
40#define PICTRL_ADRS 0x06 40#define PICTRL_ADRS 0x06
41#define POLCTRL_ADRS 0x07 41#define POLCTRL_ADRS 0x07
42 42
43/* Resgister Bit Definitions */ 43/* Register Bit Definitions */
44#define RESCTL_QVGA 0x01 44#define RESCTL_QVGA 0x01
45#define RESCTL_VGA 0x00 45#define RESCTL_VGA 0x00
46 46
@@ -55,11 +55,11 @@
55#define POWER0_COM_DCLK 0x01 /* COM Voltage DC Bias DAC Serial Data Clock */ 55#define POWER0_COM_DCLK 0x01 /* COM Voltage DC Bias DAC Serial Data Clock */
56#define POWER0_COM_DOUT 0x02 /* COM Voltage DC Bias DAC Serial Data Out */ 56#define POWER0_COM_DOUT 0x02 /* COM Voltage DC Bias DAC Serial Data Out */
57#define POWER0_DAC_ON 0x04 /* DAC Power Supply ON */ 57#define POWER0_DAC_ON 0x04 /* DAC Power Supply ON */
58#define POWER0_COM_ON 0x08 /* COM Powewr Supply ON */ 58#define POWER0_COM_ON 0x08 /* COM Power Supply ON */
59#define POWER0_VCC5_ON 0x10 /* VCC5 Power Supply ON */ 59#define POWER0_VCC5_ON 0x10 /* VCC5 Power Supply ON */
60 60
61#define POWER0_DAC_OFF 0x00 /* DAC Power Supply OFF */ 61#define POWER0_DAC_OFF 0x00 /* DAC Power Supply OFF */
62#define POWER0_COM_OFF 0x00 /* COM Powewr Supply OFF */ 62#define POWER0_COM_OFF 0x00 /* COM Power Supply OFF */
63#define POWER0_VCC5_OFF 0x00 /* VCC5 Power Supply OFF */ 63#define POWER0_VCC5_OFF 0x00 /* VCC5 Power Supply OFF */
64 64
65#define PICTRL_INIT_STATE 0x01 65#define PICTRL_INIT_STATE 0x01
@@ -145,7 +145,7 @@ static void lcdtg_set_common_voltage(u8 base_data, u8 data)
145 lcdtg_i2c_send_stop(base_data); 145 lcdtg_i2c_send_stop(base_data);
146} 146}
147 147
148/* Set Phase Adjuct */ 148/* Set Phase Adjust */
149static void lcdtg_set_phadadj(int mode) 149static void lcdtg_set_phadadj(int mode)
150{ 150{
151 int adj; 151 int adj;
@@ -226,7 +226,7 @@ static void lcdtg_hw_init(int mode)
226 /* Signals output enable */ 226 /* Signals output enable */
227 corgi_ssp_lcdtg_send(PICTRL_ADRS, 0); 227 corgi_ssp_lcdtg_send(PICTRL_ADRS, 0);
228 228
229 /* Set Phase Adjuct */ 229 /* Set Phase Adjust */
230 lcdtg_set_phadadj(mode); 230 lcdtg_set_phadadj(mode);
231 231
232 /* Initialize for Input Signals from ATI */ 232 /* Initialize for Input Signals from ATI */