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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2008-11-04 13:59:32 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-02-08 06:38:40 -0500
commitbc51da4ee46d481dc3fbc57ec407594b80e92705 (patch)
tree35f3ad987f9c655127bd449a703b1222e6209484 /arch/arm/mach-omap2/clock34xx.h
parentb36ee724208358bd892ad279efce629740517149 (diff)
[ARM] omap: eliminate unnecessary conditionals in omap2_clk_wait_ready
Rather than employing run-time tests in omap2_clk_wait_ready() to decide whether we need to wait for the clock to become ready, we can set the .ops appropriately. This change deals with the OMAP24xx and OMAP34xx conditionals only. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-omap2/clock34xx.h')
-rw-r--r--arch/arm/mach-omap2/clock34xx.h14
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 0d6a11ca132..1ff05d351b3 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -1652,7 +1652,7 @@ static const struct clksel ssi_ssr_clksel[] = {
1652 1652
1653static struct clk ssi_ssr_fck = { 1653static struct clk ssi_ssr_fck = {
1654 .name = "ssi_ssr_fck", 1654 .name = "ssi_ssr_fck",
1655 .ops = &clkops_omap2_dflt_wait, 1655 .ops = &clkops_omap2_dflt,
1656 .init = &omap2_init_clksel_parent, 1656 .init = &omap2_init_clksel_parent,
1657 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1657 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1658 .enable_bit = OMAP3430_EN_SSI_SHIFT, 1658 .enable_bit = OMAP3430_EN_SSI_SHIFT,
@@ -2064,7 +2064,7 @@ static struct clk ssi_l4_ick = {
2064 2064
2065static struct clk ssi_ick = { 2065static struct clk ssi_ick = {
2066 .name = "ssi_ick", 2066 .name = "ssi_ick",
2067 .ops = &clkops_omap2_dflt_wait, 2067 .ops = &clkops_omap2_dflt,
2068 .parent = &ssi_l4_ick, 2068 .parent = &ssi_l4_ick,
2069 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2069 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2070 .enable_bit = OMAP3430_EN_SSI_SHIFT, 2070 .enable_bit = OMAP3430_EN_SSI_SHIFT,
@@ -2156,7 +2156,7 @@ static const struct clksel dss1_alwon_fck_clksel[] = {
2156 2156
2157static struct clk dss1_alwon_fck = { 2157static struct clk dss1_alwon_fck = {
2158 .name = "dss1_alwon_fck", 2158 .name = "dss1_alwon_fck",
2159 .ops = &clkops_omap2_dflt_wait, 2159 .ops = &clkops_omap2_dflt,
2160 .parent = &dpll4_m4x2_ck, 2160 .parent = &dpll4_m4x2_ck,
2161 .init = &omap2_init_clksel_parent, 2161 .init = &omap2_init_clksel_parent,
2162 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), 2162 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
@@ -2171,7 +2171,7 @@ static struct clk dss1_alwon_fck = {
2171 2171
2172static struct clk dss_tv_fck = { 2172static struct clk dss_tv_fck = {
2173 .name = "dss_tv_fck", 2173 .name = "dss_tv_fck",
2174 .ops = &clkops_omap2_dflt_wait, 2174 .ops = &clkops_omap2_dflt,
2175 .parent = &omap_54m_fck, 2175 .parent = &omap_54m_fck,
2176 .init = &omap2_init_clk_clkdm, 2176 .init = &omap2_init_clk_clkdm,
2177 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), 2177 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
@@ -2183,7 +2183,7 @@ static struct clk dss_tv_fck = {
2183 2183
2184static struct clk dss_96m_fck = { 2184static struct clk dss_96m_fck = {
2185 .name = "dss_96m_fck", 2185 .name = "dss_96m_fck",
2186 .ops = &clkops_omap2_dflt_wait, 2186 .ops = &clkops_omap2_dflt,
2187 .parent = &omap_96m_fck, 2187 .parent = &omap_96m_fck,
2188 .init = &omap2_init_clk_clkdm, 2188 .init = &omap2_init_clk_clkdm,
2189 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), 2189 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
@@ -2195,7 +2195,7 @@ static struct clk dss_96m_fck = {
2195 2195
2196static struct clk dss2_alwon_fck = { 2196static struct clk dss2_alwon_fck = {
2197 .name = "dss2_alwon_fck", 2197 .name = "dss2_alwon_fck",
2198 .ops = &clkops_omap2_dflt_wait, 2198 .ops = &clkops_omap2_dflt,
2199 .parent = &sys_ck, 2199 .parent = &sys_ck,
2200 .init = &omap2_init_clk_clkdm, 2200 .init = &omap2_init_clk_clkdm,
2201 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), 2201 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
@@ -2208,7 +2208,7 @@ static struct clk dss2_alwon_fck = {
2208static struct clk dss_ick = { 2208static struct clk dss_ick = {
2209 /* Handles both L3 and L4 clocks */ 2209 /* Handles both L3 and L4 clocks */
2210 .name = "dss_ick", 2210 .name = "dss_ick",
2211 .ops = &clkops_omap2_dflt_wait, 2211 .ops = &clkops_omap2_dflt,
2212 .parent = &l4_ick, 2212 .parent = &l4_ick,
2213 .init = &omap2_init_clk_clkdm, 2213 .init = &omap2_init_clk_clkdm,
2214 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), 2214 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),