diff options
author | Paul Walmsley <paul@pwsan.com> | 2009-12-08 18:18:44 -0500 |
---|---|---|
committer | paul <paul@twilight.(none)> | 2009-12-11 18:12:07 -0500 |
commit | ebd893ded2733b8bd9ba403ee4a9e6ab6fbc2a54 (patch) | |
tree | c8c31ef40c271421ddebe16c5f513a97268d503e /arch/arm/mach-omap2/clock34xx.c | |
parent | aa2cf420593b67cc93de7a3f675b2a88eba0505f (diff) |
OMAP1/2/3 clock: remove paranoid checks in preparation for clock{,2xxx,3xxx}_data.c
Some parts of the clock code took advantage of the fact that the statically
allocated clock tree was in clock{,24xx,34xx}.c's local namespace to do some
extra argument checks. These are overzealous and are more difficult to
maintain when the clock tree is in a separate namespace, so, remove them.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock34xx.c')
-rw-r--r-- | arch/arm/mach-omap2/clock34xx.c | 18 |
1 files changed, 0 insertions, 18 deletions
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index ecbb5cd8eec..523978a58d4 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c | |||
@@ -520,9 +520,6 @@ static int _omap3_noncore_dpll_lock(struct clk *clk) | |||
520 | u8 ai; | 520 | u8 ai; |
521 | int r; | 521 | int r; |
522 | 522 | ||
523 | if (clk == &dpll3_ck) | ||
524 | return -EINVAL; | ||
525 | |||
526 | pr_debug("clock: locking DPLL %s\n", clk->name); | 523 | pr_debug("clock: locking DPLL %s\n", clk->name); |
527 | 524 | ||
528 | ai = omap3_dpll_autoidle_read(clk); | 525 | ai = omap3_dpll_autoidle_read(clk); |
@@ -557,9 +554,6 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk) | |||
557 | int r; | 554 | int r; |
558 | u8 ai; | 555 | u8 ai; |
559 | 556 | ||
560 | if (clk == &dpll3_ck) | ||
561 | return -EINVAL; | ||
562 | |||
563 | if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) | 557 | if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) |
564 | return -EINVAL; | 558 | return -EINVAL; |
565 | 559 | ||
@@ -593,9 +587,6 @@ static int _omap3_noncore_dpll_stop(struct clk *clk) | |||
593 | { | 587 | { |
594 | u8 ai; | 588 | u8 ai; |
595 | 589 | ||
596 | if (clk == &dpll3_ck) | ||
597 | return -EINVAL; | ||
598 | |||
599 | if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP))) | 590 | if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP))) |
600 | return -EINVAL; | 591 | return -EINVAL; |
601 | 592 | ||
@@ -632,9 +623,6 @@ static int omap3_noncore_dpll_enable(struct clk *clk) | |||
632 | int r; | 623 | int r; |
633 | struct dpll_data *dd; | 624 | struct dpll_data *dd; |
634 | 625 | ||
635 | if (clk == &dpll3_ck) | ||
636 | return -EINVAL; | ||
637 | |||
638 | dd = clk->dpll_data; | 626 | dd = clk->dpll_data; |
639 | if (!dd) | 627 | if (!dd) |
640 | return -EINVAL; | 628 | return -EINVAL; |
@@ -669,9 +657,6 @@ static int omap3_noncore_dpll_enable(struct clk *clk) | |||
669 | */ | 657 | */ |
670 | static void omap3_noncore_dpll_disable(struct clk *clk) | 658 | static void omap3_noncore_dpll_disable(struct clk *clk) |
671 | { | 659 | { |
672 | if (clk == &dpll3_ck) | ||
673 | return; | ||
674 | |||
675 | _omap3_noncore_dpll_stop(clk); | 660 | _omap3_noncore_dpll_stop(clk); |
676 | } | 661 | } |
677 | 662 | ||
@@ -844,9 +829,6 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) | |||
844 | if (!clk || !rate) | 829 | if (!clk || !rate) |
845 | return -EINVAL; | 830 | return -EINVAL; |
846 | 831 | ||
847 | if (clk != &dpll3_m2_ck) | ||
848 | return -EINVAL; | ||
849 | |||
850 | validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); | 832 | validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); |
851 | if (validrate != rate) | 833 | if (validrate != rate) |
852 | return -EINVAL; | 834 | return -EINVAL; |