ARM: OMAP2: New DPLL clock framework

These changes is the result of the discussion with Paul Walmsley.
His ideas are included into this patch.

Remove DPLL output divider handling from DPLLs and CLKOUTX2 clocks,
and place it into specific DPLL output divider clocks (e.g., dpll3_m2_clk).
omap2_get_dpll_rate() now returns the correct DPLL rate, as represented
by the DPLL's CLKOUT output. Also add MPU and IVA2 subsystem clocks, along
with high-frequency bypass support.

Add support for DPLLs function in locked and bypass clock modes.

Signed-off-by: Roman Tereshonkov <roman.tereshonkov@nokia.com>
Acked-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

1 files changed, 0 insertions, 8 deletions

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index a5b9564ea78..b57ffb5a22a 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -111,14 +111,6 @@ u32 omap2_get_dpll_rate(struct clk *clk)
         dpll_clk = (long long)clk->parent->rate * dpll_mult;
         do_div(dpll_clk, dpll_div + 1);
 
-        /* 34XX only */
-        if (dd->div2_reg) {
-                dpll = __raw_readl(dd->div2_reg);
-                dpll_div = dpll & dd->div2_mask;
-                dpll_div >>= __ffs(dd->div2_mask);
-                do_div(dpll_clk, dpll_div + 1);
-        }
-
         return dpll_clk;
 }