diff options
author | Grant Likely <grant.likely@secretlab.ca> | 2007-10-23 00:27:41 -0400 |
---|---|---|
committer | Josh Boyer <jwboyer@linux.vnet.ibm.com> | 2007-11-01 08:11:18 -0400 |
commit | 7ae0fa49c6502ca1ada0e043c5d25ee73c0a28c6 (patch) | |
tree | d56a8f130987d12d6f7bb58ca30e93b7176d2559 /Documentation | |
parent | d47403733403bec7c050cce6f6ff56dfcf80b8b7 (diff) |
[POWERPC] Device tree bindings for Xilinx devices
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Acked-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Diffstat (limited to 'Documentation')
-rw-r--r-- | Documentation/powerpc/booting-without-of.txt | 261 |
1 files changed, 261 insertions, 0 deletions
diff --git a/Documentation/powerpc/booting-without-of.txt b/Documentation/powerpc/booting-without-of.txt index a96e85397eb..59df69d56a7 100644 --- a/Documentation/powerpc/booting-without-of.txt +++ b/Documentation/powerpc/booting-without-of.txt | |||
@@ -52,6 +52,7 @@ Table of Contents | |||
52 | i) Freescale QUICC Engine module (QE) | 52 | i) Freescale QUICC Engine module (QE) |
53 | j) CFI or JEDEC memory-mapped NOR flash | 53 | j) CFI or JEDEC memory-mapped NOR flash |
54 | k) Global Utilities Block | 54 | k) Global Utilities Block |
55 | l) Xilinx IP cores | ||
55 | 56 | ||
56 | VII - Specifying interrupt information for devices | 57 | VII - Specifying interrupt information for devices |
57 | 1) interrupts property | 58 | 1) interrupts property |
@@ -2242,6 +2243,266 @@ platforms are moved over to use the flattened-device-tree model. | |||
2242 | available. | 2243 | available. |
2243 | For Axon: 0x0000012a | 2244 | For Axon: 0x0000012a |
2244 | 2245 | ||
2246 | l) Xilinx IP cores | ||
2247 | |||
2248 | The Xilinx EDK toolchain ships with a set of IP cores (devices) for use | ||
2249 | in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range | ||
2250 | of standard device types (network, serial, etc.) and miscellanious | ||
2251 | devices (gpio, LCD, spi, etc). Also, since these devices are | ||
2252 | implemented within the fpga fabric every instance of the device can be | ||
2253 | synthesised with different options that change the behaviour. | ||
2254 | |||
2255 | Each IP-core has a set of parameters which the FPGA designer can use to | ||
2256 | control how the core is synthesized. Historically, the EDK tool would | ||
2257 | extract the device parameters relevant to device drivers and copy them | ||
2258 | into an 'xparameters.h' in the form of #define symbols. This tells the | ||
2259 | device drivers how the IP cores are configured, but it requres the kernel | ||
2260 | to be recompiled every time the FPGA bitstream is resynthesized. | ||
2261 | |||
2262 | The new approach is to export the parameters into the device tree and | ||
2263 | generate a new device tree each time the FPGA bitstream changes. The | ||
2264 | parameters which used to be exported as #defines will now become | ||
2265 | properties of the device node. In general, device nodes for IP-cores | ||
2266 | will take the following form: | ||
2267 | |||
2268 | (name)@(base-address) { | ||
2269 | compatible = "xlnx,(ip-core-name)-(HW_VER)" | ||
2270 | [, (list of compatible devices), ...]; | ||
2271 | reg = <(baseaddr) (size)>; | ||
2272 | interrupt-parent = <&interrupt-controller-phandle>; | ||
2273 | interrupts = < ... >; | ||
2274 | xlnx,(parameter1) = "(string-value)"; | ||
2275 | xlnx,(parameter2) = <(int-value)>; | ||
2276 | }; | ||
2277 | |||
2278 | (ip-core-name): the name of the ip block (given after the BEGIN | ||
2279 | directive in system.mhs). Should be in lowercase | ||
2280 | and all underscores '_' converted to dashes '-'. | ||
2281 | (name): is derived from the "PARAMETER INSTANCE" value. | ||
2282 | (parameter#): C_* parameters from system.mhs. The C_ prefix is | ||
2283 | dropped from the parameter name, the name is converted | ||
2284 | to lowercase and all underscore '_' characters are | ||
2285 | converted to dashes '-'. | ||
2286 | (baseaddr): the C_BASEADDR parameter. | ||
2287 | (HW_VER): from the HW_VER parameter. | ||
2288 | (size): equals C_HIGHADDR - C_BASEADDR + 1 | ||
2289 | |||
2290 | Typically, the compatible list will include the exact IP core version | ||
2291 | followed by an older IP core version which implements the same | ||
2292 | interface or any other device with the same interface. | ||
2293 | |||
2294 | 'reg', 'interrupt-parent' and 'interrupts' are all optional properties. | ||
2295 | |||
2296 | For example, the following block from system.mhs: | ||
2297 | |||
2298 | BEGIN opb_uartlite | ||
2299 | PARAMETER INSTANCE = opb_uartlite_0 | ||
2300 | PARAMETER HW_VER = 1.00.b | ||
2301 | PARAMETER C_BAUDRATE = 115200 | ||
2302 | PARAMETER C_DATA_BITS = 8 | ||
2303 | PARAMETER C_ODD_PARITY = 0 | ||
2304 | PARAMETER C_USE_PARITY = 0 | ||
2305 | PARAMETER C_CLK_FREQ = 50000000 | ||
2306 | PARAMETER C_BASEADDR = 0xEC100000 | ||
2307 | PARAMETER C_HIGHADDR = 0xEC10FFFF | ||
2308 | BUS_INTERFACE SOPB = opb_7 | ||
2309 | PORT OPB_Clk = CLK_50MHz | ||
2310 | PORT Interrupt = opb_uartlite_0_Interrupt | ||
2311 | PORT RX = opb_uartlite_0_RX | ||
2312 | PORT TX = opb_uartlite_0_TX | ||
2313 | PORT OPB_Rst = sys_bus_reset_0 | ||
2314 | END | ||
2315 | |||
2316 | becomes the following device tree node: | ||
2317 | |||
2318 | opb-uartlite-0@ec100000 { | ||
2319 | device_type = "serial"; | ||
2320 | compatible = "xlnx,opb-uartlite-1.00.b"; | ||
2321 | reg = <ec100000 10000>; | ||
2322 | interrupt-parent = <&opb-intc>; | ||
2323 | interrupts = <1 0>; // got this from the opb_intc parameters | ||
2324 | current-speed = <d#115200>; // standard serial device prop | ||
2325 | clock-frequency = <d#50000000>; // standard serial device prop | ||
2326 | xlnx,data-bits = <8>; | ||
2327 | xlnx,odd-parity = <0>; | ||
2328 | xlnx,use-parity = <0>; | ||
2329 | }; | ||
2330 | |||
2331 | Some IP cores actually implement 2 or more logical devices. In this case, | ||
2332 | the device should still describe the whole IP core with a single node | ||
2333 | and add a child node for each logical device. The ranges property can | ||
2334 | be used to translate from parent IP-core to the registers of each device. | ||
2335 | (Note: this makes the assumption that both logical devices have the same | ||
2336 | bus binding. If this is not true, then separate nodes should be used for | ||
2337 | each logical device). The 'cell-index' property can be used to enumerate | ||
2338 | logical devices within an IP core. For example, the following is the | ||
2339 | system.mhs entry for the dual ps2 controller found on the ml403 reference | ||
2340 | design. | ||
2341 | |||
2342 | BEGIN opb_ps2_dual_ref | ||
2343 | PARAMETER INSTANCE = opb_ps2_dual_ref_0 | ||
2344 | PARAMETER HW_VER = 1.00.a | ||
2345 | PARAMETER C_BASEADDR = 0xA9000000 | ||
2346 | PARAMETER C_HIGHADDR = 0xA9001FFF | ||
2347 | BUS_INTERFACE SOPB = opb_v20_0 | ||
2348 | PORT Sys_Intr1 = ps2_1_intr | ||
2349 | PORT Sys_Intr2 = ps2_2_intr | ||
2350 | PORT Clkin1 = ps2_clk_rx_1 | ||
2351 | PORT Clkin2 = ps2_clk_rx_2 | ||
2352 | PORT Clkpd1 = ps2_clk_tx_1 | ||
2353 | PORT Clkpd2 = ps2_clk_tx_2 | ||
2354 | PORT Rx1 = ps2_d_rx_1 | ||
2355 | PORT Rx2 = ps2_d_rx_2 | ||
2356 | PORT Txpd1 = ps2_d_tx_1 | ||
2357 | PORT Txpd2 = ps2_d_tx_2 | ||
2358 | END | ||
2359 | |||
2360 | It would result in the following device tree nodes: | ||
2361 | |||
2362 | opb_ps2_dual_ref_0@a9000000 { | ||
2363 | ranges = <0 a9000000 2000>; | ||
2364 | // If this device had extra parameters, then they would | ||
2365 | // go here. | ||
2366 | ps2@0 { | ||
2367 | compatible = "xlnx,opb-ps2-dual-ref-1.00.a"; | ||
2368 | reg = <0 40>; | ||
2369 | interrupt-parent = <&opb-intc>; | ||
2370 | interrupts = <3 0>; | ||
2371 | cell-index = <0>; | ||
2372 | }; | ||
2373 | ps2@1000 { | ||
2374 | compatible = "xlnx,opb-ps2-dual-ref-1.00.a"; | ||
2375 | reg = <1000 40>; | ||
2376 | interrupt-parent = <&opb-intc>; | ||
2377 | interrupts = <3 0>; | ||
2378 | cell-index = <0>; | ||
2379 | }; | ||
2380 | }; | ||
2381 | |||
2382 | Also, the system.mhs file defines bus attachments from the processor | ||
2383 | to the devices. The device tree structure should reflect the bus | ||
2384 | attachments. Again an example; this system.mhs fragment: | ||
2385 | |||
2386 | BEGIN ppc405_virtex4 | ||
2387 | PARAMETER INSTANCE = ppc405_0 | ||
2388 | PARAMETER HW_VER = 1.01.a | ||
2389 | BUS_INTERFACE DPLB = plb_v34_0 | ||
2390 | BUS_INTERFACE IPLB = plb_v34_0 | ||
2391 | END | ||
2392 | |||
2393 | BEGIN opb_intc | ||
2394 | PARAMETER INSTANCE = opb_intc_0 | ||
2395 | PARAMETER HW_VER = 1.00.c | ||
2396 | PARAMETER C_BASEADDR = 0xD1000FC0 | ||
2397 | PARAMETER C_HIGHADDR = 0xD1000FDF | ||
2398 | BUS_INTERFACE SOPB = opb_v20_0 | ||
2399 | END | ||
2400 | |||
2401 | BEGIN opb_uart16550 | ||
2402 | PARAMETER INSTANCE = opb_uart16550_0 | ||
2403 | PARAMETER HW_VER = 1.00.d | ||
2404 | PARAMETER C_BASEADDR = 0xa0000000 | ||
2405 | PARAMETER C_HIGHADDR = 0xa0001FFF | ||
2406 | BUS_INTERFACE SOPB = opb_v20_0 | ||
2407 | END | ||
2408 | |||
2409 | BEGIN plb_v34 | ||
2410 | PARAMETER INSTANCE = plb_v34_0 | ||
2411 | PARAMETER HW_VER = 1.02.a | ||
2412 | END | ||
2413 | |||
2414 | BEGIN plb_bram_if_cntlr | ||
2415 | PARAMETER INSTANCE = plb_bram_if_cntlr_0 | ||
2416 | PARAMETER HW_VER = 1.00.b | ||
2417 | PARAMETER C_BASEADDR = 0xFFFF0000 | ||
2418 | PARAMETER C_HIGHADDR = 0xFFFFFFFF | ||
2419 | BUS_INTERFACE SPLB = plb_v34_0 | ||
2420 | END | ||
2421 | |||
2422 | BEGIN plb2opb_bridge | ||
2423 | PARAMETER INSTANCE = plb2opb_bridge_0 | ||
2424 | PARAMETER HW_VER = 1.01.a | ||
2425 | PARAMETER C_RNG0_BASEADDR = 0x20000000 | ||
2426 | PARAMETER C_RNG0_HIGHADDR = 0x3FFFFFFF | ||
2427 | PARAMETER C_RNG1_BASEADDR = 0x60000000 | ||
2428 | PARAMETER C_RNG1_HIGHADDR = 0x7FFFFFFF | ||
2429 | PARAMETER C_RNG2_BASEADDR = 0x80000000 | ||
2430 | PARAMETER C_RNG2_HIGHADDR = 0xBFFFFFFF | ||
2431 | PARAMETER C_RNG3_BASEADDR = 0xC0000000 | ||
2432 | PARAMETER C_RNG3_HIGHADDR = 0xDFFFFFFF | ||
2433 | BUS_INTERFACE SPLB = plb_v34_0 | ||
2434 | BUS_INTERFACE MOPB = opb_v20_0 | ||
2435 | END | ||
2436 | |||
2437 | Gives this device tree (some properties removed for clarity): | ||
2438 | |||
2439 | plb-v34-0 { | ||
2440 | #address-cells = <1>; | ||
2441 | #size-cells = <1>; | ||
2442 | device_type = "ibm,plb"; | ||
2443 | ranges; // 1:1 translation | ||
2444 | |||
2445 | plb-bram-if-cntrl-0@ffff0000 { | ||
2446 | reg = <ffff0000 10000>; | ||
2447 | } | ||
2448 | |||
2449 | opb-v20-0 { | ||
2450 | #address-cells = <1>; | ||
2451 | #size-cells = <1>; | ||
2452 | ranges = <20000000 20000000 20000000 | ||
2453 | 60000000 60000000 20000000 | ||
2454 | 80000000 80000000 40000000 | ||
2455 | c0000000 c0000000 20000000>; | ||
2456 | |||
2457 | opb-uart16550-0@a0000000 { | ||
2458 | reg = <a00000000 2000>; | ||
2459 | }; | ||
2460 | |||
2461 | opb-intc-0@d1000fc0 { | ||
2462 | reg = <d1000fc0 20>; | ||
2463 | }; | ||
2464 | }; | ||
2465 | }; | ||
2466 | |||
2467 | That covers the general approach to binding xilinx IP cores into the | ||
2468 | device tree. The following are bindings for specific devices: | ||
2469 | |||
2470 | i) Xilinx ML300 Framebuffer | ||
2471 | |||
2472 | Simple framebuffer device from the ML300 reference design (also on the | ||
2473 | ML403 reference design as well as others). | ||
2474 | |||
2475 | Optional properties: | ||
2476 | - resolution = <xres yres> : pixel resolution of framebuffer. Some | ||
2477 | implementations use a different resolution. | ||
2478 | Default is <d#640 d#480> | ||
2479 | - virt-resolution = <xvirt yvirt> : Size of framebuffer in memory. | ||
2480 | Default is <d#1024 d#480>. | ||
2481 | - rotate-display (empty) : rotate display 180 degrees. | ||
2482 | |||
2483 | ii) Xilinx SystemACE | ||
2484 | |||
2485 | The Xilinx SystemACE device is used to program FPGAs from an FPGA | ||
2486 | bitstream stored on a CF card. It can also be used as a generic CF | ||
2487 | interface device. | ||
2488 | |||
2489 | Optional properties: | ||
2490 | - 8-bit (empty) : Set this property for SystemACE in 8 bit mode | ||
2491 | |||
2492 | iii) Xilinx EMAC and Xilinx TEMAC | ||
2493 | |||
2494 | Xilinx Ethernet devices. In addition to general xilinx properties | ||
2495 | listed above, nodes for these devices should include a phy-handle | ||
2496 | property, and may include other common network device properties | ||
2497 | like local-mac-address. | ||
2498 | |||
2499 | iv) Xilinx Uartlite | ||
2500 | |||
2501 | Xilinx uartlite devices are simple fixed speed serial ports. | ||
2502 | |||
2503 | Requred properties: | ||
2504 | - current-speed : Baud rate of uartlite | ||
2505 | |||
2245 | More devices will be defined as this spec matures. | 2506 | More devices will be defined as this spec matures. |
2246 | 2507 | ||
2247 | VII - Specifying interrupt information for devices | 2508 | VII - Specifying interrupt information for devices |