diff options
author | R.Marek@sh.cvut.cz <R.Marek@sh.cvut.cz> | 2005-05-26 08:42:19 -0400 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@suse.de> | 2005-06-22 00:52:02 -0400 |
commit | 7f15b66468b7003d5241e352a007e73be5519b20 (patch) | |
tree | c9333e14baae06a831c8515d9e1e24808826053e /Documentation/i2c/chips/eeprom | |
parent | 2bf34a1ca9d570dd4fab4d95c4de82d873ecf718 (diff) |
[PATCH] I2C: documentation update 2/3
This patch adds missing documentation for system health monitoring chips.
I would like to thank all people, who helped me with this project.
Signed-off-by: Rudolf Marek <r.marek@sh.cvut.cz>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'Documentation/i2c/chips/eeprom')
-rw-r--r-- | Documentation/i2c/chips/eeprom | 96 |
1 files changed, 96 insertions, 0 deletions
diff --git a/Documentation/i2c/chips/eeprom b/Documentation/i2c/chips/eeprom new file mode 100644 index 00000000000..f7e8104b576 --- /dev/null +++ b/Documentation/i2c/chips/eeprom | |||
@@ -0,0 +1,96 @@ | |||
1 | Kernel driver eeprom | ||
2 | ==================== | ||
3 | |||
4 | Supported chips: | ||
5 | * Any EEPROM chip in the designated address range | ||
6 | Prefix: 'eeprom' | ||
7 | Addresses scanned: I2C 0x50 - 0x57 | ||
8 | Datasheets: Publicly available from: | ||
9 | Atmel (www.atmel.com), | ||
10 | Catalyst (www.catsemi.com), | ||
11 | Fairchild (www.fairchildsemi.com), | ||
12 | Microchip (www.microchip.com), | ||
13 | Philips (www.semiconductor.philips.com), | ||
14 | Rohm (www.rohm.com), | ||
15 | ST (www.st.com), | ||
16 | Xicor (www.xicor.com), | ||
17 | and others. | ||
18 | |||
19 | Chip Size (bits) Address | ||
20 | 24C01 1K 0x50 (shadows at 0x51 - 0x57) | ||
21 | 24C01A 1K 0x50 - 0x57 (Typical device on DIMMs) | ||
22 | 24C02 2K 0x50 - 0x57 | ||
23 | 24C04 4K 0x50, 0x52, 0x54, 0x56 | ||
24 | (additional data at 0x51, 0x53, 0x55, 0x57) | ||
25 | 24C08 8K 0x50, 0x54 (additional data at 0x51, 0x52, | ||
26 | 0x53, 0x55, 0x56, 0x57) | ||
27 | 24C16 16K 0x50 (additional data at 0x51 - 0x57) | ||
28 | Sony 2K 0x57 | ||
29 | |||
30 | Atmel 34C02B 2K 0x50 - 0x57, SW write protect at 0x30-37 | ||
31 | Catalyst 34FC02 2K 0x50 - 0x57, SW write protect at 0x30-37 | ||
32 | Catalyst 34RC02 2K 0x50 - 0x57, SW write protect at 0x30-37 | ||
33 | Fairchild 34W02 2K 0x50 - 0x57, SW write protect at 0x30-37 | ||
34 | Microchip 24AA52 2K 0x50 - 0x57, SW write protect at 0x30-37 | ||
35 | ST M34C02 2K 0x50 - 0x57, SW write protect at 0x30-37 | ||
36 | |||
37 | |||
38 | Authors: | ||
39 | Frodo Looijaard <frodol@dds.nl>, | ||
40 | Philip Edelbrock <phil@netroedge.com>, | ||
41 | Jean Delvare <khali@linux-fr.org>, | ||
42 | Greg Kroah-Hartman <greg@kroah.com>, | ||
43 | IBM Corp. | ||
44 | |||
45 | Description | ||
46 | ----------- | ||
47 | |||
48 | This is a simple EEPROM module meant to enable reading the first 256 bytes | ||
49 | of an EEPROM (on a SDRAM DIMM for example). However, it will access serial | ||
50 | EEPROMs on any I2C adapter. The supported devices are generically called | ||
51 | 24Cxx, and are listed above; however the numbering for these | ||
52 | industry-standard devices may vary by manufacturer. | ||
53 | |||
54 | This module was a programming exercise to get used to the new project | ||
55 | organization laid out by Frodo, but it should be at least completely | ||
56 | effective for decoding the contents of EEPROMs on DIMMs. | ||
57 | |||
58 | DIMMS will typically contain a 24C01A or 24C02, or the 34C02 variants. | ||
59 | The other devices will not be found on a DIMM because they respond to more | ||
60 | than one address. | ||
61 | |||
62 | DDC Monitors may contain any device. Often a 24C01, which responds to all 8 | ||
63 | addresses, is found. | ||
64 | |||
65 | Recent Sony Vaio laptops have an EEPROM at 0x57. We couldn't get the | ||
66 | specification, so it is guess work and far from being complete. | ||
67 | |||
68 | The Microchip 24AA52/24LCS52, ST M34C02, and others support an additional | ||
69 | software write protect register at 0x30 - 0x37 (0x20 less than the memory | ||
70 | location). The chip responds to "write quick" detection at this address but | ||
71 | does not respond to byte reads. If this register is present, the lower 128 | ||
72 | bytes of the memory array are not write protected. Any byte data write to | ||
73 | this address will write protect the memory array permanently, and the | ||
74 | device will no longer respond at the 0x30-37 address. The eeprom driver | ||
75 | does not support this register. | ||
76 | |||
77 | Lacking functionality: | ||
78 | |||
79 | * Full support for larger devices (24C04, 24C08, 24C16). These are not | ||
80 | typically found on a PC. These devices will appear as separate devices at | ||
81 | multiple addresses. | ||
82 | |||
83 | * Support for really large devices (24C32, 24C64, 24C128, 24C256, 24C512). | ||
84 | These devices require two-byte address fields and are not supported. | ||
85 | |||
86 | * Enable Writing. Again, no technical reason why not, but making it easy | ||
87 | to change the contents of the EEPROMs (on DIMMs anyway) also makes it easy | ||
88 | to disable the DIMMs (potentially preventing the computer from booting) | ||
89 | until the values are restored somehow. | ||
90 | |||
91 | Use: | ||
92 | |||
93 | After inserting the module (and any other required SMBus/i2c modules), you | ||
94 | should have some EEPROM directories in /sys/bus/i2c/devices/* of names such | ||
95 | as "0-0050". Inside each of these is a series of files, the eeprom file | ||
96 | contains the binary data from EEPROM. | ||