diff options
author | Chen Gong <gong.chen@linux.intel.com> | 2010-08-09 20:21:10 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2010-08-09 23:45:10 -0400 |
commit | f3cffe4d1a20208da9bf2c9cc0a973bf091eb160 (patch) | |
tree | f79f587b6300f4b7bced1ac7df31df4d99cd27e6 /Documentation/hwmon | |
parent | 851b29cb3b196cb66452ec964ab5f66c9c9cd1ed (diff) |
hwmon: coretemp: documentation update and cleanup
Update coretemp supported CPU TjMax lists and some cleanup work.
Signed-off-by: Chen Gong <gong.chen@linux.intel.com>
Cc: Rudolf Marek <r.marek@assembler.cz>
Cc: Huaxu Wan <huaxu.wan@intel.com>
Cc: Jean Delvare <khali@linux-fr.org>
Cc: Guenter Roeck <guenter.roeck@ericsson.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'Documentation/hwmon')
-rw-r--r-- | Documentation/hwmon/coretemp | 105 |
1 files changed, 103 insertions, 2 deletions
diff --git a/Documentation/hwmon/coretemp b/Documentation/hwmon/coretemp index 92267b62db5..25568f84480 100644 --- a/Documentation/hwmon/coretemp +++ b/Documentation/hwmon/coretemp | |||
@@ -21,8 +21,8 @@ Temperature is measured in degrees Celsius and measurement resolution is | |||
21 | 1 degree C. Valid temperatures are from 0 to TjMax degrees C, because | 21 | 1 degree C. Valid temperatures are from 0 to TjMax degrees C, because |
22 | the actual value of temperature register is in fact a delta from TjMax. | 22 | the actual value of temperature register is in fact a delta from TjMax. |
23 | 23 | ||
24 | Temperature known as TjMax is the maximum junction temperature of processor. | 24 | Temperature known as TjMax is the maximum junction temperature of processor, |
25 | Intel defines this temperature as 85C or 100C. At this temperature, protection | 25 | which depends on the CPU model. See table below. At this temperature, protection |
26 | mechanism will perform actions to forcibly cool down the processor. Alarm | 26 | mechanism will perform actions to forcibly cool down the processor. Alarm |
27 | may be raised, if the temperature grows enough (more than TjMax) to trigger | 27 | may be raised, if the temperature grows enough (more than TjMax) to trigger |
28 | the Out-Of-Spec bit. Following table summarizes the exported sysfs files: | 28 | the Out-Of-Spec bit. Following table summarizes the exported sysfs files: |
@@ -38,3 +38,104 @@ temp1_label - Contains string "Core X", where X is processor | |||
38 | The TjMax temperature is set to 85 degrees C if undocumented model specific | 38 | The TjMax temperature is set to 85 degrees C if undocumented model specific |
39 | register (UMSR) 0xee has bit 30 set. If not the TjMax is 100 degrees C as | 39 | register (UMSR) 0xee has bit 30 set. If not the TjMax is 100 degrees C as |
40 | (sometimes) documented in processor datasheet. | 40 | (sometimes) documented in processor datasheet. |
41 | |||
42 | Appendix A. Known TjMax lists (TBD): | ||
43 | Some information comes from ark.intel.com | ||
44 | |||
45 | Process Processor TjMax(C) | ||
46 | |||
47 | 32nm Core i3/i5/i7 Processors | ||
48 | i7 660UM/640/620, 640LM/620, 620M, 610E 105 | ||
49 | i5 540UM/520/430, 540M/520/450/430 105 | ||
50 | i3 330E, 370M/350/330 90 rPGA, 105 BGA | ||
51 | i3 330UM 105 | ||
52 | |||
53 | 32nm Core i7 Extreme Processors | ||
54 | 980X 100 | ||
55 | |||
56 | 32nm Celeron Processors | ||
57 | U3400 105 | ||
58 | P4505/P4500 90 | ||
59 | |||
60 | 45nm Xeon Processors 5400 Quad-Core | ||
61 | X5492, X5482, X5472, X5470, X5460, X5450 85 | ||
62 | E5472, E5462, E5450/40/30/20/10/05 85 | ||
63 | L5408 95 | ||
64 | L5430, L5420, L5410 70 | ||
65 | |||
66 | 45nm Xeon Processors 5200 Dual-Core | ||
67 | X5282, X5272, X5270, X5260 90 | ||
68 | E5240 90 | ||
69 | E5205, E5220 70, 90 | ||
70 | L5240 70 | ||
71 | L5238, L5215 95 | ||
72 | |||
73 | 45nm Atom Processors | ||
74 | D525/510/425/410 100 | ||
75 | Z560/550/540/530P/530/520PT/520/515/510PT/510P 90 | ||
76 | Z510/500 90 | ||
77 | N475/470/455/450 100 | ||
78 | N280/270 90 | ||
79 | 330/230 125 | ||
80 | |||
81 | 45nm Core2 Processors | ||
82 | Solo ULV SU3500/3300 100 | ||
83 | T9900/9800/9600/9550/9500/9400/9300/8300/8100 105 | ||
84 | T6670/6500/6400 105 | ||
85 | T6600 90 | ||
86 | SU9600/9400/9300 105 | ||
87 | SP9600/9400 105 | ||
88 | SL9600/9400/9380/9300 105 | ||
89 | P9700/9600/9500/8800/8700/8600/8400/7570 105 | ||
90 | P7550/7450 90 | ||
91 | |||
92 | 45nm Core2 Quad Processors | ||
93 | Q9100/9000 100 | ||
94 | |||
95 | 45nm Core2 Extreme Processors | ||
96 | X9100/9000 105 | ||
97 | QX9300 100 | ||
98 | |||
99 | 45nm Core i3/i5/i7 Processors | ||
100 | i7 940XM/920 100 | ||
101 | i7 840QM/820/740/720 100 | ||
102 | |||
103 | 45nm Celeron Processors | ||
104 | SU2300 100 | ||
105 | 900 105 | ||
106 | |||
107 | 65nm Core2 Duo Processors | ||
108 | Solo U2200, U2100 100 | ||
109 | U7700/7600/7500 100 | ||
110 | T7800/7700/7600/7500/7400/7300/7250/7200/7100 100 | ||
111 | T5870/5670/5600/5550/5500/5470/5450/5300/5270 100 | ||
112 | T5250 100 | ||
113 | T5800/5750/5200 85 | ||
114 | L7700/7500/7400/7300/7200 100 | ||
115 | |||
116 | 65nm Core2 Extreme Processors | ||
117 | X7900/7800 100 | ||
118 | |||
119 | 65nm Core Duo Processors | ||
120 | U2500/2400 100 | ||
121 | T2700/2600/2450/2400/2350/2300E/2300/2250/2050 100 | ||
122 | L2500/2400/2300 100 | ||
123 | |||
124 | 65nm Core Solo Processors | ||
125 | U1500/1400/1300 100 | ||
126 | T1400/1350/1300/1250 100 | ||
127 | |||
128 | 65nm Xeon Processors 5000 Quad-Core | ||
129 | X5000 90-95 | ||
130 | E5000 80 | ||
131 | L5000 70 | ||
132 | L5318 95 | ||
133 | |||
134 | 65nm Xeon Processors 5000 Dual-Core | ||
135 | 5080, 5063, 5060, 5050, 5030 80-90 | ||
136 | 5160, 5150, 5148, 5140, 5130, 5120, 5110 80 | ||
137 | L5138 100 | ||
138 | |||
139 | 65nm Celeron Processors | ||
140 | T1700/1600 100 | ||
141 | 560/550/540/530 100 | ||