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authorFrancis Galiegue <fgaliegue@gmail.com>2010-04-22 18:08:02 -0400
committerJiri Kosina <jkosina@suse.cz>2010-04-22 20:09:52 -0400
commita33f32244d8550da8b4a26e277ce07d5c6d158b5 (patch)
tree2b24b891e48ae791446fef6d1b9e520190c03c62 /Documentation/cachetlb.txt
parent6c9468e9eb1252eaefd94ce7f06e1be9b0b641b1 (diff)
Documentation/: it's -> its where appropriate
Fix obvious cases of "it's" being used when "its" was meant. Signed-off-by: Francis Galiegue <fgaliegue@gmail.com> Acked-by: Randy Dunlap <rdunlap@xenotime.net> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
Diffstat (limited to 'Documentation/cachetlb.txt')
-rw-r--r--Documentation/cachetlb.txt6
1 files changed, 3 insertions, 3 deletions
diff --git a/Documentation/cachetlb.txt b/Documentation/cachetlb.txt
index 2b5f823abd0..9164ae3b83b 100644
--- a/Documentation/cachetlb.txt
+++ b/Documentation/cachetlb.txt
@@ -5,7 +5,7 @@
5 5
6This document describes the cache/tlb flushing interfaces called 6This document describes the cache/tlb flushing interfaces called
7by the Linux VM subsystem. It enumerates over each interface, 7by the Linux VM subsystem. It enumerates over each interface,
8describes it's intended purpose, and what side effect is expected 8describes its intended purpose, and what side effect is expected
9after the interface is invoked. 9after the interface is invoked.
10 10
11The side effects described below are stated for a uniprocessor 11The side effects described below are stated for a uniprocessor
@@ -231,7 +231,7 @@ require a whole different set of interfaces to handle properly.
231The biggest problem is that of virtual aliasing in the data cache 231The biggest problem is that of virtual aliasing in the data cache
232of a processor. 232of a processor.
233 233
234Is your port susceptible to virtual aliasing in it's D-cache? 234Is your port susceptible to virtual aliasing in its D-cache?
235Well, if your D-cache is virtually indexed, is larger in size than 235Well, if your D-cache is virtually indexed, is larger in size than
236PAGE_SIZE, and does not prevent multiple cache lines for the same 236PAGE_SIZE, and does not prevent multiple cache lines for the same
237physical address from existing at once, you have this problem. 237physical address from existing at once, you have this problem.
@@ -249,7 +249,7 @@ one way to solve this (in particular SPARC_FLAG_MMAPSHARED).
249Next, you have to solve the D-cache aliasing issue for all 249Next, you have to solve the D-cache aliasing issue for all
250other cases. Please keep in mind that fact that, for a given page 250other cases. Please keep in mind that fact that, for a given page
251mapped into some user address space, there is always at least one more 251mapped into some user address space, there is always at least one more
252mapping, that of the kernel in it's linear mapping starting at 252mapping, that of the kernel in its linear mapping starting at
253PAGE_OFFSET. So immediately, once the first user maps a given 253PAGE_OFFSET. So immediately, once the first user maps a given
254physical page into its address space, by implication the D-cache 254physical page into its address space, by implication the D-cache
255aliasing problem has the potential to exist since the kernel already 255aliasing problem has the potential to exist since the kernel already