diff options
author | Benoit Cousson <b-cousson@ti.com> | 2010-09-21 10:07:14 -0400 |
---|---|---|
committer | Kevin Hilman <khilman@deeprootsystems.com> | 2010-11-09 12:31:09 -0500 |
commit | f776471f620a07be234f40288a1fd9932d039e26 (patch) | |
tree | bd50adc2726da73fa89964b365b857afcd91faaa | |
parent | 4fe20e97c8b1082d16b38e9f4c53feeed143ab98 (diff) |
OMAP4: hwmod: add I2C hwmods for OMAP4430
Add hwmod structures for I2C controllers on OMAP4430.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
-rw-r--r-- | arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 237 |
1 files changed, 237 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 7274db4de48..0d5c6eb7e4c 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c | |||
@@ -383,6 +383,238 @@ static struct omap_hwmod omap44xx_l4_wkup_hwmod = { | |||
383 | }; | 383 | }; |
384 | 384 | ||
385 | /* | 385 | /* |
386 | * 'i2c' class | ||
387 | * multimaster high-speed i2c controller | ||
388 | */ | ||
389 | |||
390 | static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = { | ||
391 | .sysc_offs = 0x0010, | ||
392 | .syss_offs = 0x0090, | ||
393 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | ||
394 | SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SOFTRESET | | ||
395 | SYSC_HAS_AUTOIDLE), | ||
396 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | ||
397 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
398 | }; | ||
399 | |||
400 | static struct omap_hwmod_class omap44xx_i2c_hwmod_class = { | ||
401 | .name = "i2c", | ||
402 | .sysc = &omap44xx_i2c_sysc, | ||
403 | }; | ||
404 | |||
405 | /* i2c1 */ | ||
406 | static struct omap_hwmod omap44xx_i2c1_hwmod; | ||
407 | static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = { | ||
408 | { .irq = 56 + OMAP44XX_IRQ_GIC_START }, | ||
409 | }; | ||
410 | |||
411 | static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = { | ||
412 | { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START }, | ||
413 | { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START }, | ||
414 | }; | ||
415 | |||
416 | static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = { | ||
417 | { | ||
418 | .pa_start = 0x48070000, | ||
419 | .pa_end = 0x480700ff, | ||
420 | .flags = ADDR_TYPE_RT | ||
421 | }, | ||
422 | }; | ||
423 | |||
424 | /* l4_per -> i2c1 */ | ||
425 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = { | ||
426 | .master = &omap44xx_l4_per_hwmod, | ||
427 | .slave = &omap44xx_i2c1_hwmod, | ||
428 | .clk = "l4_div_ck", | ||
429 | .addr = omap44xx_i2c1_addrs, | ||
430 | .addr_cnt = ARRAY_SIZE(omap44xx_i2c1_addrs), | ||
431 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
432 | }; | ||
433 | |||
434 | /* i2c1 slave ports */ | ||
435 | static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = { | ||
436 | &omap44xx_l4_per__i2c1, | ||
437 | }; | ||
438 | |||
439 | static struct omap_hwmod omap44xx_i2c1_hwmod = { | ||
440 | .name = "i2c1", | ||
441 | .class = &omap44xx_i2c_hwmod_class, | ||
442 | .flags = HWMOD_INIT_NO_RESET, | ||
443 | .mpu_irqs = omap44xx_i2c1_irqs, | ||
444 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c1_irqs), | ||
445 | .sdma_reqs = omap44xx_i2c1_sdma_reqs, | ||
446 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs), | ||
447 | .main_clk = "i2c1_fck", | ||
448 | .prcm = { | ||
449 | .omap4 = { | ||
450 | .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL, | ||
451 | }, | ||
452 | }, | ||
453 | .slaves = omap44xx_i2c1_slaves, | ||
454 | .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves), | ||
455 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
456 | }; | ||
457 | |||
458 | /* i2c2 */ | ||
459 | static struct omap_hwmod omap44xx_i2c2_hwmod; | ||
460 | static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = { | ||
461 | { .irq = 57 + OMAP44XX_IRQ_GIC_START }, | ||
462 | }; | ||
463 | |||
464 | static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = { | ||
465 | { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START }, | ||
466 | { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START }, | ||
467 | }; | ||
468 | |||
469 | static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = { | ||
470 | { | ||
471 | .pa_start = 0x48072000, | ||
472 | .pa_end = 0x480720ff, | ||
473 | .flags = ADDR_TYPE_RT | ||
474 | }, | ||
475 | }; | ||
476 | |||
477 | /* l4_per -> i2c2 */ | ||
478 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = { | ||
479 | .master = &omap44xx_l4_per_hwmod, | ||
480 | .slave = &omap44xx_i2c2_hwmod, | ||
481 | .clk = "l4_div_ck", | ||
482 | .addr = omap44xx_i2c2_addrs, | ||
483 | .addr_cnt = ARRAY_SIZE(omap44xx_i2c2_addrs), | ||
484 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
485 | }; | ||
486 | |||
487 | /* i2c2 slave ports */ | ||
488 | static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = { | ||
489 | &omap44xx_l4_per__i2c2, | ||
490 | }; | ||
491 | |||
492 | static struct omap_hwmod omap44xx_i2c2_hwmod = { | ||
493 | .name = "i2c2", | ||
494 | .class = &omap44xx_i2c_hwmod_class, | ||
495 | .flags = HWMOD_INIT_NO_RESET, | ||
496 | .mpu_irqs = omap44xx_i2c2_irqs, | ||
497 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c2_irqs), | ||
498 | .sdma_reqs = omap44xx_i2c2_sdma_reqs, | ||
499 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs), | ||
500 | .main_clk = "i2c2_fck", | ||
501 | .prcm = { | ||
502 | .omap4 = { | ||
503 | .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL, | ||
504 | }, | ||
505 | }, | ||
506 | .slaves = omap44xx_i2c2_slaves, | ||
507 | .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves), | ||
508 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
509 | }; | ||
510 | |||
511 | /* i2c3 */ | ||
512 | static struct omap_hwmod omap44xx_i2c3_hwmod; | ||
513 | static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = { | ||
514 | { .irq = 61 + OMAP44XX_IRQ_GIC_START }, | ||
515 | }; | ||
516 | |||
517 | static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = { | ||
518 | { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START }, | ||
519 | { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START }, | ||
520 | }; | ||
521 | |||
522 | static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = { | ||
523 | { | ||
524 | .pa_start = 0x48060000, | ||
525 | .pa_end = 0x480600ff, | ||
526 | .flags = ADDR_TYPE_RT | ||
527 | }, | ||
528 | }; | ||
529 | |||
530 | /* l4_per -> i2c3 */ | ||
531 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = { | ||
532 | .master = &omap44xx_l4_per_hwmod, | ||
533 | .slave = &omap44xx_i2c3_hwmod, | ||
534 | .clk = "l4_div_ck", | ||
535 | .addr = omap44xx_i2c3_addrs, | ||
536 | .addr_cnt = ARRAY_SIZE(omap44xx_i2c3_addrs), | ||
537 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
538 | }; | ||
539 | |||
540 | /* i2c3 slave ports */ | ||
541 | static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = { | ||
542 | &omap44xx_l4_per__i2c3, | ||
543 | }; | ||
544 | |||
545 | static struct omap_hwmod omap44xx_i2c3_hwmod = { | ||
546 | .name = "i2c3", | ||
547 | .class = &omap44xx_i2c_hwmod_class, | ||
548 | .flags = HWMOD_INIT_NO_RESET, | ||
549 | .mpu_irqs = omap44xx_i2c3_irqs, | ||
550 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c3_irqs), | ||
551 | .sdma_reqs = omap44xx_i2c3_sdma_reqs, | ||
552 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs), | ||
553 | .main_clk = "i2c3_fck", | ||
554 | .prcm = { | ||
555 | .omap4 = { | ||
556 | .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL, | ||
557 | }, | ||
558 | }, | ||
559 | .slaves = omap44xx_i2c3_slaves, | ||
560 | .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves), | ||
561 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
562 | }; | ||
563 | |||
564 | /* i2c4 */ | ||
565 | static struct omap_hwmod omap44xx_i2c4_hwmod; | ||
566 | static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = { | ||
567 | { .irq = 62 + OMAP44XX_IRQ_GIC_START }, | ||
568 | }; | ||
569 | |||
570 | static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = { | ||
571 | { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START }, | ||
572 | { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START }, | ||
573 | }; | ||
574 | |||
575 | static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = { | ||
576 | { | ||
577 | .pa_start = 0x48350000, | ||
578 | .pa_end = 0x483500ff, | ||
579 | .flags = ADDR_TYPE_RT | ||
580 | }, | ||
581 | }; | ||
582 | |||
583 | /* l4_per -> i2c4 */ | ||
584 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = { | ||
585 | .master = &omap44xx_l4_per_hwmod, | ||
586 | .slave = &omap44xx_i2c4_hwmod, | ||
587 | .clk = "l4_div_ck", | ||
588 | .addr = omap44xx_i2c4_addrs, | ||
589 | .addr_cnt = ARRAY_SIZE(omap44xx_i2c4_addrs), | ||
590 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
591 | }; | ||
592 | |||
593 | /* i2c4 slave ports */ | ||
594 | static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = { | ||
595 | &omap44xx_l4_per__i2c4, | ||
596 | }; | ||
597 | |||
598 | static struct omap_hwmod omap44xx_i2c4_hwmod = { | ||
599 | .name = "i2c4", | ||
600 | .class = &omap44xx_i2c_hwmod_class, | ||
601 | .flags = HWMOD_INIT_NO_RESET, | ||
602 | .mpu_irqs = omap44xx_i2c4_irqs, | ||
603 | .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c4_irqs), | ||
604 | .sdma_reqs = omap44xx_i2c4_sdma_reqs, | ||
605 | .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs), | ||
606 | .main_clk = "i2c4_fck", | ||
607 | .prcm = { | ||
608 | .omap4 = { | ||
609 | .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL, | ||
610 | }, | ||
611 | }, | ||
612 | .slaves = omap44xx_i2c4_slaves, | ||
613 | .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves), | ||
614 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
615 | }; | ||
616 | |||
617 | /* | ||
386 | * 'mpu_bus' class | 618 | * 'mpu_bus' class |
387 | * instance(s): mpu_private | 619 | * instance(s): mpu_private |
388 | */ | 620 | */ |
@@ -826,6 +1058,11 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = { | |||
826 | &omap44xx_l4_cfg_hwmod, | 1058 | &omap44xx_l4_cfg_hwmod, |
827 | &omap44xx_l4_per_hwmod, | 1059 | &omap44xx_l4_per_hwmod, |
828 | &omap44xx_l4_wkup_hwmod, | 1060 | &omap44xx_l4_wkup_hwmod, |
1061 | /* i2c class */ | ||
1062 | &omap44xx_i2c1_hwmod, | ||
1063 | &omap44xx_i2c2_hwmod, | ||
1064 | &omap44xx_i2c3_hwmod, | ||
1065 | &omap44xx_i2c4_hwmod, | ||
829 | /* mpu_bus class */ | 1066 | /* mpu_bus class */ |
830 | &omap44xx_mpu_private_hwmod, | 1067 | &omap44xx_mpu_private_hwmod, |
831 | 1068 | ||